Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

17107366

1

T2

10

T3

28337

T4

2504

full_word

167932966

1

T1

6009

T2

136

T3

1487

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	185040052	1			T1	6009		T2	146		T3	29824
auto[TlIntgErrCmd]	92	1			T66	4		T67	5		T68	4
auto[TlIntgErrData]	102	1			T66	3		T67	4		T68	3
auto[TlIntgErrBoth]	86	1			T66	3		T67	1		T68	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

89497294

1

T1

3058

T2

66

T3

14686

auto[1]

95543038

1

T1

2951

T2

80

T3

15138

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8375174	1			T2	4		T3	14573		T4	1249
auto[TlIntgErrNone]	partial	auto[1]	8731937	1			T2	6		T3	13764		T4	1255
auto[TlIntgErrNone]	full_word	auto[0]	81121994	1			T1	3058		T2	62		T3	113
auto[TlIntgErrNone]	full_word	auto[1]	86810947	1			T1	2951		T2	74		T3	1374
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T66	2		T67	2		T135	2
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T66	2		T67	1		T68	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T67	2		T68	1		T138	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T146	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	41	1			T66	2		T67	2		T68	2
auto[TlIntgErrData]	partial	auto[1]	48	1			T66	1		T67	1		T68	1
auto[TlIntgErrData]	full_word	auto[0]	9	1			T137	2		T138	2		T147	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T67	1		T137	1		T138	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T66	1		T68	1		T135	2
auto[TlIntgErrBoth]	partial	auto[1]	48	1			T66	2		T67	1		T68	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T139	1		T144	1		T148	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T137	1		T149	1		-	-