Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	870380	1			T4	63		T5	4		T11	24
auto[1]	11222305	1			T1	3058		T2	6		T4	502
auto[2]	663241	1			T2	1		T4	26		T5	1
auto[3]	10949227	1			T1	2950		T2	2		T4	451

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14548330	1			T1	6008		T2	8		T4	781
auto[1]	2259846	1			T4	82		T9	110		T10	10278
auto[2]	2295171	1			T2	1		T4	161		T5	3
auto[3]	4601806	1			T4	18		T5	1		T9	26

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9329405

1

T1

6008

T2

9

T4

1042

auto[1]

14375748

1

T10

124155

T19

1

T64

200040

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	328679	1			T4	52		T5	3		T11	21
auto[0]	auto[0]	auto[1]	34510	1			T4	4		T11	2		T6	2
auto[0]	auto[0]	auto[2]	34117	1			T4	7		T5	1		T6	1
auto[0]	auto[0]	auto[3]	56851	1			T11	1		T45	857		T27	38
auto[0]	auto[1]	auto[0]	3307639	1			T1	3058		T2	6		T4	396
auto[0]	auto[1]	auto[1]	347014	1			T4	58		T9	46		T11	21
auto[0]	auto[1]	auto[2]	357421	1			T4	39		T5	2		T9	69
auto[0]	auto[1]	auto[3]	349148	1			T4	9		T9	14		T11	2
auto[0]	auto[2]	auto[0]	239484	1			T6	6		T27	2078		T90	1359
auto[0]	auto[2]	auto[1]	28133	1			T27	212		T90	135		T20	1926
auto[0]	auto[2]	auto[2]	30772	1			T2	1		T4	25		T11	17
auto[0]	auto[2]	auto[3]	39244	1			T4	1		T5	1		T11	1
auto[0]	auto[3]	auto[0]	3161766	1			T1	2950		T2	2		T4	333
auto[0]	auto[3]	auto[1]	339557	1			T4	20		T9	64		T11	10
auto[0]	auto[3]	auto[2]	359715	1			T4	90		T9	65		T11	42
auto[0]	auto[3]	auto[3]	315355	1			T4	8		T9	12		T11	1
auto[1]	auto[0]	auto[0]	13909	1			T78	770		T117	105		T159	1
auto[1]	auto[0]	auto[1]	61937	1			T78	3453		T117	427		T156	1
auto[1]	auto[0]	auto[2]	61954	1			T78	3376		T117	427		T158	4145
auto[1]	auto[0]	auto[3]	278423	1			T78	15020		T117	1955		T158	18700
auto[1]	auto[1]	auto[0]	3744536	1			T10	51335		T64	83773		T65	4071
auto[1]	auto[1]	auto[1]	723047	1			T10	5101		T64	7240		T65	17920
auto[1]	auto[1]	auto[2]	693323	1			T10	5239		T64	8287		T65	17719
auto[1]	auto[1]	auto[3]	1700177	1			T10	521		T64	745		T65	80315
auto[1]	auto[2]	auto[0]	10332	1			T78	678		T158	852		T150	1
auto[1]	auto[2]	auto[1]	46316	1			T78	3197		T158	3867		T160	3652
auto[1]	auto[2]	auto[2]	49142	1			T78	2301		T117	395		T158	2850
auto[1]	auto[2]	auto[3]	219818	1			T78	10186		T117	1779		T158	12599
auto[1]	auto[3]	auto[0]	3741985	1			T10	51118		T19	1		T64	83856
auto[1]	auto[3]	auto[1]	679332	1			T10	5177		T64	8114		T65	17825
auto[1]	auto[3]	auto[2]	708727	1			T10	5165		T64	7289		T65	17897
auto[1]	auto[3]	auto[3]	1642790	1			T10	499		T64	736		T65	80393