Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1323151809	214312	0	0
ctrl_regwen_rd_A	1323151809	4903	0	0
exec_rd_A	1323151809	4457	0	0
exec_regwen_rd_A	1323151809	4660	0	0
readback_rd_A	1323151809	3043	0	0
readback_regwen_rd_A	1323151809	2740	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1323151809	214312	0	0
T20	218351	0	0	0
T24	98749	4579	0	0
T25	0	4945	0	0
T26	0	4206	0	0
T29	838778	0	0	0
T47	590493	0	0	0
T49	692882	0	0	0
T51	0	6053	0	0
T52	0	3157	0	0
T53	0	7234	0	0
T54	0	6049	0	0
T63	0	11141	0	0
T72	0	1365	0	0
T73	0	1809	0	0
T74	165534	0	0	0
T75	73811	0	0	0
T76	72934	0	0	0
T77	514849	0	0	0
T78	169623	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1323151809	4903	0	0
T52	0	230	0	0
T53	0	583	0	0
T54	183602	544	0	0
T106	101788	0	0	0
T119	0	89	0	0
T120	0	300	0	0
T121	0	208	0	0
T122	0	91	0	0
T123	0	429	0	0
T124	0	302	0	0
T125	0	193	0	0
T126	64112	0	0	0
T127	73954	0	0	0
T128	173760	0	0	0
T129	838183	0	0	0
T130	45305	0	0	0
T131	144357	0	0	0
T132	394071	0	0	0
T133	70060	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1323151809	4457	0	0
T52	0	220	0	0
T53	0	443	0	0
T54	183602	461	0	0
T106	101788	0	0	0
T119	0	119	0	0
T120	0	279	0	0
T121	0	168	0	0
T122	0	47	0	0
T123	0	380	0	0
T124	0	274	0	0
T125	0	160	0	0
T126	64112	0	0	0
T127	73954	0	0	0
T128	173760	0	0	0
T129	838183	0	0	0
T130	45305	0	0	0
T131	144357	0	0	0
T132	394071	0	0	0
T133	70060	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1323151809	4660	0	0
T52	0	230	0	0
T53	0	539	0	0
T54	183602	466	0	0
T106	101788	0	0	0
T119	0	135	0	0
T120	0	227	0	0
T121	0	148	0	0
T122	0	98	0	0
T123	0	389	0	0
T124	0	190	0	0
T125	0	141	0	0
T126	64112	0	0	0
T127	73954	0	0	0
T128	173760	0	0	0
T129	838183	0	0	0
T130	45305	0	0	0
T131	144357	0	0	0
T132	394071	0	0	0
T133	70060	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1323151809	3043	0	0
T52	0	226	0	0
T53	0	542	0	0
T54	183602	480	0	0
T106	101788	0	0	0
T119	0	127	0	0
T120	0	209	0	0
T121	0	86	0	0
T122	0	60	0	0
T123	0	363	0	0
T124	0	285	0	0
T125	0	132	0	0
T126	64112	0	0	0
T127	73954	0	0	0
T128	173760	0	0	0
T129	838183	0	0	0
T130	45305	0	0	0
T131	144357	0	0	0
T132	394071	0	0	0
T133	70060	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1323151809	2740	0	0
T52	0	219	0	0
T53	0	444	0	0
T54	183602	327	0	0
T106	101788	0	0	0
T119	0	97	0	0
T120	0	216	0	0
T121	0	135	0	0
T122	0	53	0	0
T123	0	380	0	0
T124	0	192	0	0
T125	0	169	0	0
T126	64112	0	0	0
T127	73954	0	0	0
T128	173760	0	0	0
T129	838183	0	0	0
T130	45305	0	0	0
T131	144357	0	0	0
T132	394071	0	0	0
T133	70060	0	0	0