Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44


Total test records in report: 1034
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T794 /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3930759523 Jun 26 04:37:35 PM PDT 24 Jun 26 04:40:00 PM PDT 24 11045687521 ps
T795 /workspace/coverage/default/20.sram_ctrl_alert_test.2955824692 Jun 26 04:37:12 PM PDT 24 Jun 26 04:37:18 PM PDT 24 20841994 ps
T796 /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3004154401 Jun 26 04:37:28 PM PDT 24 Jun 26 04:37:54 PM PDT 24 3546691550 ps
T797 /workspace/coverage/default/4.sram_ctrl_stress_all.940717130 Jun 26 04:36:38 PM PDT 24 Jun 26 05:29:06 PM PDT 24 51131881155 ps
T798 /workspace/coverage/default/0.sram_ctrl_mem_walk.3798802041 Jun 26 04:36:40 PM PDT 24 Jun 26 04:43:03 PM PDT 24 82745306344 ps
T799 /workspace/coverage/default/23.sram_ctrl_multiple_keys.1259944378 Jun 26 04:37:14 PM PDT 24 Jun 26 04:51:33 PM PDT 24 4617794670 ps
T800 /workspace/coverage/default/10.sram_ctrl_multiple_keys.3614292852 Jun 26 04:36:53 PM PDT 24 Jun 26 04:57:37 PM PDT 24 11032676880 ps
T801 /workspace/coverage/default/17.sram_ctrl_lc_escalation.3399177997 Jun 26 04:37:11 PM PDT 24 Jun 26 04:38:21 PM PDT 24 27553503689 ps
T802 /workspace/coverage/default/44.sram_ctrl_multiple_keys.271856484 Jun 26 04:38:34 PM PDT 24 Jun 26 04:45:50 PM PDT 24 6638681095 ps
T803 /workspace/coverage/default/22.sram_ctrl_max_throughput.3802100518 Jun 26 04:37:14 PM PDT 24 Jun 26 04:37:58 PM PDT 24 737021697 ps
T804 /workspace/coverage/default/40.sram_ctrl_mem_walk.3822076633 Jun 26 04:38:14 PM PDT 24 Jun 26 04:44:06 PM PDT 24 44084751154 ps
T805 /workspace/coverage/default/34.sram_ctrl_max_throughput.3889443022 Jun 26 04:37:45 PM PDT 24 Jun 26 04:38:04 PM PDT 24 774087774 ps
T806 /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.25537067 Jun 26 04:36:53 PM PDT 24 Jun 26 04:37:07 PM PDT 24 202551946 ps
T807 /workspace/coverage/default/30.sram_ctrl_stress_pipeline.3879404640 Jun 26 04:37:39 PM PDT 24 Jun 26 04:42:47 PM PDT 24 4828702188 ps
T808 /workspace/coverage/default/37.sram_ctrl_stress_all.1681571782 Jun 26 04:38:01 PM PDT 24 Jun 26 05:07:16 PM PDT 24 70740089081 ps
T809 /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2214222150 Jun 26 04:36:48 PM PDT 24 Jun 26 04:38:17 PM PDT 24 2829011799 ps
T810 /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.3254003998 Jun 26 04:38:05 PM PDT 24 Jun 26 04:46:24 PM PDT 24 37470583469 ps
T811 /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1279279706 Jun 26 04:38:21 PM PDT 24 Jun 26 04:40:26 PM PDT 24 2365378741 ps
T812 /workspace/coverage/default/16.sram_ctrl_mem_walk.412884376 Jun 26 04:37:04 PM PDT 24 Jun 26 04:41:19 PM PDT 24 4151627645 ps
T813 /workspace/coverage/default/12.sram_ctrl_max_throughput.761701108 Jun 26 04:36:59 PM PDT 24 Jun 26 04:37:31 PM PDT 24 1455221489 ps
T814 /workspace/coverage/default/18.sram_ctrl_mem_partial_access.2345407683 Jun 26 04:37:03 PM PDT 24 Jun 26 04:38:27 PM PDT 24 1394804648 ps
T815 /workspace/coverage/default/34.sram_ctrl_ram_cfg.2423251281 Jun 26 04:37:46 PM PDT 24 Jun 26 04:37:51 PM PDT 24 690314886 ps
T816 /workspace/coverage/default/3.sram_ctrl_bijection.3248698195 Jun 26 04:36:49 PM PDT 24 Jun 26 04:55:01 PM PDT 24 64157642313 ps
T817 /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.727651058 Jun 26 04:37:10 PM PDT 24 Jun 26 04:37:59 PM PDT 24 3872053672 ps
T818 /workspace/coverage/default/42.sram_ctrl_stress_pipeline.2626086526 Jun 26 04:38:25 PM PDT 24 Jun 26 04:41:09 PM PDT 24 10085760026 ps
T819 /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.10555265 Jun 26 04:38:48 PM PDT 24 Jun 26 04:39:07 PM PDT 24 501988420 ps
T820 /workspace/coverage/default/47.sram_ctrl_max_throughput.1550992927 Jun 26 04:38:52 PM PDT 24 Jun 26 04:39:12 PM PDT 24 701814617 ps
T821 /workspace/coverage/default/43.sram_ctrl_lc_escalation.722632193 Jun 26 04:38:27 PM PDT 24 Jun 26 04:39:14 PM PDT 24 15589984307 ps
T822 /workspace/coverage/default/5.sram_ctrl_bijection.1229543750 Jun 26 04:36:44 PM PDT 24 Jun 26 04:58:15 PM PDT 24 157982332690 ps
T823 /workspace/coverage/default/29.sram_ctrl_executable.645500976 Jun 26 04:37:34 PM PDT 24 Jun 26 04:45:32 PM PDT 24 32723095950 ps
T824 /workspace/coverage/default/19.sram_ctrl_stress_pipeline.2263879894 Jun 26 04:36:51 PM PDT 24 Jun 26 04:42:42 PM PDT 24 4546676554 ps
T825 /workspace/coverage/default/7.sram_ctrl_smoke.137338285 Jun 26 04:36:36 PM PDT 24 Jun 26 04:36:53 PM PDT 24 2079489120 ps
T826 /workspace/coverage/default/22.sram_ctrl_stress_all.3462506073 Jun 26 04:37:06 PM PDT 24 Jun 26 06:27:53 PM PDT 24 96688651675 ps
T827 /workspace/coverage/default/9.sram_ctrl_executable.573750514 Jun 26 04:37:01 PM PDT 24 Jun 26 05:00:12 PM PDT 24 26245436038 ps
T828 /workspace/coverage/default/2.sram_ctrl_stress_pipeline.1791003592 Jun 26 04:36:35 PM PDT 24 Jun 26 04:39:34 PM PDT 24 3254118826 ps
T829 /workspace/coverage/default/13.sram_ctrl_regwen.3711735937 Jun 26 04:36:51 PM PDT 24 Jun 26 05:06:37 PM PDT 24 14272290185 ps
T830 /workspace/coverage/default/10.sram_ctrl_mem_walk.4274722168 Jun 26 04:37:01 PM PDT 24 Jun 26 04:39:12 PM PDT 24 12330283740 ps
T831 /workspace/coverage/default/48.sram_ctrl_mem_walk.3735400502 Jun 26 04:38:59 PM PDT 24 Jun 26 04:42:06 PM PDT 24 46983347785 ps
T832 /workspace/coverage/default/14.sram_ctrl_smoke.1160228387 Jun 26 04:37:10 PM PDT 24 Jun 26 04:37:49 PM PDT 24 1341822281 ps
T833 /workspace/coverage/default/37.sram_ctrl_mem_partial_access.1707975814 Jun 26 04:38:00 PM PDT 24 Jun 26 04:40:37 PM PDT 24 5093156905 ps
T834 /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.4078804238 Jun 26 04:37:56 PM PDT 24 Jun 26 04:41:37 PM PDT 24 38513121702 ps
T835 /workspace/coverage/default/18.sram_ctrl_stress_pipeline.1876678584 Jun 26 04:37:19 PM PDT 24 Jun 26 04:43:23 PM PDT 24 22359780860 ps
T836 /workspace/coverage/default/12.sram_ctrl_access_during_key_req.1336661993 Jun 26 04:36:53 PM PDT 24 Jun 26 05:03:56 PM PDT 24 142487600453 ps
T837 /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.169536573 Jun 26 04:37:09 PM PDT 24 Jun 26 04:47:52 PM PDT 24 46911208285 ps
T838 /workspace/coverage/default/2.sram_ctrl_regwen.1950811318 Jun 26 04:36:41 PM PDT 24 Jun 26 04:53:57 PM PDT 24 31936158104 ps
T839 /workspace/coverage/default/15.sram_ctrl_alert_test.1800901737 Jun 26 04:36:47 PM PDT 24 Jun 26 04:36:56 PM PDT 24 14107026 ps
T840 /workspace/coverage/default/40.sram_ctrl_bijection.2744174816 Jun 26 04:38:11 PM PDT 24 Jun 26 04:46:16 PM PDT 24 31325300229 ps
T841 /workspace/coverage/default/44.sram_ctrl_mem_walk.1154030716 Jun 26 04:38:37 PM PDT 24 Jun 26 04:40:47 PM PDT 24 9878739037 ps
T842 /workspace/coverage/default/41.sram_ctrl_multiple_keys.1214447461 Jun 26 04:38:12 PM PDT 24 Jun 26 04:53:12 PM PDT 24 39457012615 ps
T843 /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.1352115953 Jun 26 04:38:03 PM PDT 24 Jun 26 04:41:17 PM PDT 24 16748643232 ps
T844 /workspace/coverage/default/5.sram_ctrl_alert_test.653145414 Jun 26 04:36:43 PM PDT 24 Jun 26 04:36:45 PM PDT 24 20413276 ps
T845 /workspace/coverage/default/22.sram_ctrl_partial_access.1786450401 Jun 26 04:37:17 PM PDT 24 Jun 26 04:39:04 PM PDT 24 1927421153 ps
T846 /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2119531002 Jun 26 04:39:02 PM PDT 24 Jun 26 04:39:11 PM PDT 24 228760251 ps
T847 /workspace/coverage/default/2.sram_ctrl_alert_test.1017814479 Jun 26 04:36:54 PM PDT 24 Jun 26 04:36:58 PM PDT 24 61904437 ps
T848 /workspace/coverage/default/37.sram_ctrl_lc_escalation.1406188068 Jun 26 04:37:56 PM PDT 24 Jun 26 04:39:08 PM PDT 24 24027985578 ps
T849 /workspace/coverage/default/17.sram_ctrl_max_throughput.1331851305 Jun 26 04:37:09 PM PDT 24 Jun 26 04:37:50 PM PDT 24 736858566 ps
T850 /workspace/coverage/default/18.sram_ctrl_ram_cfg.3852739266 Jun 26 04:37:35 PM PDT 24 Jun 26 04:37:40 PM PDT 24 1462080737 ps
T851 /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2011785761 Jun 26 04:36:53 PM PDT 24 Jun 26 04:37:12 PM PDT 24 455304355 ps
T852 /workspace/coverage/default/49.sram_ctrl_smoke.1298839570 Jun 26 04:39:04 PM PDT 24 Jun 26 04:39:20 PM PDT 24 504233844 ps
T853 /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.4174382961 Jun 26 04:38:07 PM PDT 24 Jun 26 04:40:38 PM PDT 24 12977725036 ps
T854 /workspace/coverage/default/27.sram_ctrl_mem_partial_access.3923337701 Jun 26 04:37:18 PM PDT 24 Jun 26 04:38:48 PM PDT 24 5458650961 ps
T855 /workspace/coverage/default/31.sram_ctrl_stress_all.1870823516 Jun 26 04:37:37 PM PDT 24 Jun 26 05:27:49 PM PDT 24 136170959404 ps
T856 /workspace/coverage/default/23.sram_ctrl_stress_all.1356722407 Jun 26 04:37:31 PM PDT 24 Jun 26 06:36:05 PM PDT 24 101213419336 ps
T857 /workspace/coverage/default/3.sram_ctrl_multiple_keys.735408722 Jun 26 04:36:35 PM PDT 24 Jun 26 04:52:06 PM PDT 24 77548436066 ps
T858 /workspace/coverage/default/14.sram_ctrl_stress_pipeline.1902903306 Jun 26 04:37:01 PM PDT 24 Jun 26 04:40:35 PM PDT 24 3312594303 ps
T859 /workspace/coverage/default/13.sram_ctrl_lc_escalation.59430970 Jun 26 04:36:59 PM PDT 24 Jun 26 04:37:31 PM PDT 24 5108944487 ps
T860 /workspace/coverage/default/30.sram_ctrl_bijection.2926868898 Jun 26 04:37:38 PM PDT 24 Jun 26 04:46:27 PM PDT 24 50617237861 ps
T861 /workspace/coverage/default/42.sram_ctrl_partial_access.339337404 Jun 26 04:38:21 PM PDT 24 Jun 26 04:39:08 PM PDT 24 1975267230 ps
T862 /workspace/coverage/default/3.sram_ctrl_executable.1661079234 Jun 26 04:36:33 PM PDT 24 Jun 26 04:47:55 PM PDT 24 50461554052 ps
T863 /workspace/coverage/default/33.sram_ctrl_max_throughput.1296369515 Jun 26 04:37:41 PM PDT 24 Jun 26 04:40:04 PM PDT 24 3062697019 ps
T864 /workspace/coverage/default/38.sram_ctrl_lc_escalation.152862126 Jun 26 04:38:02 PM PDT 24 Jun 26 04:39:13 PM PDT 24 12096856840 ps
T865 /workspace/coverage/default/20.sram_ctrl_access_during_key_req.1402648186 Jun 26 04:37:13 PM PDT 24 Jun 26 04:56:35 PM PDT 24 45712476282 ps
T866 /workspace/coverage/default/27.sram_ctrl_max_throughput.1035021189 Jun 26 04:37:24 PM PDT 24 Jun 26 04:37:55 PM PDT 24 779734952 ps
T867 /workspace/coverage/default/31.sram_ctrl_mem_walk.2133853874 Jun 26 04:37:36 PM PDT 24 Jun 26 04:40:05 PM PDT 24 15024539907 ps
T868 /workspace/coverage/default/36.sram_ctrl_regwen.2158272286 Jun 26 04:37:58 PM PDT 24 Jun 26 04:38:39 PM PDT 24 1673349840 ps
T869 /workspace/coverage/default/25.sram_ctrl_max_throughput.2794713411 Jun 26 04:37:08 PM PDT 24 Jun 26 04:38:28 PM PDT 24 2554766949 ps
T870 /workspace/coverage/default/25.sram_ctrl_smoke.1815877451 Jun 26 04:37:09 PM PDT 24 Jun 26 04:37:37 PM PDT 24 4123483975 ps
T871 /workspace/coverage/default/1.sram_ctrl_alert_test.1960714517 Jun 26 04:36:26 PM PDT 24 Jun 26 04:36:28 PM PDT 24 32264642 ps
T872 /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.2294823698 Jun 26 04:37:36 PM PDT 24 Jun 26 04:45:23 PM PDT 24 22023123921 ps
T873 /workspace/coverage/default/41.sram_ctrl_smoke.1842694107 Jun 26 04:38:14 PM PDT 24 Jun 26 04:39:17 PM PDT 24 2937521663 ps
T874 /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2915032559 Jun 26 04:36:48 PM PDT 24 Jun 26 04:45:47 PM PDT 24 38353055856 ps
T875 /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.4275155472 Jun 26 04:38:48 PM PDT 24 Jun 26 04:38:55 PM PDT 24 671953511 ps
T876 /workspace/coverage/default/14.sram_ctrl_stress_all.2176850494 Jun 26 04:36:57 PM PDT 24 Jun 26 05:35:09 PM PDT 24 64717461031 ps
T877 /workspace/coverage/default/49.sram_ctrl_bijection.1113079485 Jun 26 04:39:03 PM PDT 24 Jun 26 05:25:12 PM PDT 24 165241898813 ps
T878 /workspace/coverage/default/33.sram_ctrl_executable.3483723472 Jun 26 04:37:44 PM PDT 24 Jun 26 05:02:02 PM PDT 24 45954398293 ps
T879 /workspace/coverage/default/35.sram_ctrl_bijection.3145829984 Jun 26 04:37:53 PM PDT 24 Jun 26 05:01:32 PM PDT 24 92566577570 ps
T880 /workspace/coverage/default/16.sram_ctrl_partial_access.4066375050 Jun 26 04:37:13 PM PDT 24 Jun 26 04:38:03 PM PDT 24 1630543695 ps
T881 /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3626726295 Jun 26 04:38:56 PM PDT 24 Jun 26 04:39:18 PM PDT 24 1442455203 ps
T882 /workspace/coverage/default/45.sram_ctrl_alert_test.1400036807 Jun 26 04:38:46 PM PDT 24 Jun 26 04:38:48 PM PDT 24 45092185 ps
T883 /workspace/coverage/default/32.sram_ctrl_partial_access.1519285823 Jun 26 04:37:32 PM PDT 24 Jun 26 04:37:46 PM PDT 24 523948774 ps
T884 /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.2052767672 Jun 26 04:37:38 PM PDT 24 Jun 26 04:41:27 PM PDT 24 13794622119 ps
T885 /workspace/coverage/default/9.sram_ctrl_ram_cfg.4044540994 Jun 26 04:36:48 PM PDT 24 Jun 26 04:36:53 PM PDT 24 352073218 ps
T886 /workspace/coverage/default/4.sram_ctrl_lc_escalation.1952928092 Jun 26 04:36:40 PM PDT 24 Jun 26 04:36:49 PM PDT 24 5103021192 ps
T887 /workspace/coverage/default/0.sram_ctrl_alert_test.3195256536 Jun 26 04:36:48 PM PDT 24 Jun 26 04:36:51 PM PDT 24 12704668 ps
T888 /workspace/coverage/default/46.sram_ctrl_stress_all.3363827388 Jun 26 04:38:48 PM PDT 24 Jun 26 05:59:27 PM PDT 24 399794957282 ps
T889 /workspace/coverage/default/37.sram_ctrl_partial_access.1071104142 Jun 26 04:37:58 PM PDT 24 Jun 26 04:38:04 PM PDT 24 1593359780 ps
T890 /workspace/coverage/default/27.sram_ctrl_lc_escalation.1036613852 Jun 26 04:37:41 PM PDT 24 Jun 26 04:38:01 PM PDT 24 8840883548 ps
T891 /workspace/coverage/default/28.sram_ctrl_regwen.1484883964 Jun 26 04:37:28 PM PDT 24 Jun 26 04:53:43 PM PDT 24 3825482921 ps
T892 /workspace/coverage/default/31.sram_ctrl_mem_partial_access.3734525826 Jun 26 04:37:32 PM PDT 24 Jun 26 04:40:07 PM PDT 24 17567530743 ps
T893 /workspace/coverage/default/47.sram_ctrl_mem_walk.2312926728 Jun 26 04:38:54 PM PDT 24 Jun 26 04:44:20 PM PDT 24 55407126025 ps
T894 /workspace/coverage/default/32.sram_ctrl_mem_partial_access.2450067717 Jun 26 04:37:48 PM PDT 24 Jun 26 04:40:18 PM PDT 24 19707678495 ps
T895 /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.3224299569 Jun 26 04:37:55 PM PDT 24 Jun 26 04:38:11 PM PDT 24 3027882444 ps
T896 /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1590414163 Jun 26 04:38:20 PM PDT 24 Jun 26 04:43:03 PM PDT 24 34135214368 ps
T897 /workspace/coverage/default/33.sram_ctrl_stress_all.2729738676 Jun 26 04:37:44 PM PDT 24 Jun 26 06:11:47 PM PDT 24 97866417112 ps
T898 /workspace/coverage/default/11.sram_ctrl_regwen.2332067703 Jun 26 04:37:35 PM PDT 24 Jun 26 04:47:35 PM PDT 24 8166406347 ps
T899 /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3128470589 Jun 26 04:36:49 PM PDT 24 Jun 26 04:41:21 PM PDT 24 11925104394 ps
T900 /workspace/coverage/default/35.sram_ctrl_smoke.970990576 Jun 26 04:37:50 PM PDT 24 Jun 26 04:39:33 PM PDT 24 453567423 ps
T901 /workspace/coverage/default/20.sram_ctrl_mem_walk.2840065025 Jun 26 04:37:08 PM PDT 24 Jun 26 04:39:49 PM PDT 24 6916568106 ps
T902 /workspace/coverage/default/30.sram_ctrl_access_during_key_req.4032649941 Jun 26 04:37:32 PM PDT 24 Jun 26 04:53:14 PM PDT 24 33491855649 ps
T903 /workspace/coverage/default/17.sram_ctrl_stress_pipeline.3302874085 Jun 26 04:37:06 PM PDT 24 Jun 26 04:41:30 PM PDT 24 4687931447 ps
T904 /workspace/coverage/default/1.sram_ctrl_partial_access.886863842 Jun 26 04:36:33 PM PDT 24 Jun 26 04:37:24 PM PDT 24 1576602676 ps
T905 /workspace/coverage/default/24.sram_ctrl_access_during_key_req.901418682 Jun 26 04:37:14 PM PDT 24 Jun 26 04:57:54 PM PDT 24 58056527679 ps
T906 /workspace/coverage/default/28.sram_ctrl_mem_partial_access.1054144242 Jun 26 04:37:31 PM PDT 24 Jun 26 04:39:30 PM PDT 24 3223752650 ps
T907 /workspace/coverage/default/15.sram_ctrl_bijection.1271662318 Jun 26 04:37:09 PM PDT 24 Jun 26 04:46:45 PM PDT 24 8550247270 ps
T908 /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3814889889 Jun 26 04:36:53 PM PDT 24 Jun 26 04:37:32 PM PDT 24 793375651 ps
T909 /workspace/coverage/default/12.sram_ctrl_partial_access.488466876 Jun 26 04:36:54 PM PDT 24 Jun 26 04:37:11 PM PDT 24 4467162357 ps
T910 /workspace/coverage/default/20.sram_ctrl_bijection.3225719135 Jun 26 04:37:11 PM PDT 24 Jun 26 04:50:01 PM PDT 24 32500790176 ps
T911 /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.381837394 Jun 26 04:39:03 PM PDT 24 Jun 26 04:39:53 PM PDT 24 3045067890 ps
T912 /workspace/coverage/default/3.sram_ctrl_lc_escalation.1019829064 Jun 26 04:36:35 PM PDT 24 Jun 26 04:37:55 PM PDT 24 12684798194 ps
T913 /workspace/coverage/default/45.sram_ctrl_multiple_keys.1747869529 Jun 26 04:38:39 PM PDT 24 Jun 26 04:43:35 PM PDT 24 17598005254 ps
T914 /workspace/coverage/default/12.sram_ctrl_stress_pipeline.1782560196 Jun 26 04:36:48 PM PDT 24 Jun 26 04:41:15 PM PDT 24 23376835571 ps
T915 /workspace/coverage/default/28.sram_ctrl_partial_access.2363535748 Jun 26 04:37:39 PM PDT 24 Jun 26 04:37:57 PM PDT 24 5088863582 ps
T916 /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2146178100 Jun 26 04:38:32 PM PDT 24 Jun 26 04:38:42 PM PDT 24 713800082 ps
T917 /workspace/coverage/default/4.sram_ctrl_partial_access.2316083590 Jun 26 04:36:36 PM PDT 24 Jun 26 04:38:13 PM PDT 24 852328482 ps
T918 /workspace/coverage/default/9.sram_ctrl_partial_access.745666032 Jun 26 04:36:50 PM PDT 24 Jun 26 04:37:11 PM PDT 24 651966747 ps
T919 /workspace/coverage/default/17.sram_ctrl_ram_cfg.4127263588 Jun 26 04:37:07 PM PDT 24 Jun 26 04:37:14 PM PDT 24 5583844704 ps
T920 /workspace/coverage/default/23.sram_ctrl_partial_access.707682368 Jun 26 04:37:19 PM PDT 24 Jun 26 04:39:35 PM PDT 24 1691756994 ps
T921 /workspace/coverage/default/21.sram_ctrl_multiple_keys.1537926648 Jun 26 04:37:10 PM PDT 24 Jun 26 04:57:04 PM PDT 24 29559851764 ps
T922 /workspace/coverage/default/19.sram_ctrl_stress_all.3736957338 Jun 26 04:37:13 PM PDT 24 Jun 26 05:23:05 PM PDT 24 87905012065 ps
T923 /workspace/coverage/default/8.sram_ctrl_max_throughput.322493726 Jun 26 04:36:44 PM PDT 24 Jun 26 04:38:44 PM PDT 24 3633880379 ps
T924 /workspace/coverage/default/15.sram_ctrl_max_throughput.237206406 Jun 26 04:37:04 PM PDT 24 Jun 26 04:37:56 PM PDT 24 750979459 ps
T925 /workspace/coverage/default/10.sram_ctrl_bijection.3787661439 Jun 26 04:36:48 PM PDT 24 Jun 26 05:19:58 PM PDT 24 138891959822 ps
T926 /workspace/coverage/default/32.sram_ctrl_lc_escalation.8217628 Jun 26 04:37:43 PM PDT 24 Jun 26 04:39:15 PM PDT 24 53316551336 ps
T927 /workspace/coverage/default/20.sram_ctrl_stress_all.665757364 Jun 26 04:37:10 PM PDT 24 Jun 26 06:43:51 PM PDT 24 505365445373 ps
T928 /workspace/coverage/default/27.sram_ctrl_stress_all.2986141231 Jun 26 04:37:16 PM PDT 24 Jun 26 05:59:25 PM PDT 24 623162964120 ps
T929 /workspace/coverage/default/26.sram_ctrl_max_throughput.821133708 Jun 26 04:37:31 PM PDT 24 Jun 26 04:37:45 PM PDT 24 720184314 ps
T930 /workspace/coverage/default/6.sram_ctrl_mem_walk.4124624028 Jun 26 04:36:51 PM PDT 24 Jun 26 04:39:50 PM PDT 24 18331286855 ps
T931 /workspace/coverage/default/39.sram_ctrl_access_during_key_req.3373108014 Jun 26 04:38:08 PM PDT 24 Jun 26 05:08:53 PM PDT 24 20222617666 ps
T932 /workspace/coverage/default/23.sram_ctrl_lc_escalation.2600820321 Jun 26 04:37:19 PM PDT 24 Jun 26 04:38:16 PM PDT 24 8006135016 ps
T933 /workspace/coverage/default/14.sram_ctrl_access_during_key_req.4244744691 Jun 26 04:37:01 PM PDT 24 Jun 26 05:04:22 PM PDT 24 30713015518 ps
T934 /workspace/coverage/default/8.sram_ctrl_lc_escalation.2616681253 Jun 26 04:36:47 PM PDT 24 Jun 26 04:38:15 PM PDT 24 24702463401 ps
T935 /workspace/coverage/default/48.sram_ctrl_max_throughput.1984900880 Jun 26 04:38:57 PM PDT 24 Jun 26 04:40:41 PM PDT 24 7527984177 ps
T936 /workspace/coverage/default/42.sram_ctrl_executable.3139441988 Jun 26 04:38:21 PM PDT 24 Jun 26 04:48:55 PM PDT 24 78478386547 ps
T937 /workspace/coverage/default/26.sram_ctrl_mem_partial_access.306325370 Jun 26 04:37:32 PM PDT 24 Jun 26 04:38:57 PM PDT 24 2446227027 ps
T938 /workspace/coverage/default/5.sram_ctrl_ram_cfg.423916149 Jun 26 04:36:40 PM PDT 24 Jun 26 04:36:45 PM PDT 24 4245981916 ps
T939 /workspace/coverage/default/48.sram_ctrl_ram_cfg.1857077379 Jun 26 04:38:58 PM PDT 24 Jun 26 04:39:02 PM PDT 24 348237046 ps
T940 /workspace/coverage/default/1.sram_ctrl_regwen.291568866 Jun 26 04:36:16 PM PDT 24 Jun 26 04:46:37 PM PDT 24 7590546286 ps
T941 /workspace/coverage/default/5.sram_ctrl_partial_access.1370029811 Jun 26 04:36:45 PM PDT 24 Jun 26 04:37:01 PM PDT 24 1126374547 ps
T942 /workspace/coverage/default/43.sram_ctrl_regwen.2498226884 Jun 26 04:38:28 PM PDT 24 Jun 26 04:49:41 PM PDT 24 3320924673 ps
T70 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1112387888 Jun 26 04:36:17 PM PDT 24 Jun 26 04:36:25 PM PDT 24 21083479 ps
T66 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.552681672 Jun 26 04:36:17 PM PDT 24 Jun 26 04:36:22 PM PDT 24 287795333 ps
T71 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.99599388 Jun 26 04:36:15 PM PDT 24 Jun 26 04:36:19 PM PDT 24 28979187 ps
T80 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1160313366 Jun 26 04:36:06 PM PDT 24 Jun 26 04:36:10 PM PDT 24 12588042 ps
T943 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1100345198 Jun 26 04:36:10 PM PDT 24 Jun 26 04:36:17 PM PDT 24 347548780 ps
T944 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.723651423 Jun 26 04:36:21 PM PDT 24 Jun 26 04:36:26 PM PDT 24 256642347 ps
T118 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1490845840 Jun 26 04:35:56 PM PDT 24 Jun 26 04:36:01 PM PDT 24 47825492 ps
T81 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1725421832 Jun 26 04:36:11 PM PDT 24 Jun 26 04:36:41 PM PDT 24 3858873351 ps
T945 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1245302019 Jun 26 04:36:09 PM PDT 24 Jun 26 04:36:15 PM PDT 24 341619537 ps
T82 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3482536363 Jun 26 04:36:42 PM PDT 24 Jun 26 04:36:45 PM PDT 24 64721244 ps
T67 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.4287614865 Jun 26 04:36:18 PM PDT 24 Jun 26 04:36:22 PM PDT 24 184153700 ps
T83 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.970535532 Jun 26 04:36:49 PM PDT 24 Jun 26 04:36:52 PM PDT 24 26637742 ps
T946 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2617641186 Jun 26 04:36:12 PM PDT 24 Jun 26 04:36:20 PM PDT 24 126178117 ps
T110 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3901426770 Jun 26 04:36:20 PM PDT 24 Jun 26 04:36:23 PM PDT 24 85546604 ps
T84 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2181272405 Jun 26 04:36:09 PM PDT 24 Jun 26 04:36:14 PM PDT 24 12524793 ps
T85 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.624977531 Jun 26 04:36:09 PM PDT 24 Jun 26 04:36:39 PM PDT 24 14792878354 ps
T86 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2916142211 Jun 26 04:36:10 PM PDT 24 Jun 26 04:36:14 PM PDT 24 82809184 ps
T111 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2159885562 Jun 26 04:36:22 PM PDT 24 Jun 26 04:36:25 PM PDT 24 80999999 ps
T87 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.897842628 Jun 26 04:36:02 PM PDT 24 Jun 26 04:36:07 PM PDT 24 35135324 ps
T68 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1321725953 Jun 26 04:36:04 PM PDT 24 Jun 26 04:36:09 PM PDT 24 111868891 ps
T947 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1654683750 Jun 26 04:36:17 PM PDT 24 Jun 26 04:36:24 PM PDT 24 373715279 ps
T948 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.367388770 Jun 26 04:36:32 PM PDT 24 Jun 26 04:36:37 PM PDT 24 1494778878 ps
T949 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.442111715 Jun 26 04:36:29 PM PDT 24 Jun 26 04:36:32 PM PDT 24 212388723 ps
T950 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.4203324053 Jun 26 04:36:09 PM PDT 24 Jun 26 04:36:16 PM PDT 24 1288648297 ps
T112 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3368404242 Jun 26 04:36:11 PM PDT 24 Jun 26 04:36:44 PM PDT 24 14768255423 ps
T951 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3014717499 Jun 26 04:36:00 PM PDT 24 Jun 26 04:36:06 PM PDT 24 43781573 ps
T113 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.546356918 Jun 26 04:36:20 PM PDT 24 Jun 26 04:36:56 PM PDT 24 3698341154 ps
T88 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.805973433 Jun 26 04:36:17 PM PDT 24 Jun 26 04:36:49 PM PDT 24 30797449092 ps
T89 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3916871880 Jun 26 04:36:20 PM PDT 24 Jun 26 04:36:49 PM PDT 24 8031802114 ps
T952 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1577155386 Jun 26 04:36:14 PM PDT 24 Jun 26 04:36:20 PM PDT 24 342844402 ps
T953 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3825790574 Jun 26 04:36:17 PM PDT 24 Jun 26 04:36:21 PM PDT 24 67276426 ps
T954 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1335084895 Jun 26 04:36:13 PM PDT 24 Jun 26 04:36:17 PM PDT 24 200780237 ps
T135 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1535111526 Jun 26 04:36:17 PM PDT 24 Jun 26 04:36:23 PM PDT 24 624322813 ps
T955 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1822522615 Jun 26 04:36:21 PM PDT 24 Jun 26 04:36:24 PM PDT 24 26414977 ps
T142 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3223585922 Jun 26 04:36:19 PM PDT 24 Jun 26 04:36:25 PM PDT 24 1182332475 ps
T92 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.910676616 Jun 26 04:36:06 PM PDT 24 Jun 26 04:36:10 PM PDT 24 52017726 ps
T93 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1620303193 Jun 26 04:36:22 PM PDT 24 Jun 26 04:36:53 PM PDT 24 18507410648 ps
T137 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.125712132 Jun 26 04:36:35 PM PDT 24 Jun 26 04:36:39 PM PDT 24 1063967590 ps
T956 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2288238892 Jun 26 04:36:34 PM PDT 24 Jun 26 04:36:40 PM PDT 24 378129858 ps
T957 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.258812854 Jun 26 04:36:05 PM PDT 24 Jun 26 04:36:37 PM PDT 24 3860432321 ps
T94 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3950642788 Jun 26 04:36:26 PM PDT 24 Jun 26 04:37:31 PM PDT 24 30650351106 ps
T958 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2582503262 Jun 26 04:36:30 PM PDT 24 Jun 26 04:36:31 PM PDT 24 38051575 ps
T959 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3568240097 Jun 26 04:36:01 PM PDT 24 Jun 26 04:36:08 PM PDT 24 349774228 ps
T139 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1293062150 Jun 26 04:36:04 PM PDT 24 Jun 26 04:36:09 PM PDT 24 305090487 ps
T960 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.300260471 Jun 26 04:36:14 PM PDT 24 Jun 26 04:36:23 PM PDT 24 2958466387 ps
T961 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3125449426 Jun 26 04:36:15 PM PDT 24 Jun 26 04:36:23 PM PDT 24 715778056 ps
T962 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.979038712 Jun 26 04:36:01 PM PDT 24 Jun 26 04:36:07 PM PDT 24 180959421 ps
T963 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.827988945 Jun 26 04:36:18 PM PDT 24 Jun 26 04:36:21 PM PDT 24 20897249 ps
T964 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3192998508 Jun 26 04:35:52 PM PDT 24 Jun 26 04:35:57 PM PDT 24 108897839 ps
T138 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1937085868 Jun 26 04:36:23 PM PDT 24 Jun 26 04:36:27 PM PDT 24 286932209 ps
T965 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2372882298 Jun 26 04:36:07 PM PDT 24 Jun 26 04:36:11 PM PDT 24 20564271 ps
T966 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.764949622 Jun 26 04:36:17 PM PDT 24 Jun 26 04:36:22 PM PDT 24 24260772 ps
T967 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1245421088 Jun 26 04:36:17 PM PDT 24 Jun 26 04:36:20 PM PDT 24 18957761 ps
T968 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1255701789 Jun 26 04:36:28 PM PDT 24 Jun 26 04:36:30 PM PDT 24 71417431 ps
T95 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1320147000 Jun 26 04:36:18 PM PDT 24 Jun 26 04:36:46 PM PDT 24 15438062493 ps
T969 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3141152027 Jun 26 04:36:16 PM PDT 24 Jun 26 04:36:47 PM PDT 24 3753951281 ps
T970 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2124520391 Jun 26 04:36:33 PM PDT 24 Jun 26 04:36:38 PM PDT 24 357070090 ps
T971 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1686403263 Jun 26 04:36:14 PM PDT 24 Jun 26 04:36:18 PM PDT 24 29937711 ps
T147 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3513933913 Jun 26 04:36:49 PM PDT 24 Jun 26 04:36:54 PM PDT 24 345813231 ps
T102 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.121151671 Jun 26 04:36:12 PM PDT 24 Jun 26 04:37:08 PM PDT 24 14199051359 ps
T972 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.392301521 Jun 26 04:36:24 PM PDT 24 Jun 26 04:36:30 PM PDT 24 1389960000 ps
T973 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.240640363 Jun 26 04:36:14 PM PDT 24 Jun 26 04:36:20 PM PDT 24 280299771 ps
T974 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.4196017917 Jun 26 04:36:31 PM PDT 24 Jun 26 04:36:36 PM PDT 24 1471762136 ps
T143 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1934060610 Jun 26 04:36:26 PM PDT 24 Jun 26 04:36:29 PM PDT 24 161057218 ps
T975 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2863299037 Jun 26 04:36:17 PM PDT 24 Jun 26 04:36:20 PM PDT 24 30184307 ps
T976 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2469440247 Jun 26 04:36:20 PM PDT 24 Jun 26 04:36:23 PM PDT 24 28164374 ps
T977 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1165238785 Jun 26 04:36:13 PM PDT 24 Jun 26 04:36:17 PM PDT 24 20717282 ps
T978 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3640244245 Jun 26 04:36:05 PM PDT 24 Jun 26 04:36:09 PM PDT 24 21539290 ps
T979 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1840234583 Jun 26 04:36:19 PM PDT 24 Jun 26 04:36:25 PM PDT 24 68085381 ps
T980 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1551471444 Jun 26 04:36:21 PM PDT 24 Jun 26 04:36:24 PM PDT 24 44184714 ps
T981 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3875216812 Jun 26 04:36:21 PM PDT 24 Jun 26 04:36:24 PM PDT 24 80170111 ps
T982 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2727427420 Jun 26 04:36:31 PM PDT 24 Jun 26 04:36:33 PM PDT 24 23651340 ps
T983 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3829848927 Jun 26 04:36:50 PM PDT 24 Jun 26 04:36:54 PM PDT 24 16293435 ps
T984 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3669613531 Jun 26 04:36:02 PM PDT 24 Jun 26 04:36:07 PM PDT 24 50942140 ps
T985 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1468926473 Jun 26 04:36:17 PM PDT 24 Jun 26 04:36:21 PM PDT 24 57252411 ps
T105 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2630821065 Jun 26 04:36:06 PM PDT 24 Jun 26 04:36:39 PM PDT 24 14812312511 ps
T146 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.499258902 Jun 26 04:36:20 PM PDT 24 Jun 26 04:36:25 PM PDT 24 675896264 ps
T986 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3771324580 Jun 26 04:36:43 PM PDT 24 Jun 26 04:36:45 PM PDT 24 29918580 ps
T103 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2085414529 Jun 26 04:36:45 PM PDT 24 Jun 26 04:37:17 PM PDT 24 14239757924 ps
T104 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.913919564 Jun 26 04:36:33 PM PDT 24 Jun 26 04:37:44 PM PDT 24 58835403999 ps
T987 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.579092979 Jun 26 04:36:18 PM PDT 24 Jun 26 04:36:22 PM PDT 24 18092153 ps
T988 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.567034648 Jun 26 04:36:17 PM PDT 24 Jun 26 04:36:23 PM PDT 24 1436653079 ps
T989 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3769130389 Jun 26 04:36:07 PM PDT 24 Jun 26 04:36:20 PM PDT 24 146960841 ps
T990 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.17810048 Jun 26 04:35:59 PM PDT 24 Jun 26 04:36:04 PM PDT 24 28000931 ps
T991 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2141623680 Jun 26 04:36:28 PM PDT 24 Jun 26 04:36:33 PM PDT 24 378339974 ps
T992 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2005743049 Jun 26 04:36:00 PM PDT 24 Jun 26 04:36:09 PM PDT 24 18597484 ps
T993 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.223320629 Jun 26 04:35:56 PM PDT 24 Jun 26 04:36:51 PM PDT 24 25218294872 ps
T994 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2937057549 Jun 26 04:36:12 PM PDT 24 Jun 26 04:36:18 PM PDT 24 121328482 ps
T995 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2087587939 Jun 26 04:36:19 PM PDT 24 Jun 26 04:37:14 PM PDT 24 7152349422 ps
T996 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3664429579 Jun 26 04:36:21 PM PDT 24 Jun 26 04:36:24 PM PDT 24 80110896 ps
T997 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3347137532 Jun 26 04:36:17 PM PDT 24 Jun 26 04:36:25 PM PDT 24 22741341 ps
T998 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.4019993736 Jun 26 04:36:09 PM PDT 24 Jun 26 04:36:17 PM PDT 24 126250423 ps
T144 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1027209205 Jun 26 04:36:11 PM PDT 24 Jun 26 04:36:21 PM PDT 24 1028098494 ps
T149 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2730837083 Jun 26 04:36:36 PM PDT 24 Jun 26 04:36:39 PM PDT 24 251334589 ps
T999 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.4050589884 Jun 26 04:36:18 PM PDT 24 Jun 26 04:36:23 PM PDT 24 20666203 ps
T1000 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2290566715 Jun 26 04:36:15 PM PDT 24 Jun 26 04:36:26 PM PDT 24 89629937 ps
T1001 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1039873772 Jun 26 04:36:30 PM PDT 24 Jun 26 04:36:35 PM PDT 24 383827896 ps
T1002 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2866923959 Jun 26 04:36:18 PM PDT 24 Jun 26 04:36:24 PM PDT 24 102380092 ps
T1003 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2410366658 Jun 26 04:36:15 PM PDT 24 Jun 26 04:36:19 PM PDT 24 48224158 ps
T1004 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.935895848 Jun 26 04:36:36 PM PDT 24 Jun 26 04:36:38 PM PDT 24 13944106 ps
T1005 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.89260303 Jun 26 04:36:13 PM PDT 24 Jun 26 04:36:17 PM PDT 24 17611475 ps
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