Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 15849971 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 158197591 1 T1 6463 T2 165991 T3 4909



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 85724096 1 T1 3564 T2 91157 T3 2918
values[0x0] 42582946 1 T1 1688 T2 43869 T3 1444
values[0x1] 45740520 1 T1 1867 T2 47709 T3 1608



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 8059752 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 165987810 1 T1 6770 T2 174460 T3 5452



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 638930 1 T1 29 T2 685 T3 22
valid_sources[0x01] 590567 1 T1 29 T2 689 T3 22
valid_sources[0x02] 659907 1 T1 37 T2 730 T3 14
valid_sources[0x03] 605640 1 T1 34 T2 743 T3 24
valid_sources[0x04] 1551897 1 T1 26 T2 633 T3 17
valid_sources[0x05] 617957 1 T1 24 T2 714 T3 18
valid_sources[0x06] 2149822 1 T1 29 T2 711 T3 22
valid_sources[0x07] 585932 1 T1 23 T2 709 T3 24
valid_sources[0x08] 585221 1 T1 27 T2 791 T3 25
valid_sources[0x09] 603316 1 T1 16 T2 686 T3 19
valid_sources[0x0a] 593823 1 T1 30 T2 776 T3 35
valid_sources[0x0b] 628223 1 T1 19 T2 725 T3 22
valid_sources[0x0c] 611805 1 T1 20 T2 711 T3 30
valid_sources[0x0d] 610643 1 T1 21 T2 767 T3 14
valid_sources[0x0e] 664095 1 T1 25 T2 657 T3 18
valid_sources[0x0f] 613882 1 T1 19 T2 764 T3 16
valid_sources[0x10] 575699 1 T1 26 T2 690 T3 35
valid_sources[0x11] 566403 1 T1 22 T2 708 T3 20
valid_sources[0x12] 600615 1 T1 34 T2 669 T3 21
valid_sources[0x13] 618652 1 T1 28 T2 755 T3 25
valid_sources[0x14] 600848 1 T1 15 T2 766 T3 56
valid_sources[0x15] 567833 1 T1 39 T2 654 T3 28
valid_sources[0x16] 570374 1 T1 29 T2 704 T3 23
valid_sources[0x17] 671304 1 T1 37 T2 697 T3 13
valid_sources[0x18] 656765 1 T1 28 T2 760 T3 27
valid_sources[0x19] 1498749 1 T1 23 T2 696 T3 25
valid_sources[0x1a] 593130 1 T1 20 T2 711 T3 26
valid_sources[0x1b] 576427 1 T1 23 T2 709 T3 16
valid_sources[0x1c] 563007 1 T1 25 T2 789 T3 31
valid_sources[0x1d] 612057 1 T1 28 T2 760 T3 11
valid_sources[0x1e] 590611 1 T1 29 T2 680 T3 8
valid_sources[0x1f] 583717 1 T1 36 T2 752 T3 20
valid_sources[0x20] 584931 1 T1 26 T2 782 T3 30
valid_sources[0x21] 586070 1 T1 25 T2 650 T3 24
valid_sources[0x22] 573316 1 T1 33 T2 727 T3 22
valid_sources[0x23] 592500 1 T1 26 T2 678 T3 20
valid_sources[0x24] 588294 1 T1 27 T2 736 T3 22
valid_sources[0x25] 600046 1 T1 20 T2 691 T3 18
valid_sources[0x26] 604615 1 T1 40 T2 693 T3 20
valid_sources[0x27] 633320 1 T1 37 T2 664 T3 33
valid_sources[0x28] 592813 1 T1 21 T2 727 T3 31
valid_sources[0x29] 585623 1 T1 37 T2 767 T3 22
valid_sources[0x2a] 570808 1 T1 24 T2 673 T3 19
valid_sources[0x2b] 567288 1 T1 22 T2 726 T3 19
valid_sources[0x2c] 635472 1 T1 31 T2 714 T3 33
valid_sources[0x2d] 573857 1 T1 29 T2 729 T3 18
valid_sources[0x2e] 592299 1 T1 12 T2 644 T3 27
valid_sources[0x2f] 607106 1 T1 18 T2 708 T3 26
valid_sources[0x30] 583448 1 T1 27 T2 706 T3 15
valid_sources[0x31] 635305 1 T1 35 T2 725 T3 19
valid_sources[0x32] 569249 1 T1 23 T2 714 T3 23
valid_sources[0x33] 633035 1 T1 23 T2 768 T3 28
valid_sources[0x34] 577077 1 T1 34 T2 749 T3 19
valid_sources[0x35] 601510 1 T1 27 T2 671 T3 11
valid_sources[0x36] 1421627 1 T1 29 T2 676 T3 25
valid_sources[0x37] 656968 1 T1 21 T2 696 T3 27
valid_sources[0x38] 603135 1 T1 19 T2 702 T3 15
valid_sources[0x39] 572713 1 T1 27 T2 743 T3 19
valid_sources[0x3a] 564797 1 T1 37 T2 712 T3 31
valid_sources[0x3b] 583619 1 T1 47 T2 785 T3 16
valid_sources[0x3c] 612269 1 T1 40 T2 673 T3 28
valid_sources[0x3d] 602985 1 T1 28 T2 754 T3 16
valid_sources[0x3e] 570121 1 T1 39 T2 689 T3 20
valid_sources[0x3f] 607811 1 T1 57 T2 721 T3 26
valid_sources[0x40] 626672 1 T1 26 T2 764 T3 12
valid_sources[0x41] 577606 1 T1 22 T2 747 T3 21
valid_sources[0x42] 642282 1 T1 12 T2 684 T3 18
valid_sources[0x43] 571744 1 T1 42 T2 725 T3 20
valid_sources[0x44] 966931 1 T1 24 T2 719 T3 18
valid_sources[0x45] 582013 1 T1 33 T2 716 T3 30
valid_sources[0x46] 583265 1 T1 20 T2 732 T3 15
valid_sources[0x47] 567627 1 T1 30 T2 727 T3 18
valid_sources[0x48] 580300 1 T1 48 T2 784 T3 12
valid_sources[0x49] 564546 1 T1 23 T2 683 T3 25
valid_sources[0x4a] 567676 1 T1 20 T2 786 T3 30
valid_sources[0x4b] 581323 1 T1 34 T2 687 T3 21
valid_sources[0x4c] 579370 1 T1 30 T2 780 T3 15
valid_sources[0x4d] 611157 1 T1 28 T2 776 T3 25
valid_sources[0x4e] 1190097 1 T1 42 T2 673 T3 17
valid_sources[0x4f] 567269 1 T1 32 T2 725 T3 29
valid_sources[0x50] 1099191 1 T1 28 T2 696 T3 30
valid_sources[0x51] 630091 1 T1 21 T2 680 T3 11
valid_sources[0x52] 574389 1 T1 23 T2 730 T3 26
valid_sources[0x53] 599740 1 T1 21 T2 738 T3 27
valid_sources[0x54] 593182 1 T1 35 T2 666 T3 10
valid_sources[0x55] 599622 1 T1 37 T2 712 T3 18
valid_sources[0x56] 591847 1 T1 30 T2 702 T3 33
valid_sources[0x57] 599394 1 T1 30 T2 735 T3 33
valid_sources[0x58] 627502 1 T1 25 T2 717 T3 33
valid_sources[0x59] 567490 1 T1 20 T2 712 T3 14
valid_sources[0x5a] 566917 1 T1 33 T2 792 T3 24
valid_sources[0x5b] 567026 1 T1 35 T2 674 T3 36
valid_sources[0x5c] 569744 1 T1 42 T2 720 T3 15
valid_sources[0x5d] 590082 1 T1 19 T2 730 T3 14
valid_sources[0x5e] 768356 1 T1 29 T2 735 T3 15
valid_sources[0x5f] 596211 1 T1 39 T2 682 T3 20
valid_sources[0x60] 1469429 1 T1 19 T2 671 T3 30
valid_sources[0x61] 572915 1 T1 20 T2 729 T3 29
valid_sources[0x62] 638221 1 T1 31 T2 780 T3 20
valid_sources[0x63] 612856 1 T1 37 T2 737 T3 29
valid_sources[0x64] 609093 1 T1 17 T2 798 T3 28
valid_sources[0x65] 568583 1 T1 13 T2 769 T3 13
valid_sources[0x66] 571405 1 T1 25 T2 764 T3 41
valid_sources[0x67] 601175 1 T1 35 T2 722 T3 25
valid_sources[0x68] 577633 1 T1 18 T2 761 T3 27
valid_sources[0x69] 618960 1 T1 21 T2 695 T3 10
valid_sources[0x6a] 589940 1 T1 27 T2 700 T3 17
valid_sources[0x6b] 614402 1 T1 22 T2 719 T3 20
valid_sources[0x6c] 566746 1 T1 29 T2 677 T3 28
valid_sources[0x6d] 628286 1 T1 24 T2 710 T3 21
valid_sources[0x6e] 583118 1 T1 35 T2 718 T3 24
valid_sources[0x6f] 575134 1 T1 23 T2 775 T3 23
valid_sources[0x70] 602415 1 T1 31 T2 777 T3 22
valid_sources[0x71] 565534 1 T1 13 T2 752 T3 24
valid_sources[0x72] 616508 1 T1 32 T2 731 T3 16
valid_sources[0x73] 616679 1 T1 26 T2 738 T3 23
valid_sources[0x74] 588924 1 T1 25 T2 711 T3 19
valid_sources[0x75] 588052 1 T1 29 T2 752 T3 14
valid_sources[0x76] 570832 1 T1 31 T2 703 T3 27
valid_sources[0x77] 563244 1 T1 29 T2 746 T3 16
valid_sources[0x78] 571918 1 T1 31 T2 746 T3 28
valid_sources[0x79] 635934 1 T1 32 T2 782 T3 30
valid_sources[0x7a] 615598 1 T1 15 T2 726 T3 18
valid_sources[0x7b] 2179953 1 T1 27 T2 702 T3 31
valid_sources[0x7c] 577970 1 T1 24 T2 666 T3 29
valid_sources[0x7d] 574526 1 T1 22 T2 719 T3 34
valid_sources[0x7e] 1674256 1 T1 30 T2 655 T3 21
valid_sources[0x7f] 664746 1 T1 29 T2 738 T3 29
valid_sources[0x80] 762604 1 T1 26 T2 746 T3 27



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 77753527 1 T1 3252 T2 82762 T3 2385
values[0x0] all_enables biggest_size 40220293 1 T1 1591 T2 41382 T3 1276
values[0x1] all_enables biggest_size 40223771 1 T1 1620 T2 41847 T3 1248


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 45183 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 150509 1 T1 1 T2 1 T4 52



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 53924 1 T4 41 T6 23 T7 43
values[0x0] 68407 1 T1 1 T2 2 T3 2
values[0x1] 73361 1 T1 1 T2 2 T4 77



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 34927 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 160765 1 T1 1 T2 1 T4 70



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 580 1 T4 2 T21 10 T22 18
valid_sources[0x01] 640 1 T7 2 T21 7 T20 3
valid_sources[0x02] 764 1 T4 2 T7 1 T21 5
valid_sources[0x03] 672 1 T21 14 T18 1 T20 2
valid_sources[0x04] 1005 1 T21 3 T18 2 T22 17
valid_sources[0x05] 824 1 T21 2 T20 1 T22 5
valid_sources[0x06] 629 1 T9 1 T21 4 T22 16
valid_sources[0x07] 1300 1 T4 2 T21 11 T18 2
valid_sources[0x08] 770 1 T21 11 T22 11 T23 4
valid_sources[0x09] 629 1 T4 1 T7 5 T21 3
valid_sources[0x0a] 872 1 T21 6 T20 1 T22 4
valid_sources[0x0b] 902 1 T7 1 T21 7 T18 1
valid_sources[0x0c] 810 1 T4 2 T5 3 T21 7
valid_sources[0x0d] 720 1 T4 1 T21 5 T22 38
valid_sources[0x0e] 956 1 T4 2 T7 6 T21 11
valid_sources[0x0f] 613 1 T21 14 T18 3 T22 7
valid_sources[0x10] 1268 1 T21 8 T20 2 T22 13
valid_sources[0x11] 691 1 T7 1 T21 9 T18 1
valid_sources[0x12] 639 1 T21 7 T22 22 T23 10
valid_sources[0x13] 661 1 T4 1 T7 2 T21 3
valid_sources[0x14] 664 1 T4 1 T5 1 T21 10
valid_sources[0x15] 643 1 T4 1 T7 2 T21 5
valid_sources[0x16] 663 1 T4 2 T7 1 T21 6
valid_sources[0x17] 912 1 T21 9 T18 1 T22 8
valid_sources[0x18] 524 1 T4 2 T21 9 T68 2
valid_sources[0x19] 649 1 T21 8 T22 7 T52 1
valid_sources[0x1a] 749 1 T4 1 T21 11 T18 3
valid_sources[0x1b] 568 1 T7 1 T21 4 T22 18
valid_sources[0x1c] 580 1 T4 1 T21 8 T78 1
valid_sources[0x1d] 935 1 T21 5 T22 33 T23 1
valid_sources[0x1e] 640 1 T21 6 T18 1 T22 23
valid_sources[0x1f] 490 1 T4 1 T21 7 T22 10
valid_sources[0x20] 860 1 T4 1 T21 6 T68 2
valid_sources[0x21] 660 1 T4 2 T21 4 T22 20
valid_sources[0x22] 597 1 T4 2 T21 6 T18 1
valid_sources[0x23] 589 1 T4 1 T21 7 T20 3
valid_sources[0x24] 694 1 T1 1 T4 1 T21 4
valid_sources[0x25] 818 1 T4 2 T21 4 T20 4
valid_sources[0x26] 842 1 T5 1 T7 1 T21 5
valid_sources[0x27] 1304 1 T4 1 T21 10 T18 1
valid_sources[0x28] 936 1 T4 1 T21 9 T18 1
valid_sources[0x29] 604 1 T2 1 T4 2 T21 6
valid_sources[0x2a] 1247 1 T21 3 T22 21 T23 2
valid_sources[0x2b] 587 1 T4 4 T21 4 T18 1
valid_sources[0x2c] 622 1 T7 1 T21 5 T22 39
valid_sources[0x2d] 1007 1 T4 1 T7 2 T21 8
valid_sources[0x2e] 920 1 T21 7 T20 2 T22 54
valid_sources[0x2f] 593 1 T4 2 T21 14 T68 4
valid_sources[0x30] 676 1 T4 3 T21 11 T22 12
valid_sources[0x31] 648 1 T3 2 T21 11 T18 1
valid_sources[0x32] 608 1 T4 1 T7 1 T21 7
valid_sources[0x33] 891 1 T4 1 T21 3 T18 1
valid_sources[0x34] 759 1 T21 9 T18 2 T22 18
valid_sources[0x35] 568 1 T7 1 T21 5 T68 3
valid_sources[0x36] 632 1 T5 1 T21 8 T18 2
valid_sources[0x37] 837 1 T6 161 T7 3 T21 7
valid_sources[0x38] 604 1 T21 7 T18 2 T22 17
valid_sources[0x39] 720 1 T4 1 T21 8 T22 5
valid_sources[0x3a] 810 1 T4 1 T21 3 T18 1
valid_sources[0x3b] 668 1 T4 2 T21 9 T18 1
valid_sources[0x3c] 686 1 T4 1 T21 8 T22 9
valid_sources[0x3d] 773 1 T21 7 T18 6 T22 27
valid_sources[0x3e] 665 1 T7 2 T21 6 T22 23
valid_sources[0x3f] 639 1 T4 3 T21 6 T22 12
valid_sources[0x40] 772 1 T4 1 T5 1 T21 4
valid_sources[0x41] 685 1 T5 1 T21 11 T68 2
valid_sources[0x42] 585 1 T4 3 T21 3 T18 2
valid_sources[0x43] 557 1 T5 1 T21 10 T22 23
valid_sources[0x44] 969 1 T4 1 T21 7 T22 16
valid_sources[0x45] 625 1 T21 4 T20 7 T22 7
valid_sources[0x46] 1323 1 T4 1 T21 6 T79 1
valid_sources[0x47] 700 1 T21 5 T22 28 T12 2
valid_sources[0x48] 669 1 T4 1 T5 1 T21 7
valid_sources[0x49] 810 1 T21 9 T18 1 T22 47
valid_sources[0x4a] 779 1 T21 5 T22 4 T23 5
valid_sources[0x4b] 607 1 T4 1 T21 7 T20 4
valid_sources[0x4c] 1000 1 T21 6 T18 2 T22 30
valid_sources[0x4d] 698 1 T4 1 T21 8 T18 6
valid_sources[0x4e] 743 1 T7 3 T21 8 T18 1
valid_sources[0x4f] 547 1 T4 1 T7 1 T21 11
valid_sources[0x50] 620 1 T4 2 T21 12 T68 3
valid_sources[0x51] 1002 1 T4 2 T21 14 T18 2
valid_sources[0x52] 659 1 T21 5 T22 23 T23 1
valid_sources[0x53] 572 1 T7 3 T21 12 T20 2
valid_sources[0x54] 637 1 T4 2 T5 1 T21 9
valid_sources[0x55] 624 1 T21 12 T22 2 T23 1
valid_sources[0x56] 799 1 T7 1 T21 5 T68 4
valid_sources[0x57] 700 1 T21 5 T22 15 T73 5
valid_sources[0x58] 634 1 T4 1 T5 1 T7 1
valid_sources[0x59] 708 1 T4 2 T21 14 T20 2
valid_sources[0x5a] 1010 1 T7 1 T21 7 T18 1
valid_sources[0x5b] 1331 1 T4 1 T21 6 T22 61
valid_sources[0x5c] 639 1 T4 1 T7 2 T21 5
valid_sources[0x5d] 686 1 T7 1 T21 11 T22 1
valid_sources[0x5e] 826 1 T4 1 T7 1 T21 7
valid_sources[0x5f] 554 1 T4 1 T21 11 T22 17
valid_sources[0x60] 606 1 T21 12 T22 7 T23 5
valid_sources[0x61] 1026 1 T7 2 T21 7 T18 4
valid_sources[0x62] 714 1 T4 1 T7 3 T21 15
valid_sources[0x63] 830 1 T4 1 T7 1 T21 5
valid_sources[0x64] 673 1 T5 1 T7 3 T21 10
valid_sources[0x65] 992 1 T21 7 T22 6 T23 7
valid_sources[0x66] 528 1 T21 2 T20 2 T22 12
valid_sources[0x67] 657 1 T39 5 T21 5 T22 11
valid_sources[0x68] 656 1 T4 1 T7 1 T21 9
valid_sources[0x69] 715 1 T21 8 T22 13 T23 3
valid_sources[0x6a] 676 1 T21 11 T18 1 T22 11
valid_sources[0x6b] 578 1 T4 1 T21 2 T22 28
valid_sources[0x6c] 842 1 T4 1 T21 6 T68 6
valid_sources[0x6d] 844 1 T4 1 T7 2 T21 7
valid_sources[0x6e] 877 1 T4 2 T21 10 T18 1
valid_sources[0x6f] 791 1 T4 2 T21 9 T22 10
valid_sources[0x70] 712 1 T7 2 T21 9 T18 1
valid_sources[0x71] 827 1 T4 2 T21 8 T22 3
valid_sources[0x72] 899 1 T21 6 T18 1 T22 1
valid_sources[0x73] 626 1 T4 1 T21 5 T18 1
valid_sources[0x74] 601 1 T37 16 T7 1 T21 7
valid_sources[0x75] 521 1 T72 1 T21 5 T18 2
valid_sources[0x76] 763 1 T4 1 T7 3 T21 6
valid_sources[0x77] 1076 1 T4 1 T21 7 T18 1
valid_sources[0x78] 603 1 T7 3 T21 11 T18 1
valid_sources[0x79] 733 1 T4 1 T21 12 T22 19
valid_sources[0x7a] 509 1 T21 11 T22 5 T23 2
valid_sources[0x7b] 580 1 T4 2 T7 1 T21 4
valid_sources[0x7c] 628 1 T7 1 T21 6 T78 1
valid_sources[0x7d] 853 1 T21 9 T68 1 T18 1
valid_sources[0x7e] 662 1 T21 6 T18 3 T20 4
valid_sources[0x7f] 823 1 T4 1 T7 2 T21 8
valid_sources[0x80] 757 1 T7 1 T21 5 T22 17



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 40636 1 T4 18 T6 10 T7 26
values[0x0] all_enables biggest_size 56458 1 T4 20 T8 2 T5 2
values[0x1] all_enables biggest_size 53415 1 T1 1 T2 1 T4 14

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%