Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
partial 15754075 1 T1 656 T2 16744 T3 1061
full_word 155140558 1 T1 6463 T2 165991 T3 4909



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 170894333 1 T1 7119 T2 182735 T3 5970
auto[TlIntgErrCmd] 102 1 T65 8 T66 3 T67 8
auto[TlIntgErrData] 99 1 T65 5 T66 3 T67 10
auto[TlIntgErrBoth] 99 1 T65 7 T66 4 T67 2



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 82507007 1 T1 3564 T2 91157 T3 2918
auto[1] 88387626 1 T1 3555 T2 91578 T3 3052



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 7716499 1 T1 312 T2 8395 T3 533
auto[TlIntgErrNone] partial auto[1] 8037299 1 T1 344 T2 8349 T3 528
auto[TlIntgErrNone] full_word auto[0] 74790374 1 T1 3252 T2 82762 T3 2385
auto[TlIntgErrNone] full_word auto[1] 80350161 1 T1 3211 T2 83229 T3 2524
auto[TlIntgErrCmd] partial auto[0] 44 1 T65 4 T66 2 T67 2
auto[TlIntgErrCmd] partial auto[1] 50 1 T65 2 T67 6 T144 1
auto[TlIntgErrCmd] full_word auto[0] 3 1 T142 1 T146 1 T151 1
auto[TlIntgErrCmd] full_word auto[1] 5 1 T65 2 T66 1 T148 1
auto[TlIntgErrData] partial auto[0] 40 1 T65 4 T67 2 T144 1
auto[TlIntgErrData] partial auto[1] 53 1 T65 1 T66 3 T67 7
auto[TlIntgErrData] full_word auto[0] 5 1 T67 1 T145 1 T143 1
auto[TlIntgErrData] full_word auto[1] 1 1 T150 1 - - - -
auto[TlIntgErrBoth] partial auto[0] 37 1 T65 2 T66 2 T67 1
auto[TlIntgErrBoth] partial auto[1] 53 1 T65 3 T66 2 T67 1
auto[TlIntgErrBoth] full_word auto[0] 5 1 T144 1 T152 1 T153 1
auto[TlIntgErrBoth] full_word auto[1] 4 1 T65 2 T145 1 T146 1

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