Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	761510	1			T4	423		T5	2657		T11	2
auto[1]	11438223	1			T1	1		T2	76773		T3	2918
auto[2]	589842	1			T1	2		T4	266		T5	1723
auto[3]	11177696	1			T1	1		T2	77017		T3	3051

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	15503436	1			T1	2		T2	127055		T3	4076
auto[1]	2215687	1			T2	12666		T3	832		T4	858
auto[2]	2260359	1			T1	2		T2	12764		T3	873
auto[3]	3987789	1			T2	1305		T3	188		T4	170

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10084868

1

T1

4

T3

5969

T4

8193

auto[1]

13882403

1

T2

153790

T39

127069

T18

2

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	349973	1			T4	343		T5	2153		T11	1
auto[0]	auto[0]	auto[1]	36445	1			T4	30		T5	228		T6	25
auto[0]	auto[0]	auto[2]	36071	1			T4	44		T5	260		T11	1
auto[0]	auto[0]	auto[3]	80624	1			T4	6		T5	16		T7	50
auto[0]	auto[1]	auto[0]	3595017	1			T1	1		T3	1986		T4	3082
auto[0]	auto[1]	auto[1]	374416	1			T3	399		T4	585		T5	164
auto[0]	auto[1]	auto[2]	387920	1			T3	440		T4	293		T5	34
auto[0]	auto[1]	auto[3]	347201	1			T3	93		T4	71		T5	20
auto[0]	auto[2]	auto[0]	267086	1			T1	1		T5	1475		T6	1
auto[0]	auto[2]	auto[1]	32000	1			T5	140		T7	293		T20	1
auto[0]	auto[2]	auto[2]	28951	1			T1	1		T4	243		T5	98
auto[0]	auto[2]	auto[3]	57731	1			T4	23		T5	10		T6	10
auto[0]	auto[3]	auto[0]	3430808	1			T3	2090		T4	2410		T5	97
auto[0]	auto[3]	auto[1]	367915	1			T3	433		T4	243		T5	7
auto[0]	auto[3]	auto[2]	381846	1			T1	1		T3	433		T4	750
auto[0]	auto[3]	auto[3]	310864	1			T3	95		T4	70		T5	11
auto[1]	auto[0]	auto[0]	8429	1			T94	507		T118	317		T157	198
auto[1]	auto[0]	auto[1]	38662	1			T94	2430		T118	1510		T157	873
auto[1]	auto[0]	auto[2]	38700	1			T94	2490		T118	1450		T157	887
auto[1]	auto[0]	auto[3]	172606	1			T94	11068		T100	2		T118	6619
auto[1]	auto[1]	auto[0]	3923339	1			T2	63369		T39	52579		T18	1
auto[1]	auto[1]	auto[1]	680800	1			T2	6387		T39	5163		T41	1
auto[1]	auto[1]	auto[2]	677594	1			T2	6372		T39	5240		T18	1
auto[1]	auto[1]	auto[3]	1451936	1			T2	645		T39	560		T94	11159
auto[1]	auto[2]	auto[0]	5114	1			T94	521		T118	297		T158	204
auto[1]	auto[2]	auto[1]	23192	1			T94	2195		T118	1373		T159	1
auto[1]	auto[2]	auto[2]	31897	1			T94	1585		T118	1244		T157	814
auto[1]	auto[2]	auto[3]	143871	1			T94	7370		T118	5705		T157	3713
auto[1]	auto[3]	auto[0]	3923670	1			T2	63686		T39	52470		T20	2
auto[1]	auto[3]	auto[1]	662257	1			T2	6279		T39	5258		T94	247
auto[1]	auto[3]	auto[2]	677380	1			T2	6392		T39	5302		T56	2
auto[1]	auto[3]	auto[3]	1422956	1			T2	660		T39	497		T94	7448