Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1106246997	226170	0	0
ctrl_regwen_rd_A	1106246997	4138	0	0
exec_rd_A	1106246997	3865	0	0
exec_regwen_rd_A	1106246997	4430	0	0
readback_rd_A	1106246997	3188	0	0
readback_regwen_rd_A	1106246997	2857	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1106246997	226170	0	0
T18	308475	0	0	0
T20	428256	0	0	0
T21	32212	2611	0	0
T22	191251	5962	0	0
T23	0	1558	0	0
T24	33853	0	0	0
T38	179884	0	0	0
T44	0	13785	0	0
T56	947871	0	0	0
T64	0	2792	0	0
T68	711753	0	0	0
T73	0	757	0	0
T74	0	3992	0	0
T75	0	9063	0	0
T76	0	653	0	0
T77	0	1896	0	0
T78	70773	0	0	0
T79	70907	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1106246997	4138	0	0
T14	2287	0	0	0
T44	0	779	0	0
T45	0	515	0	0
T73	14227	29	0	0
T76	0	93	0	0
T81	595341	0	0	0
T82	566902	0	0	0
T98	242692	0	0	0
T117	436286	0	0	0
T131	0	110	0	0
T132	0	217	0	0
T133	0	272	0	0
T134	0	239	0	0
T135	0	172	0	0
T136	0	249	0	0
T137	197645	0	0	0
T138	68045	0	0	0
T139	67531	0	0	0
T140	85363	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1106246997	3865	0	0
T14	2287	0	0	0
T44	0	842	0	0
T45	0	396	0	0
T73	14227	58	0	0
T76	0	47	0	0
T81	595341	0	0	0
T82	566902	0	0	0
T98	242692	0	0	0
T117	436286	0	0	0
T131	0	108	0	0
T132	0	108	0	0
T133	0	310	0	0
T134	0	150	0	0
T135	0	133	0	0
T136	0	243	0	0
T137	197645	0	0	0
T138	68045	0	0	0
T139	67531	0	0	0
T140	85363	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1106246997	4430	0	0
T14	2287	0	0	0
T44	0	960	0	0
T45	0	515	0	0
T73	14227	18	0	0
T76	0	59	0	0
T81	595341	0	0	0
T82	566902	0	0	0
T98	242692	0	0	0
T117	436286	0	0	0
T131	0	84	0	0
T132	0	210	0	0
T133	0	352	0	0
T134	0	205	0	0
T135	0	171	0	0
T136	0	318	0	0
T137	197645	0	0	0
T138	68045	0	0	0
T139	67531	0	0	0
T140	85363	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1106246997	3188	0	0
T14	2287	0	0	0
T44	0	879	0	0
T45	0	479	0	0
T73	14227	56	0	0
T76	0	55	0	0
T81	595341	0	0	0
T82	566902	0	0	0
T98	242692	0	0	0
T117	436286	0	0	0
T131	0	95	0	0
T132	0	199	0	0
T133	0	290	0	0
T134	0	180	0	0
T135	0	196	0	0
T136	0	292	0	0
T137	197645	0	0	0
T138	68045	0	0	0
T139	67531	0	0	0
T140	85363	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1106246997	2857	0	0
T14	2287	0	0	0
T44	0	766	0	0
T45	0	406	0	0
T73	14227	26	0	0
T76	0	30	0	0
T81	595341	0	0	0
T82	566902	0	0	0
T98	242692	0	0	0
T117	436286	0	0	0
T131	0	85	0	0
T132	0	130	0	0
T133	0	299	0	0
T134	0	204	0	0
T135	0	155	0	0
T136	0	257	0	0
T137	197645	0	0	0
T138	68045	0	0	0
T139	67531	0	0	0
T140	85363	0	0	0