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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44


Total test records in report: 1034
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T793 /workspace/coverage/default/46.sram_ctrl_smoke.2000602877 Jun 27 06:55:56 PM PDT 24 Jun 27 06:56:05 PM PDT 24 488160793 ps
T794 /workspace/coverage/default/32.sram_ctrl_ram_cfg.2920902328 Jun 27 06:53:00 PM PDT 24 Jun 27 06:53:04 PM PDT 24 412556426 ps
T795 /workspace/coverage/default/43.sram_ctrl_bijection.1815965575 Jun 27 06:55:19 PM PDT 24 Jun 27 07:15:33 PM PDT 24 18105567579 ps
T796 /workspace/coverage/default/26.sram_ctrl_lc_escalation.643214780 Jun 27 06:51:37 PM PDT 24 Jun 27 06:52:33 PM PDT 24 8462006127 ps
T797 /workspace/coverage/default/7.sram_ctrl_stress_pipeline.1545441771 Jun 27 06:49:27 PM PDT 24 Jun 27 06:52:27 PM PDT 24 6743828441 ps
T798 /workspace/coverage/default/26.sram_ctrl_partial_access.2980801718 Jun 27 06:51:31 PM PDT 24 Jun 27 06:51:51 PM PDT 24 598519544 ps
T799 /workspace/coverage/default/28.sram_ctrl_ram_cfg.3744600006 Jun 27 06:52:04 PM PDT 24 Jun 27 06:52:09 PM PDT 24 711164232 ps
T800 /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.1024406367 Jun 27 06:50:38 PM PDT 24 Jun 27 06:50:51 PM PDT 24 1883569991 ps
T801 /workspace/coverage/default/13.sram_ctrl_alert_test.2787878270 Jun 27 06:50:00 PM PDT 24 Jun 27 06:50:04 PM PDT 24 11714467 ps
T802 /workspace/coverage/default/3.sram_ctrl_mem_partial_access.3070021916 Jun 27 06:49:13 PM PDT 24 Jun 27 06:50:44 PM PDT 24 18708658334 ps
T803 /workspace/coverage/default/33.sram_ctrl_max_throughput.2513675322 Jun 27 06:53:00 PM PDT 24 Jun 27 06:54:51 PM PDT 24 3083946380 ps
T804 /workspace/coverage/default/0.sram_ctrl_lc_escalation.1685708114 Jun 27 06:48:59 PM PDT 24 Jun 27 06:49:47 PM PDT 24 8162043405 ps
T805 /workspace/coverage/default/6.sram_ctrl_bijection.2179042930 Jun 27 06:49:26 PM PDT 24 Jun 27 07:16:20 PM PDT 24 374378886778 ps
T806 /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1831378100 Jun 27 06:49:47 PM PDT 24 Jun 27 06:55:44 PM PDT 24 33170517098 ps
T807 /workspace/coverage/default/40.sram_ctrl_executable.110999896 Jun 27 06:54:44 PM PDT 24 Jun 27 07:11:10 PM PDT 24 14752940890 ps
T808 /workspace/coverage/default/16.sram_ctrl_stress_all.1376679482 Jun 27 06:50:03 PM PDT 24 Jun 27 08:03:13 PM PDT 24 137188568003 ps
T809 /workspace/coverage/default/30.sram_ctrl_stress_all.3567573508 Jun 27 06:52:36 PM PDT 24 Jun 27 08:23:40 PM PDT 24 68469808984 ps
T810 /workspace/coverage/default/39.sram_ctrl_partial_access.710866600 Jun 27 06:54:26 PM PDT 24 Jun 27 06:54:46 PM PDT 24 4157625554 ps
T811 /workspace/coverage/default/29.sram_ctrl_max_throughput.2272676297 Jun 27 06:52:09 PM PDT 24 Jun 27 06:54:47 PM PDT 24 798970291 ps
T812 /workspace/coverage/default/41.sram_ctrl_stress_all.31272746 Jun 27 06:54:58 PM PDT 24 Jun 27 07:25:24 PM PDT 24 124145856914 ps
T813 /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3230818933 Jun 27 06:49:14 PM PDT 24 Jun 27 06:56:41 PM PDT 24 30072937689 ps
T814 /workspace/coverage/default/2.sram_ctrl_executable.4000025379 Jun 27 06:49:12 PM PDT 24 Jun 27 07:01:24 PM PDT 24 23799078585 ps
T815 /workspace/coverage/default/4.sram_ctrl_multiple_keys.1213239018 Jun 27 06:49:24 PM PDT 24 Jun 27 07:07:14 PM PDT 24 7259090428 ps
T816 /workspace/coverage/default/18.sram_ctrl_ram_cfg.2027153260 Jun 27 06:50:23 PM PDT 24 Jun 27 06:50:28 PM PDT 24 709008982 ps
T817 /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.271642894 Jun 27 06:53:00 PM PDT 24 Jun 27 06:53:13 PM PDT 24 724849436 ps
T818 /workspace/coverage/default/48.sram_ctrl_access_during_key_req.1287252071 Jun 27 06:56:24 PM PDT 24 Jun 27 07:08:09 PM PDT 24 13175878759 ps
T819 /workspace/coverage/default/28.sram_ctrl_executable.1357596704 Jun 27 06:51:55 PM PDT 24 Jun 27 07:00:43 PM PDT 24 21119770629 ps
T820 /workspace/coverage/default/38.sram_ctrl_bijection.2067714159 Jun 27 06:54:16 PM PDT 24 Jun 27 07:20:40 PM PDT 24 52613583349 ps
T821 /workspace/coverage/default/4.sram_ctrl_access_during_key_req.4099159626 Jun 27 06:49:24 PM PDT 24 Jun 27 07:14:21 PM PDT 24 18278809999 ps
T822 /workspace/coverage/default/27.sram_ctrl_stress_pipeline.3757618606 Jun 27 06:51:41 PM PDT 24 Jun 27 06:53:35 PM PDT 24 3601909224 ps
T823 /workspace/coverage/default/7.sram_ctrl_access_during_key_req.2893539918 Jun 27 06:49:26 PM PDT 24 Jun 27 07:03:38 PM PDT 24 60669262452 ps
T824 /workspace/coverage/default/41.sram_ctrl_bijection.3629666079 Jun 27 06:54:55 PM PDT 24 Jun 27 07:33:29 PM PDT 24 101282517592 ps
T825 /workspace/coverage/default/38.sram_ctrl_regwen.1174749634 Jun 27 06:54:14 PM PDT 24 Jun 27 07:14:47 PM PDT 24 12377487799 ps
T826 /workspace/coverage/default/49.sram_ctrl_max_throughput.3383466493 Jun 27 06:56:42 PM PDT 24 Jun 27 06:57:00 PM PDT 24 702925963 ps
T827 /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.308932439 Jun 27 06:49:15 PM PDT 24 Jun 27 06:51:20 PM PDT 24 2958676121 ps
T828 /workspace/coverage/default/24.sram_ctrl_partial_access.3519960597 Jun 27 06:51:05 PM PDT 24 Jun 27 06:51:26 PM PDT 24 799621397 ps
T829 /workspace/coverage/default/36.sram_ctrl_stress_pipeline.1146951046 Jun 27 06:53:41 PM PDT 24 Jun 27 06:59:25 PM PDT 24 7948156819 ps
T830 /workspace/coverage/default/10.sram_ctrl_ram_cfg.4090108851 Jun 27 06:49:41 PM PDT 24 Jun 27 06:49:48 PM PDT 24 699479851 ps
T831 /workspace/coverage/default/11.sram_ctrl_lc_escalation.1781062766 Jun 27 06:49:41 PM PDT 24 Jun 27 06:50:57 PM PDT 24 31668902411 ps
T832 /workspace/coverage/default/46.sram_ctrl_regwen.1493479389 Jun 27 06:55:56 PM PDT 24 Jun 27 07:16:50 PM PDT 24 16038477619 ps
T833 /workspace/coverage/default/10.sram_ctrl_mem_partial_access.1568212708 Jun 27 06:49:45 PM PDT 24 Jun 27 06:52:23 PM PDT 24 9058958794 ps
T834 /workspace/coverage/default/17.sram_ctrl_mem_walk.346660845 Jun 27 06:50:01 PM PDT 24 Jun 27 06:56:05 PM PDT 24 115168648643 ps
T835 /workspace/coverage/default/36.sram_ctrl_executable.660604072 Jun 27 06:53:51 PM PDT 24 Jun 27 07:08:16 PM PDT 24 54919111917 ps
T836 /workspace/coverage/default/49.sram_ctrl_mem_walk.3032424200 Jun 27 06:56:42 PM PDT 24 Jun 27 07:02:07 PM PDT 24 60252528713 ps
T837 /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.3627936016 Jun 27 06:49:26 PM PDT 24 Jun 27 06:56:17 PM PDT 24 207660531732 ps
T838 /workspace/coverage/default/47.sram_ctrl_stress_pipeline.2870962068 Jun 27 06:56:09 PM PDT 24 Jun 27 07:02:22 PM PDT 24 5284777498 ps
T26 /workspace/coverage/default/3.sram_ctrl_sec_cm.991776131 Jun 27 06:49:14 PM PDT 24 Jun 27 06:49:20 PM PDT 24 476274163 ps
T839 /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.69499056 Jun 27 06:49:39 PM PDT 24 Jun 27 06:50:59 PM PDT 24 5863931886 ps
T840 /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.365122434 Jun 27 06:52:47 PM PDT 24 Jun 27 06:57:55 PM PDT 24 102574473887 ps
T841 /workspace/coverage/default/28.sram_ctrl_access_during_key_req.1513785163 Jun 27 06:51:53 PM PDT 24 Jun 27 07:03:22 PM PDT 24 26640548335 ps
T842 /workspace/coverage/default/11.sram_ctrl_access_during_key_req.1965241585 Jun 27 06:49:42 PM PDT 24 Jun 27 07:09:37 PM PDT 24 48241041080 ps
T843 /workspace/coverage/default/19.sram_ctrl_regwen.3064390548 Jun 27 06:50:36 PM PDT 24 Jun 27 07:07:14 PM PDT 24 25273074291 ps
T844 /workspace/coverage/default/49.sram_ctrl_access_during_key_req.1258768684 Jun 27 06:56:40 PM PDT 24 Jun 27 07:02:27 PM PDT 24 26520463312 ps
T845 /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.4095858546 Jun 27 06:48:56 PM PDT 24 Jun 27 06:49:39 PM PDT 24 752634768 ps
T846 /workspace/coverage/default/49.sram_ctrl_stress_pipeline.2266278165 Jun 27 06:56:22 PM PDT 24 Jun 27 07:01:49 PM PDT 24 34373577318 ps
T847 /workspace/coverage/default/23.sram_ctrl_partial_access.2250514880 Jun 27 06:51:11 PM PDT 24 Jun 27 06:51:43 PM PDT 24 424881904 ps
T848 /workspace/coverage/default/16.sram_ctrl_mem_walk.3662367849 Jun 27 06:50:03 PM PDT 24 Jun 27 06:52:41 PM PDT 24 5479465585 ps
T849 /workspace/coverage/default/6.sram_ctrl_lc_escalation.378931773 Jun 27 06:49:28 PM PDT 24 Jun 27 06:50:36 PM PDT 24 17420909752 ps
T850 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.847483714 Jun 27 06:51:08 PM PDT 24 Jun 27 06:56:14 PM PDT 24 53603148418 ps
T851 /workspace/coverage/default/26.sram_ctrl_bijection.1670209448 Jun 27 06:51:29 PM PDT 24 Jun 27 07:28:18 PM PDT 24 508082755892 ps
T852 /workspace/coverage/default/37.sram_ctrl_regwen.3497570622 Jun 27 06:54:09 PM PDT 24 Jun 27 06:56:12 PM PDT 24 3983988844 ps
T853 /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2457782956 Jun 27 06:55:46 PM PDT 24 Jun 27 06:55:54 PM PDT 24 706956303 ps
T27 /workspace/coverage/default/1.sram_ctrl_sec_cm.2921099941 Jun 27 06:49:10 PM PDT 24 Jun 27 06:49:14 PM PDT 24 464366568 ps
T854 /workspace/coverage/default/18.sram_ctrl_mem_partial_access.2104432612 Jun 27 06:50:23 PM PDT 24 Jun 27 06:51:56 PM PDT 24 11635014731 ps
T855 /workspace/coverage/default/14.sram_ctrl_alert_test.3315171215 Jun 27 06:50:01 PM PDT 24 Jun 27 06:50:06 PM PDT 24 25558849 ps
T856 /workspace/coverage/default/16.sram_ctrl_executable.2774107663 Jun 27 06:50:01 PM PDT 24 Jun 27 06:59:02 PM PDT 24 22871178542 ps
T857 /workspace/coverage/default/37.sram_ctrl_alert_test.3934045275 Jun 27 06:54:08 PM PDT 24 Jun 27 06:54:10 PM PDT 24 15843270 ps
T858 /workspace/coverage/default/33.sram_ctrl_lc_escalation.4194974530 Jun 27 06:53:00 PM PDT 24 Jun 27 06:53:15 PM PDT 24 7449820678 ps
T859 /workspace/coverage/default/35.sram_ctrl_stress_pipeline.3712185878 Jun 27 06:53:29 PM PDT 24 Jun 27 06:58:21 PM PDT 24 5021773242 ps
T860 /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2489285238 Jun 27 06:49:39 PM PDT 24 Jun 27 06:50:16 PM PDT 24 8528796002 ps
T861 /workspace/coverage/default/13.sram_ctrl_stress_all.3763216373 Jun 27 06:49:49 PM PDT 24 Jun 27 07:42:53 PM PDT 24 34909703696 ps
T862 /workspace/coverage/default/30.sram_ctrl_executable.127231304 Jun 27 06:52:36 PM PDT 24 Jun 27 07:00:46 PM PDT 24 26929152250 ps
T863 /workspace/coverage/default/17.sram_ctrl_regwen.3839511562 Jun 27 06:50:01 PM PDT 24 Jun 27 07:08:46 PM PDT 24 106052665396 ps
T864 /workspace/coverage/default/19.sram_ctrl_mem_walk.603170902 Jun 27 06:50:41 PM PDT 24 Jun 27 06:53:46 PM PDT 24 10448676780 ps
T865 /workspace/coverage/default/46.sram_ctrl_partial_access.561572579 Jun 27 06:55:57 PM PDT 24 Jun 27 06:56:18 PM PDT 24 4912249147 ps
T866 /workspace/coverage/default/11.sram_ctrl_stress_all.3508065377 Jun 27 06:49:43 PM PDT 24 Jun 27 07:16:48 PM PDT 24 76865850474 ps
T867 /workspace/coverage/default/40.sram_ctrl_access_during_key_req.2570383888 Jun 27 06:54:44 PM PDT 24 Jun 27 07:03:19 PM PDT 24 11055910634 ps
T868 /workspace/coverage/default/22.sram_ctrl_smoke.1404450133 Jun 27 06:50:51 PM PDT 24 Jun 27 06:51:06 PM PDT 24 954559675 ps
T869 /workspace/coverage/default/31.sram_ctrl_smoke.3285740693 Jun 27 06:52:35 PM PDT 24 Jun 27 06:52:53 PM PDT 24 982238425 ps
T870 /workspace/coverage/default/29.sram_ctrl_ram_cfg.3088410553 Jun 27 06:52:17 PM PDT 24 Jun 27 06:52:21 PM PDT 24 684445385 ps
T871 /workspace/coverage/default/7.sram_ctrl_smoke.4293041356 Jun 27 06:49:26 PM PDT 24 Jun 27 06:49:39 PM PDT 24 3081425996 ps
T872 /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3641176371 Jun 27 06:51:06 PM PDT 24 Jun 27 06:52:12 PM PDT 24 7150468599 ps
T873 /workspace/coverage/default/26.sram_ctrl_multiple_keys.4137014750 Jun 27 06:51:30 PM PDT 24 Jun 27 06:53:25 PM PDT 24 3588978048 ps
T874 /workspace/coverage/default/33.sram_ctrl_multiple_keys.2953311092 Jun 27 06:53:01 PM PDT 24 Jun 27 07:12:29 PM PDT 24 16770873980 ps
T875 /workspace/coverage/default/41.sram_ctrl_max_throughput.3170550909 Jun 27 06:54:54 PM PDT 24 Jun 27 06:55:02 PM PDT 24 1295190345 ps
T876 /workspace/coverage/default/16.sram_ctrl_stress_pipeline.3960806097 Jun 27 06:49:49 PM PDT 24 Jun 27 06:54:53 PM PDT 24 4753855590 ps
T877 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2642511688 Jun 27 06:53:27 PM PDT 24 Jun 27 06:53:37 PM PDT 24 300580607 ps
T878 /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1288803424 Jun 27 06:48:56 PM PDT 24 Jun 27 06:50:00 PM PDT 24 1522628190 ps
T879 /workspace/coverage/default/17.sram_ctrl_mem_partial_access.1576106493 Jun 27 06:50:00 PM PDT 24 Jun 27 06:51:20 PM PDT 24 5559013207 ps
T880 /workspace/coverage/default/30.sram_ctrl_regwen.1997522018 Jun 27 06:52:36 PM PDT 24 Jun 27 07:10:54 PM PDT 24 6096828599 ps
T881 /workspace/coverage/default/26.sram_ctrl_executable.3767120001 Jun 27 06:51:28 PM PDT 24 Jun 27 07:03:01 PM PDT 24 48517322042 ps
T882 /workspace/coverage/default/25.sram_ctrl_alert_test.4250719515 Jun 27 06:51:37 PM PDT 24 Jun 27 06:51:41 PM PDT 24 37015560 ps
T883 /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2737923785 Jun 27 06:49:23 PM PDT 24 Jun 27 06:52:21 PM PDT 24 1605829252 ps
T884 /workspace/coverage/default/45.sram_ctrl_smoke.1488553618 Jun 27 06:55:47 PM PDT 24 Jun 27 06:56:09 PM PDT 24 2704208943 ps
T885 /workspace/coverage/default/21.sram_ctrl_bijection.3472382538 Jun 27 06:50:39 PM PDT 24 Jun 27 07:19:10 PM PDT 24 105203770203 ps
T886 /workspace/coverage/default/23.sram_ctrl_regwen.3914287374 Jun 27 06:51:07 PM PDT 24 Jun 27 07:10:29 PM PDT 24 14447310447 ps
T887 /workspace/coverage/default/14.sram_ctrl_mem_walk.4149992179 Jun 27 06:50:02 PM PDT 24 Jun 27 06:55:09 PM PDT 24 21871659376 ps
T888 /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.963935309 Jun 27 06:55:06 PM PDT 24 Jun 27 06:59:10 PM PDT 24 8891363584 ps
T889 /workspace/coverage/default/11.sram_ctrl_multiple_keys.1864355515 Jun 27 06:49:40 PM PDT 24 Jun 27 07:13:22 PM PDT 24 53847927126 ps
T890 /workspace/coverage/default/45.sram_ctrl_max_throughput.2700793296 Jun 27 06:55:57 PM PDT 24 Jun 27 06:56:20 PM PDT 24 1408158105 ps
T891 /workspace/coverage/default/21.sram_ctrl_stress_all.1476746852 Jun 27 06:50:53 PM PDT 24 Jun 27 07:47:48 PM PDT 24 29313772683 ps
T892 /workspace/coverage/default/9.sram_ctrl_executable.2428610635 Jun 27 06:49:40 PM PDT 24 Jun 27 07:07:36 PM PDT 24 14703514072 ps
T893 /workspace/coverage/default/32.sram_ctrl_smoke.1665973368 Jun 27 06:52:49 PM PDT 24 Jun 27 06:53:09 PM PDT 24 8686779402 ps
T894 /workspace/coverage/default/5.sram_ctrl_multiple_keys.774022331 Jun 27 06:49:24 PM PDT 24 Jun 27 07:14:27 PM PDT 24 18734550640 ps
T895 /workspace/coverage/default/12.sram_ctrl_mem_walk.1918972492 Jun 27 06:49:49 PM PDT 24 Jun 27 06:52:02 PM PDT 24 8221054786 ps
T896 /workspace/coverage/default/31.sram_ctrl_max_throughput.3381130545 Jun 27 06:52:55 PM PDT 24 Jun 27 06:53:20 PM PDT 24 2937834301 ps
T897 /workspace/coverage/default/33.sram_ctrl_access_during_key_req.1703498228 Jun 27 06:53:01 PM PDT 24 Jun 27 07:13:01 PM PDT 24 55070277117 ps
T898 /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2875307474 Jun 27 06:49:41 PM PDT 24 Jun 27 06:49:54 PM PDT 24 805679422 ps
T899 /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.6165526 Jun 27 06:49:47 PM PDT 24 Jun 27 06:50:28 PM PDT 24 1568743812 ps
T900 /workspace/coverage/default/16.sram_ctrl_ram_cfg.2543246384 Jun 27 06:50:01 PM PDT 24 Jun 27 06:50:08 PM PDT 24 1271979622 ps
T901 /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.874162825 Jun 27 06:49:59 PM PDT 24 Jun 27 06:50:59 PM PDT 24 8660287249 ps
T902 /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2057320547 Jun 27 06:49:27 PM PDT 24 Jun 27 06:52:34 PM PDT 24 7075506450 ps
T903 /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.3985963970 Jun 27 06:50:41 PM PDT 24 Jun 27 06:54:55 PM PDT 24 11139409798 ps
T904 /workspace/coverage/default/20.sram_ctrl_mem_walk.1714069240 Jun 27 06:50:37 PM PDT 24 Jun 27 06:56:08 PM PDT 24 21009296816 ps
T905 /workspace/coverage/default/19.sram_ctrl_lc_escalation.1705581866 Jun 27 06:50:37 PM PDT 24 Jun 27 06:51:49 PM PDT 24 23139901558 ps
T906 /workspace/coverage/default/28.sram_ctrl_alert_test.1539178372 Jun 27 06:52:05 PM PDT 24 Jun 27 06:52:07 PM PDT 24 21581638 ps
T907 /workspace/coverage/default/14.sram_ctrl_regwen.3555359583 Jun 27 06:49:51 PM PDT 24 Jun 27 06:55:34 PM PDT 24 27170088242 ps
T908 /workspace/coverage/default/25.sram_ctrl_executable.266417787 Jun 27 06:51:18 PM PDT 24 Jun 27 07:15:57 PM PDT 24 48148227035 ps
T909 /workspace/coverage/default/0.sram_ctrl_max_throughput.3565251899 Jun 27 06:48:59 PM PDT 24 Jun 27 06:49:36 PM PDT 24 2982643752 ps
T910 /workspace/coverage/default/1.sram_ctrl_ram_cfg.3549163489 Jun 27 06:49:10 PM PDT 24 Jun 27 06:49:15 PM PDT 24 708782298 ps
T911 /workspace/coverage/default/41.sram_ctrl_regwen.3287038182 Jun 27 06:54:57 PM PDT 24 Jun 27 07:05:59 PM PDT 24 9137257366 ps
T912 /workspace/coverage/default/30.sram_ctrl_multiple_keys.784450845 Jun 27 06:52:18 PM PDT 24 Jun 27 07:10:03 PM PDT 24 38392502887 ps
T913 /workspace/coverage/default/17.sram_ctrl_bijection.1397068392 Jun 27 06:50:02 PM PDT 24 Jun 27 07:14:29 PM PDT 24 119932876573 ps
T914 /workspace/coverage/default/12.sram_ctrl_access_during_key_req.1458895305 Jun 27 06:49:47 PM PDT 24 Jun 27 07:01:01 PM PDT 24 8629060693 ps
T915 /workspace/coverage/default/8.sram_ctrl_lc_escalation.3685152975 Jun 27 06:49:39 PM PDT 24 Jun 27 06:50:31 PM PDT 24 26995472662 ps
T916 /workspace/coverage/default/17.sram_ctrl_access_during_key_req.1205955985 Jun 27 06:50:02 PM PDT 24 Jun 27 06:55:28 PM PDT 24 8574851806 ps
T917 /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3295129285 Jun 27 06:55:56 PM PDT 24 Jun 27 06:56:33 PM PDT 24 7603277920 ps
T918 /workspace/coverage/default/3.sram_ctrl_multiple_keys.2923348614 Jun 27 06:49:12 PM PDT 24 Jun 27 07:05:49 PM PDT 24 105400357339 ps
T919 /workspace/coverage/default/34.sram_ctrl_mem_partial_access.3187869337 Jun 27 06:53:27 PM PDT 24 Jun 27 06:54:56 PM PDT 24 22150819797 ps
T920 /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.4172924986 Jun 27 06:54:44 PM PDT 24 Jun 27 06:55:39 PM PDT 24 2963972858 ps
T921 /workspace/coverage/default/30.sram_ctrl_max_throughput.3798564575 Jun 27 06:52:36 PM PDT 24 Jun 27 06:53:55 PM PDT 24 2974665094 ps
T922 /workspace/coverage/default/30.sram_ctrl_mem_partial_access.3184266323 Jun 27 06:52:37 PM PDT 24 Jun 27 06:54:05 PM PDT 24 10892810358 ps
T923 /workspace/coverage/default/13.sram_ctrl_partial_access.2575384557 Jun 27 06:49:42 PM PDT 24 Jun 27 06:49:57 PM PDT 24 1319772217 ps
T924 /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.301559136 Jun 27 06:56:22 PM PDT 24 Jun 27 07:01:39 PM PDT 24 13300797633 ps
T925 /workspace/coverage/default/23.sram_ctrl_ram_cfg.2127041285 Jun 27 06:51:11 PM PDT 24 Jun 27 06:51:22 PM PDT 24 355314740 ps
T926 /workspace/coverage/default/1.sram_ctrl_alert_test.1526888013 Jun 27 06:48:59 PM PDT 24 Jun 27 06:49:04 PM PDT 24 142417163 ps
T927 /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.2399666609 Jun 27 06:53:02 PM PDT 24 Jun 27 06:58:13 PM PDT 24 27422057404 ps
T928 /workspace/coverage/default/7.sram_ctrl_lc_escalation.810181839 Jun 27 06:49:27 PM PDT 24 Jun 27 06:50:16 PM PDT 24 8891191132 ps
T929 /workspace/coverage/default/34.sram_ctrl_ram_cfg.2157143349 Jun 27 06:53:13 PM PDT 24 Jun 27 06:53:17 PM PDT 24 348187134 ps
T930 /workspace/coverage/default/14.sram_ctrl_stress_all.456539235 Jun 27 06:49:50 PM PDT 24 Jun 27 08:00:22 PM PDT 24 173184930380 ps
T931 /workspace/coverage/default/4.sram_ctrl_stress_pipeline.1092441998 Jun 27 06:49:27 PM PDT 24 Jun 27 06:54:22 PM PDT 24 4178368987 ps
T932 /workspace/coverage/default/34.sram_ctrl_lc_escalation.1693630501 Jun 27 06:53:13 PM PDT 24 Jun 27 06:54:13 PM PDT 24 46541538325 ps
T933 /workspace/coverage/default/12.sram_ctrl_lc_escalation.281092637 Jun 27 06:49:46 PM PDT 24 Jun 27 06:50:40 PM PDT 24 14042625408 ps
T934 /workspace/coverage/default/38.sram_ctrl_mem_partial_access.3312327122 Jun 27 06:54:27 PM PDT 24 Jun 27 06:55:43 PM PDT 24 1402281761 ps
T935 /workspace/coverage/default/20.sram_ctrl_smoke.4117587847 Jun 27 06:50:36 PM PDT 24 Jun 27 06:50:53 PM PDT 24 824298997 ps
T936 /workspace/coverage/default/43.sram_ctrl_access_during_key_req.420078725 Jun 27 06:55:19 PM PDT 24 Jun 27 07:05:30 PM PDT 24 14094452928 ps
T937 /workspace/coverage/default/14.sram_ctrl_ram_cfg.371094401 Jun 27 06:49:56 PM PDT 24 Jun 27 06:50:01 PM PDT 24 1355126951 ps
T938 /workspace/coverage/default/5.sram_ctrl_max_throughput.1960402253 Jun 27 06:49:28 PM PDT 24 Jun 27 06:49:38 PM PDT 24 2792235341 ps
T939 /workspace/coverage/default/28.sram_ctrl_max_throughput.2575012352 Jun 27 06:51:53 PM PDT 24 Jun 27 06:52:00 PM PDT 24 1511631268 ps
T69 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2201461104 Jun 27 06:12:35 PM PDT 24 Jun 27 06:13:08 PM PDT 24 7561916554 ps
T70 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4070874707 Jun 27 06:12:50 PM PDT 24 Jun 27 06:12:55 PM PDT 24 53929140 ps
T71 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3501641733 Jun 27 06:12:39 PM PDT 24 Jun 27 06:13:37 PM PDT 24 71359793340 ps
T114 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.960763093 Jun 27 06:12:48 PM PDT 24 Jun 27 06:12:51 PM PDT 24 59639674 ps
T84 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1666596974 Jun 27 06:12:38 PM PDT 24 Jun 27 06:12:43 PM PDT 24 39305002 ps
T115 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2173700526 Jun 27 06:12:34 PM PDT 24 Jun 27 06:12:39 PM PDT 24 173449835 ps
T85 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.4032311349 Jun 27 06:12:38 PM PDT 24 Jun 27 06:12:42 PM PDT 24 15213114 ps
T130 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3575387004 Jun 27 06:12:33 PM PDT 24 Jun 27 06:12:36 PM PDT 24 15631698 ps
T940 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3922707956 Jun 27 06:12:38 PM PDT 24 Jun 27 06:12:46 PM PDT 24 369657831 ps
T86 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1008379674 Jun 27 06:12:48 PM PDT 24 Jun 27 06:13:52 PM PDT 24 28194914866 ps
T87 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1424169661 Jun 27 06:12:33 PM PDT 24 Jun 27 06:13:06 PM PDT 24 23017123892 ps
T941 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3095241282 Jun 27 06:12:34 PM PDT 24 Jun 27 06:12:41 PM PDT 24 1490259663 ps
T65 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2399521158 Jun 27 06:12:40 PM PDT 24 Jun 27 06:12:45 PM PDT 24 354879859 ps
T66 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2858440464 Jun 27 06:12:34 PM PDT 24 Jun 27 06:12:40 PM PDT 24 213082344 ps
T116 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.678342132 Jun 27 06:12:47 PM PDT 24 Jun 27 06:12:50 PM PDT 24 100507901 ps
T88 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.693273532 Jun 27 06:12:35 PM PDT 24 Jun 27 06:13:08 PM PDT 24 3774142506 ps
T89 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.4259050363 Jun 27 06:12:38 PM PDT 24 Jun 27 06:13:32 PM PDT 24 29432346856 ps
T90 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.4274104018 Jun 27 06:12:38 PM PDT 24 Jun 27 06:12:43 PM PDT 24 14287767 ps
T67 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1504876844 Jun 27 06:12:50 PM PDT 24 Jun 27 06:12:57 PM PDT 24 271927496 ps
T942 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1532115811 Jun 27 06:12:32 PM PDT 24 Jun 27 06:12:36 PM PDT 24 21514189 ps
T943 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3188847358 Jun 27 06:12:32 PM PDT 24 Jun 27 06:12:35 PM PDT 24 149259897 ps
T944 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.660888832 Jun 27 06:12:33 PM PDT 24 Jun 27 06:12:41 PM PDT 24 1424899624 ps
T945 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1684647501 Jun 27 06:12:48 PM PDT 24 Jun 27 06:12:52 PM PDT 24 109977653 ps
T946 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1277774230 Jun 27 06:12:34 PM PDT 24 Jun 27 06:12:38 PM PDT 24 108908108 ps
T947 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.994116820 Jun 27 06:12:51 PM PDT 24 Jun 27 06:12:59 PM PDT 24 141344846 ps
T948 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.682160708 Jun 27 06:12:40 PM PDT 24 Jun 27 06:12:48 PM PDT 24 2676963113 ps
T949 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.884665745 Jun 27 06:12:34 PM PDT 24 Jun 27 06:12:39 PM PDT 24 41544155 ps
T950 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2143640648 Jun 27 06:12:33 PM PDT 24 Jun 27 06:12:36 PM PDT 24 51196394 ps
T95 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1556099426 Jun 27 06:12:46 PM PDT 24 Jun 27 06:13:38 PM PDT 24 7486764887 ps
T96 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.311224868 Jun 27 06:12:48 PM PDT 24 Jun 27 06:13:17 PM PDT 24 14798930360 ps
T144 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1603042278 Jun 27 06:12:36 PM PDT 24 Jun 27 06:12:43 PM PDT 24 178118686 ps
T97 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.170340358 Jun 27 06:12:38 PM PDT 24 Jun 27 06:13:30 PM PDT 24 7432697860 ps
T145 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3045666037 Jun 27 06:12:32 PM PDT 24 Jun 27 06:12:36 PM PDT 24 661787572 ps
T951 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.387881249 Jun 27 06:12:33 PM PDT 24 Jun 27 06:12:38 PM PDT 24 24014072 ps
T952 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2475719037 Jun 27 06:12:50 PM PDT 24 Jun 27 06:12:54 PM PDT 24 18229635 ps
T953 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3552661603 Jun 27 06:12:33 PM PDT 24 Jun 27 06:12:38 PM PDT 24 17865913 ps
T954 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2872517697 Jun 27 06:12:32 PM PDT 24 Jun 27 06:12:35 PM PDT 24 88811357 ps
T955 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1529675367 Jun 27 06:12:35 PM PDT 24 Jun 27 06:12:43 PM PDT 24 355787992 ps
T142 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2113774635 Jun 27 06:12:34 PM PDT 24 Jun 27 06:12:39 PM PDT 24 132109878 ps
T143 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2161337497 Jun 27 06:12:46 PM PDT 24 Jun 27 06:12:51 PM PDT 24 723871767 ps
T956 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2451692014 Jun 27 06:12:49 PM PDT 24 Jun 27 06:12:53 PM PDT 24 45819107 ps
T957 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3622741695 Jun 27 06:12:33 PM PDT 24 Jun 27 06:12:38 PM PDT 24 28818864 ps
T958 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4022250148 Jun 27 06:12:34 PM PDT 24 Jun 27 06:12:41 PM PDT 24 361788498 ps
T959 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.744660172 Jun 27 06:12:34 PM PDT 24 Jun 27 06:12:43 PM PDT 24 1592591759 ps
T106 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2910375637 Jun 27 06:12:50 PM PDT 24 Jun 27 06:13:48 PM PDT 24 14671794691 ps
T107 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2584333679 Jun 27 06:12:46 PM PDT 24 Jun 27 06:13:38 PM PDT 24 8095673187 ps
T960 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.976725302 Jun 27 06:12:48 PM PDT 24 Jun 27 06:12:54 PM PDT 24 36123611 ps
T108 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.4169436194 Jun 27 06:12:48 PM PDT 24 Jun 27 06:12:52 PM PDT 24 19934740 ps
T109 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1131440017 Jun 27 06:12:35 PM PDT 24 Jun 27 06:12:40 PM PDT 24 44120234 ps
T961 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2441991236 Jun 27 06:12:40 PM PDT 24 Jun 27 06:12:44 PM PDT 24 42380652 ps
T111 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1353576801 Jun 27 06:12:38 PM PDT 24 Jun 27 06:12:43 PM PDT 24 30283228 ps
T962 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3968158742 Jun 27 06:12:49 PM PDT 24 Jun 27 06:12:54 PM PDT 24 19683115 ps
T152 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.327359896 Jun 27 06:12:34 PM PDT 24 Jun 27 06:12:39 PM PDT 24 250567803 ps
T963 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.635547996 Jun 27 06:12:32 PM PDT 24 Jun 27 06:12:35 PM PDT 24 77920973 ps
T964 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3202179684 Jun 27 06:12:49 PM PDT 24 Jun 27 06:12:54 PM PDT 24 49368518 ps
T965 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3053187088 Jun 27 06:12:33 PM PDT 24 Jun 27 06:12:40 PM PDT 24 391374216 ps
T146 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3545583573 Jun 27 06:12:34 PM PDT 24 Jun 27 06:12:39 PM PDT 24 267048238 ps
T966 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2443401964 Jun 27 06:12:35 PM PDT 24 Jun 27 06:12:40 PM PDT 24 26351844 ps
T967 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1791690744 Jun 27 06:12:33 PM PDT 24 Jun 27 06:12:37 PM PDT 24 40625063 ps
T150 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3516351266 Jun 27 06:12:33 PM PDT 24 Jun 27 06:12:40 PM PDT 24 525662244 ps
T968 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1678740855 Jun 27 06:12:49 PM PDT 24 Jun 27 06:12:56 PM PDT 24 433279615 ps
T969 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4030611780 Jun 27 06:12:34 PM PDT 24 Jun 27 06:12:40 PM PDT 24 23875925 ps
T970 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1172294096 Jun 27 06:12:48 PM PDT 24 Jun 27 06:12:55 PM PDT 24 695023222 ps
T971 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1851709792 Jun 27 06:12:34 PM PDT 24 Jun 27 06:12:38 PM PDT 24 23482473 ps
T110 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.4018619198 Jun 27 06:12:32 PM PDT 24 Jun 27 06:13:30 PM PDT 24 41611337312 ps
T972 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2777679206 Jun 27 06:12:38 PM PDT 24 Jun 27 06:12:46 PM PDT 24 371366535 ps
T973 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4089345032 Jun 27 06:12:52 PM PDT 24 Jun 27 06:12:59 PM PDT 24 126715970 ps
T974 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2963534333 Jun 27 06:12:34 PM PDT 24 Jun 27 06:12:41 PM PDT 24 37267969 ps
T975 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3699969382 Jun 27 06:12:34 PM PDT 24 Jun 27 06:12:39 PM PDT 24 20681811 ps
T976 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.58726340 Jun 27 06:12:50 PM PDT 24 Jun 27 06:12:55 PM PDT 24 21340256 ps
T147 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3088015783 Jun 27 06:12:47 PM PDT 24 Jun 27 06:12:51 PM PDT 24 353590504 ps
T977 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1411498318 Jun 27 06:12:33 PM PDT 24 Jun 27 06:12:38 PM PDT 24 137317022 ps
T978 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2531920500 Jun 27 06:12:32 PM PDT 24 Jun 27 06:13:34 PM PDT 24 117373090501 ps
T979 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2388519961 Jun 27 06:12:34 PM PDT 24 Jun 27 06:12:39 PM PDT 24 33063245 ps
T980 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1736813500 Jun 27 06:12:50 PM PDT 24 Jun 27 06:12:55 PM PDT 24 102121262 ps
T981 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2044837988 Jun 27 06:12:33 PM PDT 24 Jun 27 06:12:37 PM PDT 24 36257720 ps
T982 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.4152453520 Jun 27 06:12:50 PM PDT 24 Jun 27 06:12:55 PM PDT 24 141281478 ps
T153 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3961797723 Jun 27 06:12:55 PM PDT 24 Jun 27 06:12:58 PM PDT 24 325044287 ps
T983 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3220780889 Jun 27 06:12:50 PM PDT 24 Jun 27 06:12:58 PM PDT 24 711323923 ps
T984 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3831398288 Jun 27 06:12:34 PM PDT 24 Jun 27 06:12:38 PM PDT 24 53482795 ps
T985 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3792836551 Jun 27 06:12:55 PM PDT 24 Jun 27 06:13:01 PM PDT 24 1471814989 ps
T986 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3596641572 Jun 27 06:12:34 PM PDT 24 Jun 27 06:12:42 PM PDT 24 490748303 ps
T987 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2063056514 Jun 27 06:12:49 PM PDT 24 Jun 27 06:12:55 PM PDT 24 124263174 ps
T112 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1334621850 Jun 27 06:12:35 PM PDT 24 Jun 27 06:13:06 PM PDT 24 7373462782 ps
T988 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.4138256783 Jun 27 06:12:48 PM PDT 24 Jun 27 06:12:53 PM PDT 24 363769789 ps
T989 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2994129449 Jun 27 06:12:34 PM PDT 24 Jun 27 06:12:40 PM PDT 24 22957074 ps
T148 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2981139289 Jun 27 06:12:38 PM PDT 24 Jun 27 06:12:45 PM PDT 24 187824826 ps
T990 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3563539726 Jun 27 06:12:49 PM PDT 24 Jun 27 06:12:54 PM PDT 24 218410046 ps
T991 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2320878607 Jun 27 06:12:32 PM PDT 24 Jun 27 06:12:36 PM PDT 24 32998759 ps
T149 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2476273131 Jun 27 06:12:35 PM PDT 24 Jun 27 06:12:41 PM PDT 24 140627189 ps
T992 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.431258287 Jun 27 06:12:48 PM PDT 24 Jun 27 06:13:16 PM PDT 24 23354857486 ps
T993 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1780057889 Jun 27 06:12:48 PM PDT 24 Jun 27 06:12:51 PM PDT 24 25807745 ps
T994 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2938329748 Jun 27 06:12:55 PM PDT 24 Jun 27 06:12:58 PM PDT 24 40052183 ps
T995 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1983207502 Jun 27 06:12:48 PM PDT 24 Jun 27 06:13:21 PM PDT 24 3882223325 ps
T996 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4126810846 Jun 27 06:12:55 PM PDT 24 Jun 27 06:13:01 PM PDT 24 368364622 ps
T997 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.20003573 Jun 27 06:12:50 PM PDT 24 Jun 27 06:12:54 PM PDT 24 16127231 ps
T998 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2455478511 Jun 27 06:12:39 PM PDT 24 Jun 27 06:12:43 PM PDT 24 28708221 ps
T999 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3264238082 Jun 27 06:12:38 PM PDT 24 Jun 27 06:12:44 PM PDT 24 43999832 ps
T1000 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2020681459 Jun 27 06:12:32 PM PDT 24 Jun 27 06:12:34 PM PDT 24 32301146 ps
T1001 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3140319592 Jun 27 06:12:48 PM PDT 24 Jun 27 06:13:17 PM PDT 24 3820684740 ps
T151 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.219767792 Jun 27 06:12:34 PM PDT 24 Jun 27 06:12:41 PM PDT 24 182024081 ps
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