SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
97.97 | 99.19 | 94.27 | 99.72 | 100.00 | 96.03 | 99.12 | 97.44 |
T1002 | /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.200461981 | Jun 27 06:12:52 PM PDT 24 | Jun 27 06:12:56 PM PDT 24 | 40478439 ps | ||
T1003 | /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3254252179 | Jun 27 06:12:38 PM PDT 24 | Jun 27 06:13:33 PM PDT 24 | 14087442507 ps | ||
T1004 | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3449581570 | Jun 27 06:12:47 PM PDT 24 | Jun 27 06:12:53 PM PDT 24 | 2169788213 ps | ||
T1005 | /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3763110255 | Jun 27 06:12:47 PM PDT 24 | Jun 27 06:12:49 PM PDT 24 | 25590194 ps | ||
T1006 | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2458695550 | Jun 27 06:13:08 PM PDT 24 | Jun 27 06:13:14 PM PDT 24 | 3180766149 ps | ||
T1007 | /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2653899117 | Jun 27 06:12:50 PM PDT 24 | Jun 27 06:13:22 PM PDT 24 | 24577309381 ps | ||
T1008 | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3156426191 | Jun 27 06:12:34 PM PDT 24 | Jun 27 06:12:39 PM PDT 24 | 29396524 ps | ||
T1009 | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.853740277 | Jun 27 06:12:39 PM PDT 24 | Jun 27 06:12:48 PM PDT 24 | 157643240 ps | ||
T1010 | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3174093069 | Jun 27 06:12:38 PM PDT 24 | Jun 27 06:12:44 PM PDT 24 | 48149375 ps | ||
T1011 | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.776880660 | Jun 27 06:12:46 PM PDT 24 | Jun 27 06:12:50 PM PDT 24 | 210972652 ps | ||
T1012 | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1082870960 | Jun 27 06:12:47 PM PDT 24 | Jun 27 06:12:53 PM PDT 24 | 336308561 ps | ||
T1013 | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.90516063 | Jun 27 06:12:50 PM PDT 24 | Jun 27 06:12:55 PM PDT 24 | 25851604 ps | ||
T1014 | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2106094726 | Jun 27 06:12:39 PM PDT 24 | Jun 27 06:12:48 PM PDT 24 | 300433093 ps | ||
T1015 | /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1139258589 | Jun 27 06:12:40 PM PDT 24 | Jun 27 06:12:44 PM PDT 24 | 29354307 ps | ||
T1016 | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1682522979 | Jun 27 06:12:35 PM PDT 24 | Jun 27 06:12:44 PM PDT 24 | 116073831 ps | ||
T1017 | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3134109111 | Jun 27 06:12:48 PM PDT 24 | Jun 27 06:12:51 PM PDT 24 | 247479006 ps | ||
T1018 | /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2517718092 | Jun 27 06:12:34 PM PDT 24 | Jun 27 06:13:04 PM PDT 24 | 4827321267 ps | ||
T1019 | /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1297062818 | Jun 27 06:12:35 PM PDT 24 | Jun 27 06:12:39 PM PDT 24 | 15738907 ps | ||
T1020 | /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2877211021 | Jun 27 06:12:51 PM PDT 24 | Jun 27 06:12:56 PM PDT 24 | 16246542 ps | ||
T1021 | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1419712336 | Jun 27 06:12:46 PM PDT 24 | Jun 27 06:12:51 PM PDT 24 | 1890289888 ps | ||
T1022 | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.183545786 | Jun 27 06:12:50 PM PDT 24 | Jun 27 06:12:54 PM PDT 24 | 15920573 ps | ||
T1023 | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2749064163 | Jun 27 06:12:47 PM PDT 24 | Jun 27 06:12:53 PM PDT 24 | 1570424230 ps | ||
T1024 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2223908454 | Jun 27 06:12:32 PM PDT 24 | Jun 27 06:12:35 PM PDT 24 | 24763846 ps | ||
T1025 | /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3797214107 | Jun 27 06:12:49 PM PDT 24 | Jun 27 06:12:54 PM PDT 24 | 38541322 ps | ||
T1026 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.4284035183 | Jun 27 06:12:35 PM PDT 24 | Jun 27 06:12:44 PM PDT 24 | 721392571 ps | ||
T1027 | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2321198246 | Jun 27 06:12:50 PM PDT 24 | Jun 27 06:12:56 PM PDT 24 | 382603666 ps | ||
T1028 | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.478847719 | Jun 27 06:12:40 PM PDT 24 | Jun 27 06:12:46 PM PDT 24 | 30068657 ps | ||
T1029 | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.4134782048 | Jun 27 06:12:38 PM PDT 24 | Jun 27 06:12:46 PM PDT 24 | 95408239 ps | ||
T105 | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2569461246 | Jun 27 06:12:48 PM PDT 24 | Jun 27 06:12:51 PM PDT 24 | 43056595 ps | ||
T1030 | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1829670607 | Jun 27 06:12:35 PM PDT 24 | Jun 27 06:12:43 PM PDT 24 | 139780492 ps | ||
T1031 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.4031361702 | Jun 27 06:12:37 PM PDT 24 | Jun 27 06:12:43 PM PDT 24 | 45121250 ps | ||
T1032 | /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.586476886 | Jun 27 06:12:39 PM PDT 24 | Jun 27 06:12:43 PM PDT 24 | 26109846 ps | ||
T1033 | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1787631016 | Jun 27 06:12:49 PM PDT 24 | Jun 27 06:12:57 PM PDT 24 | 1867290096 ps | ||
T1034 | /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3262898451 | Jun 27 06:12:47 PM PDT 24 | Jun 27 06:12:50 PM PDT 24 | 21423498 ps |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_all.529417442 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 431707204267 ps |
CPU time | 5810.67 seconds |
Started | Jun 27 06:49:40 PM PDT 24 |
Finished | Jun 27 08:26:36 PM PDT 24 |
Peak memory | 390076 kb |
Host | smart-b009bfc9-862c-4a9f-9572-286ebe6e14b2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529417442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 9.sram_ctrl_stress_all.529417442 |
Directory | /workspace/9.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1670580612 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 2078932991 ps |
CPU time | 102.32 seconds |
Started | Jun 27 06:48:59 PM PDT 24 |
Finished | Jun 27 06:50:46 PM PDT 24 |
Peak memory | 321544 kb |
Host | smart-5a551681-f422-4537-a459-61d810b6915a |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1670580612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.1670580612 |
Directory | /workspace/0.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2399521158 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 354879859 ps |
CPU time | 2.05 seconds |
Started | Jun 27 06:12:40 PM PDT 24 |
Finished | Jun 27 06:12:45 PM PDT 24 |
Peak memory | 211096 kb |
Host | smart-20fd691c-e2f4-47ab-9d64-5bf5a88afaa7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399521158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 6.sram_ctrl_tl_intg_err.2399521158 |
Directory | /workspace/6.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_mem_partial_access.2513964608 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 6579795950 ps |
CPU time | 78.67 seconds |
Started | Jun 27 06:51:11 PM PDT 24 |
Finished | Jun 27 06:52:38 PM PDT 24 |
Peak memory | 211080 kb |
Host | smart-618f88fe-8840-4d84-848d-354ef9135fe1 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513964608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_mem_partial_access.2513964608 |
Directory | /workspace/23.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3535182768 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 13348216762 ps |
CPU time | 283.75 seconds |
Started | Jun 27 06:48:59 PM PDT 24 |
Finished | Jun 27 06:53:48 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-98517e73-d41e-4025-837b-98467c3e5de3 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535182768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.sram_ctrl_partial_access_b2b.3535182768 |
Directory | /workspace/1.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_sec_cm.3808607762 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 129275720 ps |
CPU time | 1.94 seconds |
Started | Jun 27 06:49:10 PM PDT 24 |
Finished | Jun 27 06:49:13 PM PDT 24 |
Peak memory | 222428 kb |
Host | smart-2a5e783a-50dc-4b48-816d-f0ce002ba570 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808607762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.3808607762 |
Directory | /workspace/0.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_all.743601601 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 219689979346 ps |
CPU time | 6629.62 seconds |
Started | Jun 27 06:56:42 PM PDT 24 |
Finished | Jun 27 08:47:14 PM PDT 24 |
Peak memory | 379836 kb |
Host | smart-e4e2a5aa-9e60-40ab-9abb-43018f3d0164 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743601601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 49.sram_ctrl_stress_all.743601601 |
Directory | /workspace/49.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_alert_test.3580038719 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 38524573 ps |
CPU time | 0.71 seconds |
Started | Jun 27 06:49:44 PM PDT 24 |
Finished | Jun 27 06:49:50 PM PDT 24 |
Peak memory | 202344 kb |
Host | smart-b1fe6400-389d-4ded-8a68-d45e391ca461 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580038719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.3580038719 |
Directory | /workspace/10.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2201461104 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 7561916554 ps |
CPU time | 28.67 seconds |
Started | Jun 27 06:12:35 PM PDT 24 |
Finished | Jun 27 06:13:08 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-23c3fe89-5c4d-437b-9b33-8e71075a5bcd |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201461104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.2201461104 |
Directory | /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_ram_cfg.875629305 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 346482345 ps |
CPU time | 3.4 seconds |
Started | Jun 27 06:49:50 PM PDT 24 |
Finished | Jun 27 06:49:56 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-6e73a34d-e085-4a73-beb4-619dc1d05127 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875629305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.875629305 |
Directory | /workspace/13.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3516351266 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 525662244 ps |
CPU time | 2.43 seconds |
Started | Jun 27 06:12:33 PM PDT 24 |
Finished | Jun 27 06:12:40 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-e82aa036-586c-49d2-a8bf-a98e58a77992 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516351266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 2.sram_ctrl_tl_intg_err.3516351266 |
Directory | /workspace/2.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.4027600219 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 4733661545 ps |
CPU time | 183.88 seconds |
Started | Jun 27 06:49:49 PM PDT 24 |
Finished | Jun 27 06:52:56 PM PDT 24 |
Peak memory | 318584 kb |
Host | smart-9612e172-904b-4de2-9fbc-f767a2b197de |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4027600219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.4027600219 |
Directory | /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_all.2924999959 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 284701444180 ps |
CPU time | 5501.62 seconds |
Started | Jun 27 06:51:55 PM PDT 24 |
Finished | Jun 27 08:23:39 PM PDT 24 |
Peak memory | 382868 kb |
Host | smart-92149b11-1c90-4674-ae36-877397160bbf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924999959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 27.sram_ctrl_stress_all.2924999959 |
Directory | /workspace/27.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.219767792 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 182024081 ps |
CPU time | 2.4 seconds |
Started | Jun 27 06:12:34 PM PDT 24 |
Finished | Jun 27 06:12:41 PM PDT 24 |
Peak memory | 211052 kb |
Host | smart-1e5e9aff-0bde-456c-addc-84195c6ac250 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219767792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 10.sram_ctrl_tl_intg_err.219767792 |
Directory | /workspace/10.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_lc_escalation.3663582047 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 11355949287 ps |
CPU time | 36.72 seconds |
Started | Jun 27 06:49:55 PM PDT 24 |
Finished | Jun 27 06:50:35 PM PDT 24 |
Peak memory | 215612 kb |
Host | smart-5f71f6f6-e5f2-4410-ae8a-5aff6fcd72c0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663582047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es calation.3663582047 |
Directory | /workspace/15.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3088015783 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 353590504 ps |
CPU time | 2.33 seconds |
Started | Jun 27 06:12:47 PM PDT 24 |
Finished | Jun 27 06:12:51 PM PDT 24 |
Peak memory | 211152 kb |
Host | smart-b7428436-fa78-4380-9d22-55cc8545c79b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088015783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 12.sram_ctrl_tl_intg_err.3088015783 |
Directory | /workspace/12.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_all.3025017953 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 295179030492 ps |
CPU time | 2212.44 seconds |
Started | Jun 27 06:49:49 PM PDT 24 |
Finished | Jun 27 07:26:45 PM PDT 24 |
Peak memory | 377708 kb |
Host | smart-82a88914-0230-43ed-938a-f70c1895161c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025017953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 12.sram_ctrl_stress_all.3025017953 |
Directory | /workspace/12.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1556099426 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 7486764887 ps |
CPU time | 49.66 seconds |
Started | Jun 27 06:12:46 PM PDT 24 |
Finished | Jun 27 06:13:38 PM PDT 24 |
Peak memory | 203076 kb |
Host | smart-7c0cf0af-6cb1-4d73-917a-afb92c024948 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556099426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.1556099426 |
Directory | /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1791690744 |
Short name | T967 |
Test name | |
Test status | |
Simulation time | 40625063 ps |
CPU time | 0.7 seconds |
Started | Jun 27 06:12:33 PM PDT 24 |
Finished | Jun 27 06:12:37 PM PDT 24 |
Peak memory | 202620 kb |
Host | smart-b02b63d9-72bb-4396-b422-d930850de3ad |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791690744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_aliasing.1791690744 |
Directory | /workspace/0.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3622741695 |
Short name | T957 |
Test name | |
Test status | |
Simulation time | 28818864 ps |
CPU time | 1.28 seconds |
Started | Jun 27 06:12:33 PM PDT 24 |
Finished | Jun 27 06:12:38 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-b1679ed0-87d1-4a4d-a95b-1ffa39b3a37e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622741695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_bit_bash.3622741695 |
Directory | /workspace/0.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1532115811 |
Short name | T942 |
Test name | |
Test status | |
Simulation time | 21514189 ps |
CPU time | 0.7 seconds |
Started | Jun 27 06:12:32 PM PDT 24 |
Finished | Jun 27 06:12:36 PM PDT 24 |
Peak memory | 202640 kb |
Host | smart-2d91ec28-f832-49fa-afae-ed72d29759c2 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532115811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_hw_reset.1532115811 |
Directory | /workspace/0.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3095241282 |
Short name | T941 |
Test name | |
Test status | |
Simulation time | 1490259663 ps |
CPU time | 3.34 seconds |
Started | Jun 27 06:12:34 PM PDT 24 |
Finished | Jun 27 06:12:41 PM PDT 24 |
Peak memory | 210932 kb |
Host | smart-20eed0b7-c189-44bb-ac5c-550088936eb6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095241282 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.3095241282 |
Directory | /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1277774230 |
Short name | T946 |
Test name | |
Test status | |
Simulation time | 108908108 ps |
CPU time | 0.69 seconds |
Started | Jun 27 06:12:34 PM PDT 24 |
Finished | Jun 27 06:12:38 PM PDT 24 |
Peak memory | 202724 kb |
Host | smart-04e31a1b-39ca-47ad-87aa-908ba192c4df |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277774230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_csr_rw.1277774230 |
Directory | /workspace/0.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2517718092 |
Short name | T1018 |
Test name | |
Test status | |
Simulation time | 4827321267 ps |
CPU time | 25.72 seconds |
Started | Jun 27 06:12:34 PM PDT 24 |
Finished | Jun 27 06:13:04 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-9ae81881-0797-4ebd-8b73-19673568353e |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517718092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.2517718092 |
Directory | /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2872517697 |
Short name | T954 |
Test name | |
Test status | |
Simulation time | 88811357 ps |
CPU time | 0.86 seconds |
Started | Jun 27 06:12:32 PM PDT 24 |
Finished | Jun 27 06:12:35 PM PDT 24 |
Peak memory | 202700 kb |
Host | smart-cb4aa348-fe6c-44d3-a405-f0fd2fecced5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872517697 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.2872517697 |
Directory | /workspace/0.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4030611780 |
Short name | T969 |
Test name | |
Test status | |
Simulation time | 23875925 ps |
CPU time | 2.33 seconds |
Started | Jun 27 06:12:34 PM PDT 24 |
Finished | Jun 27 06:12:40 PM PDT 24 |
Peak memory | 210808 kb |
Host | smart-9713c67e-2add-4fcb-903c-09f714b7d2c1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030611780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 0.sram_ctrl_tl_errors.4030611780 |
Directory | /workspace/0.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3045666037 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 661787572 ps |
CPU time | 2.28 seconds |
Started | Jun 27 06:12:32 PM PDT 24 |
Finished | Jun 27 06:12:36 PM PDT 24 |
Peak memory | 211088 kb |
Host | smart-c6a63cc6-57a2-4205-beb8-42f655fccba4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045666037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.sram_ctrl_tl_intg_err.3045666037 |
Directory | /workspace/0.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2223908454 |
Short name | T1024 |
Test name | |
Test status | |
Simulation time | 24763846 ps |
CPU time | 0.76 seconds |
Started | Jun 27 06:12:32 PM PDT 24 |
Finished | Jun 27 06:12:35 PM PDT 24 |
Peak memory | 202668 kb |
Host | smart-95ba855d-4f1f-4962-9a37-489933669a9e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223908454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_aliasing.2223908454 |
Directory | /workspace/1.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3188847358 |
Short name | T943 |
Test name | |
Test status | |
Simulation time | 149259897 ps |
CPU time | 1.24 seconds |
Started | Jun 27 06:12:32 PM PDT 24 |
Finished | Jun 27 06:12:35 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-e84ee0ef-77f8-4724-a130-c4fcabee5187 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188847358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_bit_bash.3188847358 |
Directory | /workspace/1.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2020681459 |
Short name | T1000 |
Test name | |
Test status | |
Simulation time | 32301146 ps |
CPU time | 0.68 seconds |
Started | Jun 27 06:12:32 PM PDT 24 |
Finished | Jun 27 06:12:34 PM PDT 24 |
Peak memory | 202640 kb |
Host | smart-7fa66235-6abd-4dcd-8f68-29443a121252 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020681459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_hw_reset.2020681459 |
Directory | /workspace/1.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.660888832 |
Short name | T944 |
Test name | |
Test status | |
Simulation time | 1424899624 ps |
CPU time | 3.91 seconds |
Started | Jun 27 06:12:33 PM PDT 24 |
Finished | Jun 27 06:12:41 PM PDT 24 |
Peak memory | 211100 kb |
Host | smart-04990f82-8144-4d07-bbdc-99775019e6d4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660888832 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.660888832 |
Directory | /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2320878607 |
Short name | T991 |
Test name | |
Test status | |
Simulation time | 32998759 ps |
CPU time | 0.66 seconds |
Started | Jun 27 06:12:32 PM PDT 24 |
Finished | Jun 27 06:12:36 PM PDT 24 |
Peak memory | 202596 kb |
Host | smart-4af983e5-9cf6-4fa5-b1db-b6d1f5c474d9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320878607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_csr_rw.2320878607 |
Directory | /workspace/1.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2531920500 |
Short name | T978 |
Test name | |
Test status | |
Simulation time | 117373090501 ps |
CPU time | 59.11 seconds |
Started | Jun 27 06:12:32 PM PDT 24 |
Finished | Jun 27 06:13:34 PM PDT 24 |
Peak memory | 203088 kb |
Host | smart-0ace043e-fdf8-4068-a1e3-a81db8b8ce74 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531920500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.2531920500 |
Directory | /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.387881249 |
Short name | T951 |
Test name | |
Test status | |
Simulation time | 24014072 ps |
CPU time | 0.79 seconds |
Started | Jun 27 06:12:33 PM PDT 24 |
Finished | Jun 27 06:12:38 PM PDT 24 |
Peak memory | 202720 kb |
Host | smart-b83c722c-8030-4431-abc0-a3c7472590eb |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387881249 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.387881249 |
Directory | /workspace/1.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2963534333 |
Short name | T974 |
Test name | |
Test status | |
Simulation time | 37267969 ps |
CPU time | 3.35 seconds |
Started | Jun 27 06:12:34 PM PDT 24 |
Finished | Jun 27 06:12:41 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-5a20feb8-65b4-43d2-9caf-05df2d5e49f7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963534333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 1.sram_ctrl_tl_errors.2963534333 |
Directory | /workspace/1.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1603042278 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 178118686 ps |
CPU time | 1.6 seconds |
Started | Jun 27 06:12:36 PM PDT 24 |
Finished | Jun 27 06:12:43 PM PDT 24 |
Peak memory | 211140 kb |
Host | smart-144534cd-390d-45e2-a374-241ac72a7b0d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603042278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.sram_ctrl_tl_intg_err.1603042278 |
Directory | /workspace/1.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1787631016 |
Short name | T1033 |
Test name | |
Test status | |
Simulation time | 1867290096 ps |
CPU time | 4.4 seconds |
Started | Jun 27 06:12:49 PM PDT 24 |
Finished | Jun 27 06:12:57 PM PDT 24 |
Peak memory | 211088 kb |
Host | smart-1a2310c1-e0c8-4370-ba90-f77ccb1a9cb1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787631016 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.1787631016 |
Directory | /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2388519961 |
Short name | T979 |
Test name | |
Test status | |
Simulation time | 33063245 ps |
CPU time | 0.73 seconds |
Started | Jun 27 06:12:34 PM PDT 24 |
Finished | Jun 27 06:12:39 PM PDT 24 |
Peak memory | 202672 kb |
Host | smart-d08655c5-f2eb-48f4-8094-8867a1117273 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388519961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_csr_rw.2388519961 |
Directory | /workspace/10.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1334621850 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 7373462782 ps |
CPU time | 26.02 seconds |
Started | Jun 27 06:12:35 PM PDT 24 |
Finished | Jun 27 06:13:06 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-fd234a90-7395-4f91-bec7-51b9a0d52c81 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334621850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.1334621850 |
Directory | /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3262898451 |
Short name | T1034 |
Test name | |
Test status | |
Simulation time | 21423498 ps |
CPU time | 0.74 seconds |
Started | Jun 27 06:12:47 PM PDT 24 |
Finished | Jun 27 06:12:50 PM PDT 24 |
Peak memory | 202676 kb |
Host | smart-b392d077-1522-4e1b-acbb-130036f1e8c8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262898451 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.3262898451 |
Directory | /workspace/10.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1682522979 |
Short name | T1016 |
Test name | |
Test status | |
Simulation time | 116073831 ps |
CPU time | 4.21 seconds |
Started | Jun 27 06:12:35 PM PDT 24 |
Finished | Jun 27 06:12:44 PM PDT 24 |
Peak memory | 211196 kb |
Host | smart-b3e0c6f2-7e77-4e1e-97bf-de059023143c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682522979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 10.sram_ctrl_tl_errors.1682522979 |
Directory | /workspace/10.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1419712336 |
Short name | T1021 |
Test name | |
Test status | |
Simulation time | 1890289888 ps |
CPU time | 3.81 seconds |
Started | Jun 27 06:12:46 PM PDT 24 |
Finished | Jun 27 06:12:51 PM PDT 24 |
Peak memory | 212268 kb |
Host | smart-02f783dd-0780-4343-ab7c-446045dbc246 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419712336 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.1419712336 |
Directory | /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.678342132 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 100507901 ps |
CPU time | 0.65 seconds |
Started | Jun 27 06:12:47 PM PDT 24 |
Finished | Jun 27 06:12:50 PM PDT 24 |
Peak memory | 202676 kb |
Host | smart-6d5e76c5-fbf1-46c1-9183-5124cb686e17 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678342132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 11.sram_ctrl_csr_rw.678342132 |
Directory | /workspace/11.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.960763093 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 59639674 ps |
CPU time | 0.74 seconds |
Started | Jun 27 06:12:48 PM PDT 24 |
Finished | Jun 27 06:12:51 PM PDT 24 |
Peak memory | 202620 kb |
Host | smart-8e4cff69-937f-4e6a-bac7-770a04cf4c87 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960763093 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.960763093 |
Directory | /workspace/11.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1678740855 |
Short name | T968 |
Test name | |
Test status | |
Simulation time | 433279615 ps |
CPU time | 3.82 seconds |
Started | Jun 27 06:12:49 PM PDT 24 |
Finished | Jun 27 06:12:56 PM PDT 24 |
Peak memory | 211056 kb |
Host | smart-fb6f56e7-b3d6-4b35-b24f-0fc24d1e6b47 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678740855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 11.sram_ctrl_tl_errors.1678740855 |
Directory | /workspace/11.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1504876844 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 271927496 ps |
CPU time | 2.46 seconds |
Started | Jun 27 06:12:50 PM PDT 24 |
Finished | Jun 27 06:12:57 PM PDT 24 |
Peak memory | 211148 kb |
Host | smart-bb0307a5-7560-4f4e-9e9f-ab9bd2a2b920 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504876844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 11.sram_ctrl_tl_intg_err.1504876844 |
Directory | /workspace/11.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1172294096 |
Short name | T970 |
Test name | |
Test status | |
Simulation time | 695023222 ps |
CPU time | 3.81 seconds |
Started | Jun 27 06:12:48 PM PDT 24 |
Finished | Jun 27 06:12:55 PM PDT 24 |
Peak memory | 210948 kb |
Host | smart-9191b17e-636c-4815-8c28-0964b0596b05 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172294096 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.1172294096 |
Directory | /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1780057889 |
Short name | T993 |
Test name | |
Test status | |
Simulation time | 25807745 ps |
CPU time | 0.67 seconds |
Started | Jun 27 06:12:48 PM PDT 24 |
Finished | Jun 27 06:12:51 PM PDT 24 |
Peak memory | 202560 kb |
Host | smart-88ebd3ae-56f4-43f9-b77f-cf2dd2209fb4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780057889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_csr_rw.1780057889 |
Directory | /workspace/12.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3140319592 |
Short name | T1001 |
Test name | |
Test status | |
Simulation time | 3820684740 ps |
CPU time | 25.65 seconds |
Started | Jun 27 06:12:48 PM PDT 24 |
Finished | Jun 27 06:13:17 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-d377ae55-1ede-44f1-9984-ee33b85dbc15 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140319592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.3140319592 |
Directory | /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3763110255 |
Short name | T1005 |
Test name | |
Test status | |
Simulation time | 25590194 ps |
CPU time | 0.76 seconds |
Started | Jun 27 06:12:47 PM PDT 24 |
Finished | Jun 27 06:12:49 PM PDT 24 |
Peak memory | 202684 kb |
Host | smart-005373dd-d1ff-46a0-9a51-7cdb751eb815 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763110255 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.3763110255 |
Directory | /workspace/12.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3968158742 |
Short name | T962 |
Test name | |
Test status | |
Simulation time | 19683115 ps |
CPU time | 1.84 seconds |
Started | Jun 27 06:12:49 PM PDT 24 |
Finished | Jun 27 06:12:54 PM PDT 24 |
Peak memory | 211108 kb |
Host | smart-e7de1a13-7388-4796-9eec-ab5227b19ee1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968158742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 12.sram_ctrl_tl_errors.3968158742 |
Directory | /workspace/12.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4126810846 |
Short name | T996 |
Test name | |
Test status | |
Simulation time | 368364622 ps |
CPU time | 4.61 seconds |
Started | Jun 27 06:12:55 PM PDT 24 |
Finished | Jun 27 06:13:01 PM PDT 24 |
Peak memory | 212124 kb |
Host | smart-a8e6c5d2-724d-479f-9920-f333eb25b2e7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126810846 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.4126810846 |
Directory | /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2569461246 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 43056595 ps |
CPU time | 0.71 seconds |
Started | Jun 27 06:12:48 PM PDT 24 |
Finished | Jun 27 06:12:51 PM PDT 24 |
Peak memory | 202680 kb |
Host | smart-03ca7b15-f50b-48d4-b709-37aa877c8a3e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569461246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_csr_rw.2569461246 |
Directory | /workspace/13.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1008379674 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 28194914866 ps |
CPU time | 61.34 seconds |
Started | Jun 27 06:12:48 PM PDT 24 |
Finished | Jun 27 06:13:52 PM PDT 24 |
Peak memory | 203136 kb |
Host | smart-1f61f2d3-7de9-4b25-b665-7241ecb52d61 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008379674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.1008379674 |
Directory | /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2475719037 |
Short name | T952 |
Test name | |
Test status | |
Simulation time | 18229635 ps |
CPU time | 0.71 seconds |
Started | Jun 27 06:12:50 PM PDT 24 |
Finished | Jun 27 06:12:54 PM PDT 24 |
Peak memory | 202668 kb |
Host | smart-715cffa9-eca5-4bc8-9d93-f8ac6cb32be9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475719037 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.2475719037 |
Directory | /workspace/13.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1082870960 |
Short name | T1012 |
Test name | |
Test status | |
Simulation time | 336308561 ps |
CPU time | 3.22 seconds |
Started | Jun 27 06:12:47 PM PDT 24 |
Finished | Jun 27 06:12:53 PM PDT 24 |
Peak memory | 212220 kb |
Host | smart-54cd453a-be30-4b32-a5df-a4e174e38289 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082870960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 13.sram_ctrl_tl_errors.1082870960 |
Directory | /workspace/13.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2321198246 |
Short name | T1027 |
Test name | |
Test status | |
Simulation time | 382603666 ps |
CPU time | 2.62 seconds |
Started | Jun 27 06:12:50 PM PDT 24 |
Finished | Jun 27 06:12:56 PM PDT 24 |
Peak memory | 211320 kb |
Host | smart-336b9e5c-75b4-4dcb-919f-8d4fd525ad1c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321198246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 13.sram_ctrl_tl_intg_err.2321198246 |
Directory | /workspace/13.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2749064163 |
Short name | T1023 |
Test name | |
Test status | |
Simulation time | 1570424230 ps |
CPU time | 3.44 seconds |
Started | Jun 27 06:12:47 PM PDT 24 |
Finished | Jun 27 06:12:53 PM PDT 24 |
Peak memory | 210944 kb |
Host | smart-ea186052-36a3-4f44-a6d5-5901214b3aba |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749064163 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.2749064163 |
Directory | /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2451692014 |
Short name | T956 |
Test name | |
Test status | |
Simulation time | 45819107 ps |
CPU time | 0.68 seconds |
Started | Jun 27 06:12:49 PM PDT 24 |
Finished | Jun 27 06:12:53 PM PDT 24 |
Peak memory | 202596 kb |
Host | smart-1997be85-b798-4ba0-be6d-275afc8caaae |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451692014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_csr_rw.2451692014 |
Directory | /workspace/14.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.431258287 |
Short name | T992 |
Test name | |
Test status | |
Simulation time | 23354857486 ps |
CPU time | 24.97 seconds |
Started | Jun 27 06:12:48 PM PDT 24 |
Finished | Jun 27 06:13:16 PM PDT 24 |
Peak memory | 203096 kb |
Host | smart-287199cf-76ad-4c46-91c6-d4849bebfaf8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431258287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.431258287 |
Directory | /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3202179684 |
Short name | T964 |
Test name | |
Test status | |
Simulation time | 49368518 ps |
CPU time | 0.73 seconds |
Started | Jun 27 06:12:49 PM PDT 24 |
Finished | Jun 27 06:12:54 PM PDT 24 |
Peak memory | 202680 kb |
Host | smart-c263f443-cebf-4076-89c0-fc69d28f4294 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202179684 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.3202179684 |
Directory | /workspace/14.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.994116820 |
Short name | T947 |
Test name | |
Test status | |
Simulation time | 141344846 ps |
CPU time | 3.96 seconds |
Started | Jun 27 06:12:51 PM PDT 24 |
Finished | Jun 27 06:12:59 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-3278c39c-0b03-4f43-b3eb-ed15770bda44 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994116820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_errors.994116820 |
Directory | /workspace/14.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.4152453520 |
Short name | T982 |
Test name | |
Test status | |
Simulation time | 141281478 ps |
CPU time | 1.63 seconds |
Started | Jun 27 06:12:50 PM PDT 24 |
Finished | Jun 27 06:12:55 PM PDT 24 |
Peak memory | 211104 kb |
Host | smart-b03b3a8c-c638-4cdb-99a3-cba8f0c0e4bd |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152453520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 14.sram_ctrl_tl_intg_err.4152453520 |
Directory | /workspace/14.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2458695550 |
Short name | T1006 |
Test name | |
Test status | |
Simulation time | 3180766149 ps |
CPU time | 4.8 seconds |
Started | Jun 27 06:13:08 PM PDT 24 |
Finished | Jun 27 06:13:14 PM PDT 24 |
Peak memory | 211196 kb |
Host | smart-5015698e-9bfd-44ba-be02-fb809862d342 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458695550 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.2458695550 |
Directory | /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.90516063 |
Short name | T1013 |
Test name | |
Test status | |
Simulation time | 25851604 ps |
CPU time | 0.65 seconds |
Started | Jun 27 06:12:50 PM PDT 24 |
Finished | Jun 27 06:12:55 PM PDT 24 |
Peak memory | 202680 kb |
Host | smart-c8941881-5a5e-4da3-93cf-9393a518dd26 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90516063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 15.sram_ctrl_csr_rw.90516063 |
Directory | /workspace/15.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2910375637 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 14671794691 ps |
CPU time | 54.53 seconds |
Started | Jun 27 06:12:50 PM PDT 24 |
Finished | Jun 27 06:13:48 PM PDT 24 |
Peak memory | 203088 kb |
Host | smart-f2f84e2a-91b4-4723-bf19-6350422cca15 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910375637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.2910375637 |
Directory | /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.200461981 |
Short name | T1002 |
Test name | |
Test status | |
Simulation time | 40478439 ps |
CPU time | 0.79 seconds |
Started | Jun 27 06:12:52 PM PDT 24 |
Finished | Jun 27 06:12:56 PM PDT 24 |
Peak memory | 202688 kb |
Host | smart-b6bfb6e7-3d1b-4c25-8cda-b1ccee3b2c99 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200461981 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.200461981 |
Directory | /workspace/15.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.976725302 |
Short name | T960 |
Test name | |
Test status | |
Simulation time | 36123611 ps |
CPU time | 2.98 seconds |
Started | Jun 27 06:12:48 PM PDT 24 |
Finished | Jun 27 06:12:54 PM PDT 24 |
Peak memory | 211100 kb |
Host | smart-94957180-f77a-4cb3-bb79-4d4a092db05d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976725302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_errors.976725302 |
Directory | /workspace/15.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1736813500 |
Short name | T980 |
Test name | |
Test status | |
Simulation time | 102121262 ps |
CPU time | 1.55 seconds |
Started | Jun 27 06:12:50 PM PDT 24 |
Finished | Jun 27 06:12:55 PM PDT 24 |
Peak memory | 211104 kb |
Host | smart-f559f644-8dea-4149-ad62-2a9c93cfa242 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736813500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 15.sram_ctrl_tl_intg_err.1736813500 |
Directory | /workspace/15.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3449581570 |
Short name | T1004 |
Test name | |
Test status | |
Simulation time | 2169788213 ps |
CPU time | 3.71 seconds |
Started | Jun 27 06:12:47 PM PDT 24 |
Finished | Jun 27 06:12:53 PM PDT 24 |
Peak memory | 210988 kb |
Host | smart-cfdc46c2-c598-411e-848f-95fd268213a8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449581570 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.3449581570 |
Directory | /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.4169436194 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 19934740 ps |
CPU time | 0.7 seconds |
Started | Jun 27 06:12:48 PM PDT 24 |
Finished | Jun 27 06:12:52 PM PDT 24 |
Peak memory | 202696 kb |
Host | smart-91bf0bbc-98da-4019-b53a-a4ab53cb67f8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169436194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_csr_rw.4169436194 |
Directory | /workspace/16.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2584333679 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 8095673187 ps |
CPU time | 49.53 seconds |
Started | Jun 27 06:12:46 PM PDT 24 |
Finished | Jun 27 06:13:38 PM PDT 24 |
Peak memory | 203036 kb |
Host | smart-92b65ca9-5207-4b49-987f-6b691beb5fb9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584333679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.2584333679 |
Directory | /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4070874707 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 53929140 ps |
CPU time | 0.75 seconds |
Started | Jun 27 06:12:50 PM PDT 24 |
Finished | Jun 27 06:12:55 PM PDT 24 |
Peak memory | 202676 kb |
Host | smart-eeba2838-1388-42e2-b94b-4a0da884e8a3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070874707 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.4070874707 |
Directory | /workspace/16.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4089345032 |
Short name | T973 |
Test name | |
Test status | |
Simulation time | 126715970 ps |
CPU time | 4.14 seconds |
Started | Jun 27 06:12:52 PM PDT 24 |
Finished | Jun 27 06:12:59 PM PDT 24 |
Peak memory | 211132 kb |
Host | smart-9393afcd-304a-47b2-8df8-e658f8286456 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089345032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 16.sram_ctrl_tl_errors.4089345032 |
Directory | /workspace/16.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2161337497 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 723871767 ps |
CPU time | 2.62 seconds |
Started | Jun 27 06:12:46 PM PDT 24 |
Finished | Jun 27 06:12:51 PM PDT 24 |
Peak memory | 211136 kb |
Host | smart-7e573a70-9257-4f4e-84a8-03fd2520158d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161337497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 16.sram_ctrl_tl_intg_err.2161337497 |
Directory | /workspace/16.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.4138256783 |
Short name | T988 |
Test name | |
Test status | |
Simulation time | 363769789 ps |
CPU time | 3.26 seconds |
Started | Jun 27 06:12:48 PM PDT 24 |
Finished | Jun 27 06:12:53 PM PDT 24 |
Peak memory | 210932 kb |
Host | smart-096f423d-ad73-4724-936e-17ee495e9a73 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138256783 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.4138256783 |
Directory | /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.183545786 |
Short name | T1022 |
Test name | |
Test status | |
Simulation time | 15920573 ps |
CPU time | 0.64 seconds |
Started | Jun 27 06:12:50 PM PDT 24 |
Finished | Jun 27 06:12:54 PM PDT 24 |
Peak memory | 202620 kb |
Host | smart-4742522d-028a-4bbd-a225-e0497d95b3f3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183545786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 17.sram_ctrl_csr_rw.183545786 |
Directory | /workspace/17.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1983207502 |
Short name | T995 |
Test name | |
Test status | |
Simulation time | 3882223325 ps |
CPU time | 29.8 seconds |
Started | Jun 27 06:12:48 PM PDT 24 |
Finished | Jun 27 06:13:21 PM PDT 24 |
Peak memory | 202940 kb |
Host | smart-8e24f8d4-ff4a-4a1b-82b9-305ddb229154 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983207502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.1983207502 |
Directory | /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3797214107 |
Short name | T1025 |
Test name | |
Test status | |
Simulation time | 38541322 ps |
CPU time | 0.69 seconds |
Started | Jun 27 06:12:49 PM PDT 24 |
Finished | Jun 27 06:12:54 PM PDT 24 |
Peak memory | 202616 kb |
Host | smart-a5866f54-d57d-4a08-9706-6587b0f195af |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797214107 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.3797214107 |
Directory | /workspace/17.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1684647501 |
Short name | T945 |
Test name | |
Test status | |
Simulation time | 109977653 ps |
CPU time | 1.96 seconds |
Started | Jun 27 06:12:48 PM PDT 24 |
Finished | Jun 27 06:12:52 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-f2376a43-c2c0-4069-9569-951f22534da1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684647501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 17.sram_ctrl_tl_errors.1684647501 |
Directory | /workspace/17.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.776880660 |
Short name | T1011 |
Test name | |
Test status | |
Simulation time | 210972652 ps |
CPU time | 1.81 seconds |
Started | Jun 27 06:12:46 PM PDT 24 |
Finished | Jun 27 06:12:50 PM PDT 24 |
Peak memory | 211136 kb |
Host | smart-d83173da-8355-4193-8af3-ba23e7daef1d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776880660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 17.sram_ctrl_tl_intg_err.776880660 |
Directory | /workspace/17.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3220780889 |
Short name | T983 |
Test name | |
Test status | |
Simulation time | 711323923 ps |
CPU time | 3.75 seconds |
Started | Jun 27 06:12:50 PM PDT 24 |
Finished | Jun 27 06:12:58 PM PDT 24 |
Peak memory | 211092 kb |
Host | smart-c1400b55-60c0-48a4-a330-e37f14f14821 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220780889 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.3220780889 |
Directory | /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2938329748 |
Short name | T994 |
Test name | |
Test status | |
Simulation time | 40052183 ps |
CPU time | 0.67 seconds |
Started | Jun 27 06:12:55 PM PDT 24 |
Finished | Jun 27 06:12:58 PM PDT 24 |
Peak memory | 202548 kb |
Host | smart-14e13ae1-96b7-4f78-aaac-4985368007cb |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938329748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_csr_rw.2938329748 |
Directory | /workspace/18.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2653899117 |
Short name | T1007 |
Test name | |
Test status | |
Simulation time | 24577309381 ps |
CPU time | 27.68 seconds |
Started | Jun 27 06:12:50 PM PDT 24 |
Finished | Jun 27 06:13:22 PM PDT 24 |
Peak memory | 203080 kb |
Host | smart-2512b071-1ae2-4170-b25c-5d6bb070c715 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653899117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.2653899117 |
Directory | /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.58726340 |
Short name | T976 |
Test name | |
Test status | |
Simulation time | 21340256 ps |
CPU time | 0.73 seconds |
Started | Jun 27 06:12:50 PM PDT 24 |
Finished | Jun 27 06:12:55 PM PDT 24 |
Peak memory | 202664 kb |
Host | smart-6563a14c-417e-4304-a1b7-798327d89912 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58726340 -assert nopostproc +UVM_TESTNAME=sram_ctr l_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.58726340 |
Directory | /workspace/18.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3563539726 |
Short name | T990 |
Test name | |
Test status | |
Simulation time | 218410046 ps |
CPU time | 2.34 seconds |
Started | Jun 27 06:12:49 PM PDT 24 |
Finished | Jun 27 06:12:54 PM PDT 24 |
Peak memory | 211060 kb |
Host | smart-7f57bb02-3a3e-4936-9ff3-3acb60166319 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563539726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 18.sram_ctrl_tl_errors.3563539726 |
Directory | /workspace/18.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3134109111 |
Short name | T1017 |
Test name | |
Test status | |
Simulation time | 247479006 ps |
CPU time | 1.43 seconds |
Started | Jun 27 06:12:48 PM PDT 24 |
Finished | Jun 27 06:12:51 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-b2875be6-149d-4993-9258-1d6ffb77a223 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134109111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 18.sram_ctrl_tl_intg_err.3134109111 |
Directory | /workspace/18.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3792836551 |
Short name | T985 |
Test name | |
Test status | |
Simulation time | 1471814989 ps |
CPU time | 3.75 seconds |
Started | Jun 27 06:12:55 PM PDT 24 |
Finished | Jun 27 06:13:01 PM PDT 24 |
Peak memory | 210924 kb |
Host | smart-506f5ee7-6081-445d-9326-43dd02a795b6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792836551 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.3792836551 |
Directory | /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.20003573 |
Short name | T997 |
Test name | |
Test status | |
Simulation time | 16127231 ps |
CPU time | 0.65 seconds |
Started | Jun 27 06:12:50 PM PDT 24 |
Finished | Jun 27 06:12:54 PM PDT 24 |
Peak memory | 202632 kb |
Host | smart-071ff374-e298-4041-a405-f4ba62828e08 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20003573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 19.sram_ctrl_csr_rw.20003573 |
Directory | /workspace/19.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.311224868 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 14798930360 ps |
CPU time | 27 seconds |
Started | Jun 27 06:12:48 PM PDT 24 |
Finished | Jun 27 06:13:17 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-dfe238b9-2245-44d3-b78f-613355f5f0dc |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311224868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.311224868 |
Directory | /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2877211021 |
Short name | T1020 |
Test name | |
Test status | |
Simulation time | 16246542 ps |
CPU time | 0.71 seconds |
Started | Jun 27 06:12:51 PM PDT 24 |
Finished | Jun 27 06:12:56 PM PDT 24 |
Peak memory | 202676 kb |
Host | smart-a1468fce-6b0e-4cbd-a31b-38f818a6997a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877211021 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.2877211021 |
Directory | /workspace/19.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2063056514 |
Short name | T987 |
Test name | |
Test status | |
Simulation time | 124263174 ps |
CPU time | 2.35 seconds |
Started | Jun 27 06:12:49 PM PDT 24 |
Finished | Jun 27 06:12:55 PM PDT 24 |
Peak memory | 211296 kb |
Host | smart-472f774e-7ebc-4048-8636-21d4734bf502 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063056514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 19.sram_ctrl_tl_errors.2063056514 |
Directory | /workspace/19.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3961797723 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 325044287 ps |
CPU time | 1.57 seconds |
Started | Jun 27 06:12:55 PM PDT 24 |
Finished | Jun 27 06:12:58 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-eacb7de4-240b-4a66-a48e-8c1d1c6a4e64 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961797723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 19.sram_ctrl_tl_intg_err.3961797723 |
Directory | /workspace/19.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3831398288 |
Short name | T984 |
Test name | |
Test status | |
Simulation time | 53482795 ps |
CPU time | 0.72 seconds |
Started | Jun 27 06:12:34 PM PDT 24 |
Finished | Jun 27 06:12:38 PM PDT 24 |
Peak memory | 202696 kb |
Host | smart-d1bae7fa-6e2e-4528-af90-21eadd548db5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831398288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_aliasing.3831398288 |
Directory | /workspace/2.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1411498318 |
Short name | T977 |
Test name | |
Test status | |
Simulation time | 137317022 ps |
CPU time | 2.1 seconds |
Started | Jun 27 06:12:33 PM PDT 24 |
Finished | Jun 27 06:12:38 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-60723d73-244e-4698-a120-cee643b7d874 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411498318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_bit_bash.1411498318 |
Directory | /workspace/2.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3575387004 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 15631698 ps |
CPU time | 0.66 seconds |
Started | Jun 27 06:12:33 PM PDT 24 |
Finished | Jun 27 06:12:36 PM PDT 24 |
Peak memory | 202636 kb |
Host | smart-d5c3bf5e-e0f2-4dc5-9580-81637a13099d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575387004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_hw_reset.3575387004 |
Directory | /workspace/2.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.744660172 |
Short name | T959 |
Test name | |
Test status | |
Simulation time | 1592591759 ps |
CPU time | 4.79 seconds |
Started | Jun 27 06:12:34 PM PDT 24 |
Finished | Jun 27 06:12:43 PM PDT 24 |
Peak memory | 212456 kb |
Host | smart-bbdf8c9a-ad0f-4e9b-9202-98977bbc25da |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744660172 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.744660172 |
Directory | /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.635547996 |
Short name | T963 |
Test name | |
Test status | |
Simulation time | 77920973 ps |
CPU time | 0.67 seconds |
Started | Jun 27 06:12:32 PM PDT 24 |
Finished | Jun 27 06:12:35 PM PDT 24 |
Peak memory | 202564 kb |
Host | smart-15d7f3e5-dea5-44f2-91da-7a01fbd27f33 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635547996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.sram_ctrl_csr_rw.635547996 |
Directory | /workspace/2.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.4018619198 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 41611337312 ps |
CPU time | 56.34 seconds |
Started | Jun 27 06:12:32 PM PDT 24 |
Finished | Jun 27 06:13:30 PM PDT 24 |
Peak memory | 203064 kb |
Host | smart-5f861f84-3607-4d43-82a7-a778bd8fd75c |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018619198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.4018619198 |
Directory | /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1297062818 |
Short name | T1019 |
Test name | |
Test status | |
Simulation time | 15738907 ps |
CPU time | 0.73 seconds |
Started | Jun 27 06:12:35 PM PDT 24 |
Finished | Jun 27 06:12:39 PM PDT 24 |
Peak memory | 202672 kb |
Host | smart-d17a7f95-d666-4f65-a8fc-40cf0da975c4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297062818 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.1297062818 |
Directory | /workspace/2.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1829670607 |
Short name | T1030 |
Test name | |
Test status | |
Simulation time | 139780492 ps |
CPU time | 4.33 seconds |
Started | Jun 27 06:12:35 PM PDT 24 |
Finished | Jun 27 06:12:43 PM PDT 24 |
Peak memory | 212436 kb |
Host | smart-34961bde-88a5-4ccd-98f2-91e45654ae3d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829670607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 2.sram_ctrl_tl_errors.1829670607 |
Directory | /workspace/2.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.4032311349 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 15213114 ps |
CPU time | 0.69 seconds |
Started | Jun 27 06:12:38 PM PDT 24 |
Finished | Jun 27 06:12:42 PM PDT 24 |
Peak memory | 202700 kb |
Host | smart-0f1183f6-f325-4a82-acff-60b79047aedf |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032311349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_aliasing.4032311349 |
Directory | /workspace/3.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3264238082 |
Short name | T999 |
Test name | |
Test status | |
Simulation time | 43999832 ps |
CPU time | 1.86 seconds |
Started | Jun 27 06:12:38 PM PDT 24 |
Finished | Jun 27 06:12:44 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-949bc88a-afe2-4bda-b71e-497962bd5fe4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264238082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_bit_bash.3264238082 |
Directory | /workspace/3.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3699969382 |
Short name | T975 |
Test name | |
Test status | |
Simulation time | 20681811 ps |
CPU time | 0.7 seconds |
Started | Jun 27 06:12:34 PM PDT 24 |
Finished | Jun 27 06:12:39 PM PDT 24 |
Peak memory | 202496 kb |
Host | smart-54be542d-2d63-4fbe-8c7a-904c321a1fad |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699969382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_hw_reset.3699969382 |
Directory | /workspace/3.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.4284035183 |
Short name | T1026 |
Test name | |
Test status | |
Simulation time | 721392571 ps |
CPU time | 3.77 seconds |
Started | Jun 27 06:12:35 PM PDT 24 |
Finished | Jun 27 06:12:44 PM PDT 24 |
Peak memory | 211216 kb |
Host | smart-ca934502-92f4-47f3-8fb7-8aee7b7d504d |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284035183 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.4284035183 |
Directory | /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2443401964 |
Short name | T966 |
Test name | |
Test status | |
Simulation time | 26351844 ps |
CPU time | 0.73 seconds |
Started | Jun 27 06:12:35 PM PDT 24 |
Finished | Jun 27 06:12:40 PM PDT 24 |
Peak memory | 202628 kb |
Host | smart-a477b9fc-8af6-420e-bc88-7c07891e33b5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443401964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_csr_rw.2443401964 |
Directory | /workspace/3.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3254252179 |
Short name | T1003 |
Test name | |
Test status | |
Simulation time | 14087442507 ps |
CPU time | 50.64 seconds |
Started | Jun 27 06:12:38 PM PDT 24 |
Finished | Jun 27 06:13:33 PM PDT 24 |
Peak memory | 203100 kb |
Host | smart-3a3ab5a0-9fab-4cad-a152-6998fa2a6024 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254252179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.3254252179 |
Directory | /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.884665745 |
Short name | T949 |
Test name | |
Test status | |
Simulation time | 41544155 ps |
CPU time | 0.69 seconds |
Started | Jun 27 06:12:34 PM PDT 24 |
Finished | Jun 27 06:12:39 PM PDT 24 |
Peak memory | 202696 kb |
Host | smart-65f3f8e3-c8ed-470b-af95-e875d4a54d93 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884665745 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.884665745 |
Directory | /workspace/3.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.4134782048 |
Short name | T1029 |
Test name | |
Test status | |
Simulation time | 95408239 ps |
CPU time | 3.43 seconds |
Started | Jun 27 06:12:38 PM PDT 24 |
Finished | Jun 27 06:12:46 PM PDT 24 |
Peak memory | 211072 kb |
Host | smart-85ee0960-7d33-4ece-9558-8f841fe756dd |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134782048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 3.sram_ctrl_tl_errors.4134782048 |
Directory | /workspace/3.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2476273131 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 140627189 ps |
CPU time | 2.25 seconds |
Started | Jun 27 06:12:35 PM PDT 24 |
Finished | Jun 27 06:12:41 PM PDT 24 |
Peak memory | 211136 kb |
Host | smart-72edc252-5dce-4daf-9d21-cb1b5d33e543 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476273131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.sram_ctrl_tl_intg_err.2476273131 |
Directory | /workspace/3.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1666596974 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 39305002 ps |
CPU time | 0.73 seconds |
Started | Jun 27 06:12:38 PM PDT 24 |
Finished | Jun 27 06:12:43 PM PDT 24 |
Peak memory | 202612 kb |
Host | smart-ae309543-073d-45a1-8e84-505c190ede25 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666596974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_aliasing.1666596974 |
Directory | /workspace/4.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.4031361702 |
Short name | T1031 |
Test name | |
Test status | |
Simulation time | 45121250 ps |
CPU time | 1.83 seconds |
Started | Jun 27 06:12:37 PM PDT 24 |
Finished | Jun 27 06:12:43 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-398f3e7f-27a2-4e40-b6d2-4358d5d527ee |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031361702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_bit_bash.4031361702 |
Directory | /workspace/4.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2455478511 |
Short name | T998 |
Test name | |
Test status | |
Simulation time | 28708221 ps |
CPU time | 0.7 seconds |
Started | Jun 27 06:12:39 PM PDT 24 |
Finished | Jun 27 06:12:43 PM PDT 24 |
Peak memory | 202708 kb |
Host | smart-146e0940-4575-4569-866c-9ac9b4b91735 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455478511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_hw_reset.2455478511 |
Directory | /workspace/4.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3922707956 |
Short name | T940 |
Test name | |
Test status | |
Simulation time | 369657831 ps |
CPU time | 3.23 seconds |
Started | Jun 27 06:12:38 PM PDT 24 |
Finished | Jun 27 06:12:46 PM PDT 24 |
Peak memory | 210868 kb |
Host | smart-5cbfcc1e-68da-4584-89c3-0b5960f39c61 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922707956 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.3922707956 |
Directory | /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.4274104018 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 14287767 ps |
CPU time | 0.65 seconds |
Started | Jun 27 06:12:38 PM PDT 24 |
Finished | Jun 27 06:12:43 PM PDT 24 |
Peak memory | 202640 kb |
Host | smart-449ff3f3-4580-4a20-9921-ac18b86c56a8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274104018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_csr_rw.4274104018 |
Directory | /workspace/4.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.586476886 |
Short name | T1032 |
Test name | |
Test status | |
Simulation time | 26109846 ps |
CPU time | 0.74 seconds |
Started | Jun 27 06:12:39 PM PDT 24 |
Finished | Jun 27 06:12:43 PM PDT 24 |
Peak memory | 202612 kb |
Host | smart-cbbbf062-19f3-404f-84a7-2fc5564dd5e1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586476886 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.586476886 |
Directory | /workspace/4.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3174093069 |
Short name | T1010 |
Test name | |
Test status | |
Simulation time | 48149375 ps |
CPU time | 1.97 seconds |
Started | Jun 27 06:12:38 PM PDT 24 |
Finished | Jun 27 06:12:44 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-3930cb27-2b08-4cbd-b02d-4a68be4cd051 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174093069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 4.sram_ctrl_tl_errors.3174093069 |
Directory | /workspace/4.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2981139289 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 187824826 ps |
CPU time | 2.44 seconds |
Started | Jun 27 06:12:38 PM PDT 24 |
Finished | Jun 27 06:12:45 PM PDT 24 |
Peak memory | 211144 kb |
Host | smart-debc9cd6-3d68-4bf6-8904-7d25940c895a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981139289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.sram_ctrl_tl_intg_err.2981139289 |
Directory | /workspace/4.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2777679206 |
Short name | T972 |
Test name | |
Test status | |
Simulation time | 371366535 ps |
CPU time | 3.92 seconds |
Started | Jun 27 06:12:38 PM PDT 24 |
Finished | Jun 27 06:12:46 PM PDT 24 |
Peak memory | 211120 kb |
Host | smart-2abcc139-a407-4970-b58c-d7189a297e1f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777679206 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.2777679206 |
Directory | /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1353576801 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 30283228 ps |
CPU time | 0.71 seconds |
Started | Jun 27 06:12:38 PM PDT 24 |
Finished | Jun 27 06:12:43 PM PDT 24 |
Peak memory | 202696 kb |
Host | smart-e566b01b-c24d-4caa-aa2b-08d9752ff16d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353576801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_csr_rw.1353576801 |
Directory | /workspace/5.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3501641733 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 71359793340 ps |
CPU time | 54.72 seconds |
Started | Jun 27 06:12:39 PM PDT 24 |
Finished | Jun 27 06:13:37 PM PDT 24 |
Peak memory | 203012 kb |
Host | smart-21114f61-29a3-4050-b9d4-9971642ae31f |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501641733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.3501641733 |
Directory | /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1851709792 |
Short name | T971 |
Test name | |
Test status | |
Simulation time | 23482473 ps |
CPU time | 0.81 seconds |
Started | Jun 27 06:12:34 PM PDT 24 |
Finished | Jun 27 06:12:38 PM PDT 24 |
Peak memory | 202328 kb |
Host | smart-0b1632ba-7cf9-4521-918a-72b6f8d6cbb7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851709792 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.1851709792 |
Directory | /workspace/5.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.853740277 |
Short name | T1009 |
Test name | |
Test status | |
Simulation time | 157643240 ps |
CPU time | 5.19 seconds |
Started | Jun 27 06:12:39 PM PDT 24 |
Finished | Jun 27 06:12:48 PM PDT 24 |
Peak memory | 211096 kb |
Host | smart-5ad0c01e-ec56-483d-bb54-fda4600169d3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853740277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_errors.853740277 |
Directory | /workspace/5.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3545583573 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 267048238 ps |
CPU time | 1.78 seconds |
Started | Jun 27 06:12:34 PM PDT 24 |
Finished | Jun 27 06:12:39 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-04bea434-22bb-4b42-a5c2-8332ef904002 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545583573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 5.sram_ctrl_tl_intg_err.3545583573 |
Directory | /workspace/5.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.682160708 |
Short name | T948 |
Test name | |
Test status | |
Simulation time | 2676963113 ps |
CPU time | 4.33 seconds |
Started | Jun 27 06:12:40 PM PDT 24 |
Finished | Jun 27 06:12:48 PM PDT 24 |
Peak memory | 210980 kb |
Host | smart-86c4e561-9770-458b-884a-6147741f4834 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682160708 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.682160708 |
Directory | /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2441991236 |
Short name | T961 |
Test name | |
Test status | |
Simulation time | 42380652 ps |
CPU time | 0.63 seconds |
Started | Jun 27 06:12:40 PM PDT 24 |
Finished | Jun 27 06:12:44 PM PDT 24 |
Peak memory | 202648 kb |
Host | smart-d2743f31-8357-4634-b3e5-437c038c2321 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441991236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_csr_rw.2441991236 |
Directory | /workspace/6.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.4259050363 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 29432346856 ps |
CPU time | 50 seconds |
Started | Jun 27 06:12:38 PM PDT 24 |
Finished | Jun 27 06:13:32 PM PDT 24 |
Peak memory | 203148 kb |
Host | smart-65f486e4-15d1-4182-ab6b-1b0da1caedc7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259050363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.4259050363 |
Directory | /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1139258589 |
Short name | T1015 |
Test name | |
Test status | |
Simulation time | 29354307 ps |
CPU time | 0.75 seconds |
Started | Jun 27 06:12:40 PM PDT 24 |
Finished | Jun 27 06:12:44 PM PDT 24 |
Peak memory | 202644 kb |
Host | smart-3e20595a-6f60-490b-9f1b-bb1647ead48e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139258589 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.1139258589 |
Directory | /workspace/6.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2106094726 |
Short name | T1014 |
Test name | |
Test status | |
Simulation time | 300433093 ps |
CPU time | 4.88 seconds |
Started | Jun 27 06:12:39 PM PDT 24 |
Finished | Jun 27 06:12:48 PM PDT 24 |
Peak memory | 211112 kb |
Host | smart-16fb3aa6-3b6d-4496-905a-95dbb5955dcc |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106094726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 6.sram_ctrl_tl_errors.2106094726 |
Directory | /workspace/6.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1529675367 |
Short name | T955 |
Test name | |
Test status | |
Simulation time | 355787992 ps |
CPU time | 3.35 seconds |
Started | Jun 27 06:12:35 PM PDT 24 |
Finished | Jun 27 06:12:43 PM PDT 24 |
Peak memory | 210880 kb |
Host | smart-0ae4b42b-92e9-45e5-8142-0c26010f4f30 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529675367 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.1529675367 |
Directory | /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3156426191 |
Short name | T1008 |
Test name | |
Test status | |
Simulation time | 29396524 ps |
CPU time | 0.66 seconds |
Started | Jun 27 06:12:34 PM PDT 24 |
Finished | Jun 27 06:12:39 PM PDT 24 |
Peak memory | 202632 kb |
Host | smart-5be11227-3831-45f1-a7d6-aa15a8dac9ed |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156426191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_csr_rw.3156426191 |
Directory | /workspace/7.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.170340358 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 7432697860 ps |
CPU time | 47.92 seconds |
Started | Jun 27 06:12:38 PM PDT 24 |
Finished | Jun 27 06:13:30 PM PDT 24 |
Peak memory | 203156 kb |
Host | smart-dce85ef7-7399-4887-bef6-f8b2356702f5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170340358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.170340358 |
Directory | /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2143640648 |
Short name | T950 |
Test name | |
Test status | |
Simulation time | 51196394 ps |
CPU time | 0.73 seconds |
Started | Jun 27 06:12:33 PM PDT 24 |
Finished | Jun 27 06:12:36 PM PDT 24 |
Peak memory | 202672 kb |
Host | smart-9368e857-4be5-456d-9143-616870ef305b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143640648 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.2143640648 |
Directory | /workspace/7.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.478847719 |
Short name | T1028 |
Test name | |
Test status | |
Simulation time | 30068657 ps |
CPU time | 2.58 seconds |
Started | Jun 27 06:12:40 PM PDT 24 |
Finished | Jun 27 06:12:46 PM PDT 24 |
Peak memory | 210996 kb |
Host | smart-4e71ba06-6501-4566-8194-4f8898f3c127 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478847719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_errors.478847719 |
Directory | /workspace/7.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.327359896 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 250567803 ps |
CPU time | 1.44 seconds |
Started | Jun 27 06:12:34 PM PDT 24 |
Finished | Jun 27 06:12:39 PM PDT 24 |
Peak memory | 202944 kb |
Host | smart-c774add8-219e-415c-a11f-1e078811862d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327359896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 7.sram_ctrl_tl_intg_err.327359896 |
Directory | /workspace/7.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3053187088 |
Short name | T965 |
Test name | |
Test status | |
Simulation time | 391374216 ps |
CPU time | 3.54 seconds |
Started | Jun 27 06:12:33 PM PDT 24 |
Finished | Jun 27 06:12:40 PM PDT 24 |
Peak memory | 210940 kb |
Host | smart-6c7a50e4-cb61-4a6c-bd9e-24660800d6f0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053187088 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.3053187088 |
Directory | /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3552661603 |
Short name | T953 |
Test name | |
Test status | |
Simulation time | 17865913 ps |
CPU time | 0.69 seconds |
Started | Jun 27 06:12:33 PM PDT 24 |
Finished | Jun 27 06:12:38 PM PDT 24 |
Peak memory | 202556 kb |
Host | smart-cdb2632a-6520-4e05-a02e-043cb4cfde41 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552661603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_csr_rw.3552661603 |
Directory | /workspace/8.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1424169661 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 23017123892 ps |
CPU time | 30.05 seconds |
Started | Jun 27 06:12:33 PM PDT 24 |
Finished | Jun 27 06:13:06 PM PDT 24 |
Peak memory | 203072 kb |
Host | smart-b6276a07-04b9-4996-9163-5dd94968e84b |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424169661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.1424169661 |
Directory | /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2044837988 |
Short name | T981 |
Test name | |
Test status | |
Simulation time | 36257720 ps |
CPU time | 0.84 seconds |
Started | Jun 27 06:12:33 PM PDT 24 |
Finished | Jun 27 06:12:37 PM PDT 24 |
Peak memory | 202672 kb |
Host | smart-43509353-a9e4-431a-9ba2-e43dfe1b7833 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044837988 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.2044837988 |
Directory | /workspace/8.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3596641572 |
Short name | T986 |
Test name | |
Test status | |
Simulation time | 490748303 ps |
CPU time | 4.4 seconds |
Started | Jun 27 06:12:34 PM PDT 24 |
Finished | Jun 27 06:12:42 PM PDT 24 |
Peak memory | 211072 kb |
Host | smart-39941a74-e92a-4331-bc31-db1bf2966dcc |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596641572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 8.sram_ctrl_tl_errors.3596641572 |
Directory | /workspace/8.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2858440464 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 213082344 ps |
CPU time | 1.37 seconds |
Started | Jun 27 06:12:34 PM PDT 24 |
Finished | Jun 27 06:12:40 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-a013dabe-6eda-4345-b50b-5dcd30f4d5bd |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858440464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 8.sram_ctrl_tl_intg_err.2858440464 |
Directory | /workspace/8.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4022250148 |
Short name | T958 |
Test name | |
Test status | |
Simulation time | 361788498 ps |
CPU time | 3.52 seconds |
Started | Jun 27 06:12:34 PM PDT 24 |
Finished | Jun 27 06:12:41 PM PDT 24 |
Peak memory | 210940 kb |
Host | smart-eb16a2ce-b61e-4c53-971d-bcd7b0079277 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022250148 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.4022250148 |
Directory | /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1131440017 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 44120234 ps |
CPU time | 0.71 seconds |
Started | Jun 27 06:12:35 PM PDT 24 |
Finished | Jun 27 06:12:40 PM PDT 24 |
Peak memory | 202588 kb |
Host | smart-c80836b3-010b-4965-adfa-974618b3ae6b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131440017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_csr_rw.1131440017 |
Directory | /workspace/9.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.693273532 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 3774142506 ps |
CPU time | 27.51 seconds |
Started | Jun 27 06:12:35 PM PDT 24 |
Finished | Jun 27 06:13:08 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-a5257ff3-851d-4adf-a9e1-6e14ad28dfd5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693273532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.693273532 |
Directory | /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2173700526 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 173449835 ps |
CPU time | 0.69 seconds |
Started | Jun 27 06:12:34 PM PDT 24 |
Finished | Jun 27 06:12:39 PM PDT 24 |
Peak memory | 202660 kb |
Host | smart-7318a1b8-7cf3-4243-99ee-2d24cdfa61a2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173700526 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.2173700526 |
Directory | /workspace/9.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2994129449 |
Short name | T989 |
Test name | |
Test status | |
Simulation time | 22957074 ps |
CPU time | 2.19 seconds |
Started | Jun 27 06:12:34 PM PDT 24 |
Finished | Jun 27 06:12:40 PM PDT 24 |
Peak memory | 211036 kb |
Host | smart-b0058ca5-b201-488d-96fe-649e31107457 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994129449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 9.sram_ctrl_tl_errors.2994129449 |
Directory | /workspace/9.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2113774635 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 132109878 ps |
CPU time | 1.36 seconds |
Started | Jun 27 06:12:34 PM PDT 24 |
Finished | Jun 27 06:12:39 PM PDT 24 |
Peak memory | 211052 kb |
Host | smart-53c36bc5-14ca-493e-abc2-ff64b4bfbf83 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113774635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 9.sram_ctrl_tl_intg_err.2113774635 |
Directory | /workspace/9.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_access_during_key_req.93742075 |
Short name | T546 |
Test name | |
Test status | |
Simulation time | 9822533095 ps |
CPU time | 857.31 seconds |
Started | Jun 27 06:49:09 PM PDT 24 |
Finished | Jun 27 07:03:28 PM PDT 24 |
Peak memory | 379756 kb |
Host | smart-036f983f-1574-4dcc-aa14-ef7e13808ba8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93742075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 0.sram_ctrl_access_during_key_req.93742075 |
Directory | /workspace/0.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_alert_test.4275747798 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 18566638 ps |
CPU time | 0.73 seconds |
Started | Jun 27 06:48:57 PM PDT 24 |
Finished | Jun 27 06:49:02 PM PDT 24 |
Peak memory | 202616 kb |
Host | smart-93dda084-ec7b-462e-ba2d-91425a667873 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275747798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.4275747798 |
Directory | /workspace/0.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_bijection.2527639961 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 33468656560 ps |
CPU time | 1226.91 seconds |
Started | Jun 27 06:48:58 PM PDT 24 |
Finished | Jun 27 07:09:30 PM PDT 24 |
Peak memory | 203692 kb |
Host | smart-629c2f61-d277-43de-a26d-796c86908ca6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527639961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection. 2527639961 |
Directory | /workspace/0.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_executable.3952251320 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 2332815340 ps |
CPU time | 452.41 seconds |
Started | Jun 27 06:48:59 PM PDT 24 |
Finished | Jun 27 06:56:37 PM PDT 24 |
Peak memory | 370516 kb |
Host | smart-6318d2d0-48f6-45e5-8cb2-7fcaeb326734 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952251320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executabl e.3952251320 |
Directory | /workspace/0.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_lc_escalation.1685708114 |
Short name | T804 |
Test name | |
Test status | |
Simulation time | 8162043405 ps |
CPU time | 43.51 seconds |
Started | Jun 27 06:48:59 PM PDT 24 |
Finished | Jun 27 06:49:47 PM PDT 24 |
Peak memory | 211092 kb |
Host | smart-fb183aa9-42e5-4419-8632-e0675fc3d6c4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685708114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esc alation.1685708114 |
Directory | /workspace/0.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_max_throughput.3565251899 |
Short name | T909 |
Test name | |
Test status | |
Simulation time | 2982643752 ps |
CPU time | 32.24 seconds |
Started | Jun 27 06:48:59 PM PDT 24 |
Finished | Jun 27 06:49:36 PM PDT 24 |
Peak memory | 284544 kb |
Host | smart-84cf4558-3a3e-4f71-985b-ba4b5328e0ec |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565251899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.sram_ctrl_max_throughput.3565251899 |
Directory | /workspace/0.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_mem_partial_access.1446010736 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 1918042156 ps |
CPU time | 120.6 seconds |
Started | Jun 27 06:48:59 PM PDT 24 |
Finished | Jun 27 06:51:04 PM PDT 24 |
Peak memory | 210972 kb |
Host | smart-1d54123d-9b63-4776-b524-f121abd134ec |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446010736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_mem_partial_access.1446010736 |
Directory | /workspace/0.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_mem_walk.2210629848 |
Short name | T548 |
Test name | |
Test status | |
Simulation time | 26575356315 ps |
CPU time | 193.07 seconds |
Started | Jun 27 06:48:58 PM PDT 24 |
Finished | Jun 27 06:52:16 PM PDT 24 |
Peak memory | 211032 kb |
Host | smart-ac8ec30c-c4fd-40d2-bb47-216bb3fa9972 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210629848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl _mem_walk.2210629848 |
Directory | /workspace/0.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_multiple_keys.3173016348 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 8264073903 ps |
CPU time | 102.42 seconds |
Started | Jun 27 06:48:58 PM PDT 24 |
Finished | Jun 27 06:50:46 PM PDT 24 |
Peak memory | 283620 kb |
Host | smart-465b4766-b380-4e54-af47-9a6bf9175717 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173016348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip le_keys.3173016348 |
Directory | /workspace/0.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_partial_access.1169670939 |
Short name | T773 |
Test name | |
Test status | |
Simulation time | 1165388524 ps |
CPU time | 34.31 seconds |
Started | Jun 27 06:49:09 PM PDT 24 |
Finished | Jun 27 06:49:45 PM PDT 24 |
Peak memory | 280876 kb |
Host | smart-15c5d3b4-17b4-486b-a4f5-093166b6156b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169670939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s ram_ctrl_partial_access.1169670939 |
Directory | /workspace/0.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2307948168 |
Short name | T574 |
Test name | |
Test status | |
Simulation time | 18750775870 ps |
CPU time | 245.35 seconds |
Started | Jun 27 06:48:59 PM PDT 24 |
Finished | Jun 27 06:53:09 PM PDT 24 |
Peak memory | 202828 kb |
Host | smart-c804eeee-492c-4ba6-8fe4-0de2a80a11f9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307948168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.sram_ctrl_partial_access_b2b.2307948168 |
Directory | /workspace/0.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_ram_cfg.1379301362 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 1524535796 ps |
CPU time | 3.33 seconds |
Started | Jun 27 06:48:58 PM PDT 24 |
Finished | Jun 27 06:49:06 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-2f26da94-64e1-4521-b9d7-11a1d09a7904 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379301362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.1379301362 |
Directory | /workspace/0.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_regwen.3025690861 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 10860200098 ps |
CPU time | 471.16 seconds |
Started | Jun 27 06:48:55 PM PDT 24 |
Finished | Jun 27 06:56:51 PM PDT 24 |
Peak memory | 378712 kb |
Host | smart-b1419d64-6444-48b3-803d-c1715723ca2c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025690861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.3025690861 |
Directory | /workspace/0.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_smoke.3915397019 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 1018297101 ps |
CPU time | 13.8 seconds |
Started | Jun 27 06:49:00 PM PDT 24 |
Finished | Jun 27 06:49:18 PM PDT 24 |
Peak memory | 202756 kb |
Host | smart-2badb15f-31a9-437c-b720-02831be91dc0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915397019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.3915397019 |
Directory | /workspace/0.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_all.2517203669 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 205086530652 ps |
CPU time | 6790.21 seconds |
Started | Jun 27 06:49:00 PM PDT 24 |
Finished | Jun 27 08:42:15 PM PDT 24 |
Peak memory | 380844 kb |
Host | smart-a4e5fc68-ac3e-42c3-9df6-808f483b480c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517203669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 0.sram_ctrl_stress_all.2517203669 |
Directory | /workspace/0.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_pipeline.4223222686 |
Short name | T592 |
Test name | |
Test status | |
Simulation time | 33797657302 ps |
CPU time | 261.17 seconds |
Started | Jun 27 06:49:02 PM PDT 24 |
Finished | Jun 27 06:53:26 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-ef38ef2b-007b-4497-8dc0-7d46f1269337 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223222686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_stress_pipeline.4223222686 |
Directory | /workspace/0.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.4095858546 |
Short name | T845 |
Test name | |
Test status | |
Simulation time | 752634768 ps |
CPU time | 38.29 seconds |
Started | Jun 27 06:48:56 PM PDT 24 |
Finished | Jun 27 06:49:39 PM PDT 24 |
Peak memory | 284532 kb |
Host | smart-eb0bbf4a-998a-4491-a172-33ead3cfdc45 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095858546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.4095858546 |
Directory | /workspace/0.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_access_during_key_req.3560978011 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 81339172768 ps |
CPU time | 1858.42 seconds |
Started | Jun 27 06:48:58 PM PDT 24 |
Finished | Jun 27 07:20:01 PM PDT 24 |
Peak memory | 379772 kb |
Host | smart-d2967cad-c285-44e5-a490-5497d2767934 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560978011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_access_during_key_req.3560978011 |
Directory | /workspace/1.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_alert_test.1526888013 |
Short name | T926 |
Test name | |
Test status | |
Simulation time | 142417163 ps |
CPU time | 0.71 seconds |
Started | Jun 27 06:48:59 PM PDT 24 |
Finished | Jun 27 06:49:04 PM PDT 24 |
Peak memory | 202576 kb |
Host | smart-af2a837e-2bf8-4bac-bd56-5e815130647c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526888013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.1526888013 |
Directory | /workspace/1.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_bijection.4082590025 |
Short name | T549 |
Test name | |
Test status | |
Simulation time | 111437459184 ps |
CPU time | 681.45 seconds |
Started | Jun 27 06:49:02 PM PDT 24 |
Finished | Jun 27 07:00:27 PM PDT 24 |
Peak memory | 203444 kb |
Host | smart-32dec12e-3b59-42a5-b18e-a6be82c57aba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082590025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection. 4082590025 |
Directory | /workspace/1.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_executable.154969980 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 43367642615 ps |
CPU time | 674.6 seconds |
Started | Jun 27 06:48:59 PM PDT 24 |
Finished | Jun 27 07:00:18 PM PDT 24 |
Peak memory | 378764 kb |
Host | smart-1fe6486d-e8e3-4ea3-b21e-df8e005fbe82 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154969980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executable .154969980 |
Directory | /workspace/1.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_lc_escalation.2457274679 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 20664704424 ps |
CPU time | 85.01 seconds |
Started | Jun 27 06:48:55 PM PDT 24 |
Finished | Jun 27 06:50:24 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-0c0bb24e-c374-4972-b265-38281947b47d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457274679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esc alation.2457274679 |
Directory | /workspace/1.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_max_throughput.3274692050 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 758749236 ps |
CPU time | 94.75 seconds |
Started | Jun 27 06:49:02 PM PDT 24 |
Finished | Jun 27 06:50:40 PM PDT 24 |
Peak memory | 353952 kb |
Host | smart-290629de-5f70-42a1-b2ac-ba6d86af7ac3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274692050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_max_throughput.3274692050 |
Directory | /workspace/1.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_mem_partial_access.1377340245 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 11339276802 ps |
CPU time | 164.01 seconds |
Started | Jun 27 06:48:55 PM PDT 24 |
Finished | Jun 27 06:51:43 PM PDT 24 |
Peak memory | 211108 kb |
Host | smart-4d0ee230-7cca-44d4-8816-963cb964130d |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377340245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_mem_partial_access.1377340245 |
Directory | /workspace/1.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_mem_walk.1265479233 |
Short name | T717 |
Test name | |
Test status | |
Simulation time | 2634481273 ps |
CPU time | 160.89 seconds |
Started | Jun 27 06:49:10 PM PDT 24 |
Finished | Jun 27 06:51:52 PM PDT 24 |
Peak memory | 211032 kb |
Host | smart-40d5ad49-7313-48a6-be1a-43c8e0a77e65 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265479233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl _mem_walk.1265479233 |
Directory | /workspace/1.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_multiple_keys.3889069376 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 23635739121 ps |
CPU time | 1232.31 seconds |
Started | Jun 27 06:49:00 PM PDT 24 |
Finished | Jun 27 07:09:37 PM PDT 24 |
Peak memory | 375648 kb |
Host | smart-08e164da-359d-4cc6-9ec1-fa24ca82423e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889069376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip le_keys.3889069376 |
Directory | /workspace/1.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_partial_access.642483212 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 3210383320 ps |
CPU time | 12.1 seconds |
Started | Jun 27 06:49:10 PM PDT 24 |
Finished | Jun 27 06:49:23 PM PDT 24 |
Peak memory | 232640 kb |
Host | smart-576618eb-a518-4c3e-ab7f-f2748a25e80a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642483212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sr am_ctrl_partial_access.642483212 |
Directory | /workspace/1.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_ram_cfg.3549163489 |
Short name | T910 |
Test name | |
Test status | |
Simulation time | 708782298 ps |
CPU time | 3.74 seconds |
Started | Jun 27 06:49:10 PM PDT 24 |
Finished | Jun 27 06:49:15 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-e478fd6e-e561-48be-8c54-4bf03666dd4f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549163489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.3549163489 |
Directory | /workspace/1.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_regwen.731341958 |
Short name | T716 |
Test name | |
Test status | |
Simulation time | 13736738023 ps |
CPU time | 851.02 seconds |
Started | Jun 27 06:48:59 PM PDT 24 |
Finished | Jun 27 07:03:15 PM PDT 24 |
Peak memory | 380768 kb |
Host | smart-b99a31fa-7fa6-478a-b79b-a23f739afebb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731341958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.731341958 |
Directory | /workspace/1.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_sec_cm.2921099941 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 464366568 ps |
CPU time | 2.11 seconds |
Started | Jun 27 06:49:10 PM PDT 24 |
Finished | Jun 27 06:49:14 PM PDT 24 |
Peak memory | 222304 kb |
Host | smart-07225610-ef1b-4e91-a45a-ca31b77b17bd |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921099941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.2921099941 |
Directory | /workspace/1.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_smoke.1923138197 |
Short name | T509 |
Test name | |
Test status | |
Simulation time | 921282989 ps |
CPU time | 17.85 seconds |
Started | Jun 27 06:48:57 PM PDT 24 |
Finished | Jun 27 06:49:19 PM PDT 24 |
Peak memory | 247724 kb |
Host | smart-c04ab57d-e5b6-4b00-80c0-dfb6125e58c7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923138197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.1923138197 |
Directory | /workspace/1.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_all.218919854 |
Short name | T649 |
Test name | |
Test status | |
Simulation time | 1870307782471 ps |
CPU time | 9938.97 seconds |
Started | Jun 27 06:48:59 PM PDT 24 |
Finished | Jun 27 09:34:44 PM PDT 24 |
Peak memory | 376656 kb |
Host | smart-f3cd9639-0042-452b-912c-71093a57d779 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218919854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.sram_ctrl_stress_all.218919854 |
Directory | /workspace/1.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1288803424 |
Short name | T878 |
Test name | |
Test status | |
Simulation time | 1522628190 ps |
CPU time | 58.74 seconds |
Started | Jun 27 06:48:56 PM PDT 24 |
Finished | Jun 27 06:50:00 PM PDT 24 |
Peak memory | 252588 kb |
Host | smart-05e6cc0f-760c-40e3-90f8-f28f931199af |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1288803424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.1288803424 |
Directory | /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_pipeline.1918442077 |
Short name | T484 |
Test name | |
Test status | |
Simulation time | 4404114754 ps |
CPU time | 332.22 seconds |
Started | Jun 27 06:48:59 PM PDT 24 |
Finished | Jun 27 06:54:36 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-1902b72c-0e41-4fb8-bca5-c0c05c034668 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918442077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_stress_pipeline.1918442077 |
Directory | /workspace/1.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3495435122 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 750208081 ps |
CPU time | 22.42 seconds |
Started | Jun 27 06:48:58 PM PDT 24 |
Finished | Jun 27 06:49:25 PM PDT 24 |
Peak memory | 261016 kb |
Host | smart-0542b1a2-967e-4942-9040-2f684d152c9a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495435122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.sram_ctrl_throughput_w_partial_write.3495435122 |
Directory | /workspace/1.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_access_during_key_req.812803053 |
Short name | T708 |
Test name | |
Test status | |
Simulation time | 55543150845 ps |
CPU time | 430.43 seconds |
Started | Jun 27 06:49:40 PM PDT 24 |
Finished | Jun 27 06:56:55 PM PDT 24 |
Peak memory | 380716 kb |
Host | smart-a31524d0-8ee0-43c6-a004-1c9aaafa3ee6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812803053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 10.sram_ctrl_access_during_key_req.812803053 |
Directory | /workspace/10.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_bijection.3385238698 |
Short name | T567 |
Test name | |
Test status | |
Simulation time | 27855925837 ps |
CPU time | 1896.79 seconds |
Started | Jun 27 06:49:43 PM PDT 24 |
Finished | Jun 27 07:21:24 PM PDT 24 |
Peak memory | 203620 kb |
Host | smart-5c9422c5-ec45-45d4-aff8-68706927d598 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385238698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection .3385238698 |
Directory | /workspace/10.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_executable.1117083712 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 24660900406 ps |
CPU time | 1136.38 seconds |
Started | Jun 27 06:49:41 PM PDT 24 |
Finished | Jun 27 07:08:41 PM PDT 24 |
Peak memory | 378756 kb |
Host | smart-7986e931-9d7f-4828-84dc-56facf5c46c4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117083712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executab le.1117083712 |
Directory | /workspace/10.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_lc_escalation.442089880 |
Short name | T490 |
Test name | |
Test status | |
Simulation time | 33189847801 ps |
CPU time | 54.88 seconds |
Started | Jun 27 06:49:37 PM PDT 24 |
Finished | Jun 27 06:50:34 PM PDT 24 |
Peak memory | 211108 kb |
Host | smart-edc4e036-76d8-4462-9801-5394df8eb070 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442089880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_esc alation.442089880 |
Directory | /workspace/10.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_max_throughput.2191797421 |
Short name | T575 |
Test name | |
Test status | |
Simulation time | 795140194 ps |
CPU time | 163.95 seconds |
Started | Jun 27 06:49:37 PM PDT 24 |
Finished | Jun 27 06:52:23 PM PDT 24 |
Peak memory | 361216 kb |
Host | smart-72aa1dae-fe03-470d-8866-f1ef5fcc6804 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191797421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 10.sram_ctrl_max_throughput.2191797421 |
Directory | /workspace/10.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_mem_partial_access.1568212708 |
Short name | T833 |
Test name | |
Test status | |
Simulation time | 9058958794 ps |
CPU time | 153.71 seconds |
Started | Jun 27 06:49:45 PM PDT 24 |
Finished | Jun 27 06:52:23 PM PDT 24 |
Peak memory | 210964 kb |
Host | smart-95834eac-22db-4fce-803f-1d8f2cae7cf3 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568212708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_mem_partial_access.1568212708 |
Directory | /workspace/10.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_mem_walk.1888917387 |
Short name | T493 |
Test name | |
Test status | |
Simulation time | 30032396308 ps |
CPU time | 354.93 seconds |
Started | Jun 27 06:49:37 PM PDT 24 |
Finished | Jun 27 06:55:34 PM PDT 24 |
Peak memory | 210952 kb |
Host | smart-968527c1-98c3-4bd3-a92f-ff6da714c390 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888917387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr l_mem_walk.1888917387 |
Directory | /workspace/10.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_multiple_keys.2104856557 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 225401686867 ps |
CPU time | 989.86 seconds |
Started | Jun 27 06:49:41 PM PDT 24 |
Finished | Jun 27 07:06:15 PM PDT 24 |
Peak memory | 374804 kb |
Host | smart-d07e472e-ff4f-4d09-869b-25b56e31ecbf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104856557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi ple_keys.2104856557 |
Directory | /workspace/10.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_partial_access.4074792817 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 2510747583 ps |
CPU time | 18.92 seconds |
Started | Jun 27 06:49:42 PM PDT 24 |
Finished | Jun 27 06:50:05 PM PDT 24 |
Peak memory | 202828 kb |
Host | smart-49b8e8a5-d99a-440d-9d3b-f79351645a87 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074792817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10. sram_ctrl_partial_access.4074792817 |
Directory | /workspace/10.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1831378100 |
Short name | T806 |
Test name | |
Test status | |
Simulation time | 33170517098 ps |
CPU time | 352.8 seconds |
Started | Jun 27 06:49:47 PM PDT 24 |
Finished | Jun 27 06:55:44 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-dbc3c773-e9f7-4161-abf9-8a98ad655a35 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831378100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 10.sram_ctrl_partial_access_b2b.1831378100 |
Directory | /workspace/10.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_ram_cfg.4090108851 |
Short name | T830 |
Test name | |
Test status | |
Simulation time | 699479851 ps |
CPU time | 3.15 seconds |
Started | Jun 27 06:49:41 PM PDT 24 |
Finished | Jun 27 06:49:48 PM PDT 24 |
Peak memory | 203036 kb |
Host | smart-e150bb60-8834-46fd-852c-3daf9afdc882 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090108851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.4090108851 |
Directory | /workspace/10.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_regwen.93819470 |
Short name | T513 |
Test name | |
Test status | |
Simulation time | 3829426290 ps |
CPU time | 1218.55 seconds |
Started | Jun 27 06:49:40 PM PDT 24 |
Finished | Jun 27 07:10:03 PM PDT 24 |
Peak memory | 372644 kb |
Host | smart-3686c9ea-9b13-41ae-b746-752652e502c5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93819470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.93819470 |
Directory | /workspace/10.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_smoke.121840150 |
Short name | T704 |
Test name | |
Test status | |
Simulation time | 714467138 ps |
CPU time | 11.22 seconds |
Started | Jun 27 06:49:41 PM PDT 24 |
Finished | Jun 27 06:49:56 PM PDT 24 |
Peak memory | 232356 kb |
Host | smart-6175ce43-39d5-46f3-abcf-7e1af4c1fa1f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121840150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.121840150 |
Directory | /workspace/10.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_all.1463052756 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 416932762820 ps |
CPU time | 2897.94 seconds |
Started | Jun 27 06:49:39 PM PDT 24 |
Finished | Jun 27 07:38:01 PM PDT 24 |
Peak memory | 388128 kb |
Host | smart-c13ecc16-afe6-47f1-a8a9-6e239caa4557 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463052756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 10.sram_ctrl_stress_all.1463052756 |
Directory | /workspace/10.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.4281527274 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 4280270912 ps |
CPU time | 13.41 seconds |
Started | Jun 27 06:49:45 PM PDT 24 |
Finished | Jun 27 06:50:03 PM PDT 24 |
Peak memory | 211096 kb |
Host | smart-1d0a1f17-04ce-48a4-9b9e-40b0f18947e3 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4281527274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.4281527274 |
Directory | /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_pipeline.2774825026 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 16139459297 ps |
CPU time | 313.5 seconds |
Started | Jun 27 06:49:41 PM PDT 24 |
Finished | Jun 27 06:54:59 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-573948ca-9eaf-4d66-91dd-488ae1704628 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774825026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_stress_pipeline.2774825026 |
Directory | /workspace/10.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.69499056 |
Short name | T839 |
Test name | |
Test status | |
Simulation time | 5863931886 ps |
CPU time | 76.74 seconds |
Started | Jun 27 06:49:39 PM PDT 24 |
Finished | Jun 27 06:50:59 PM PDT 24 |
Peak memory | 341948 kb |
Host | smart-fa0cf963-50f9-4d0f-acac-1091dbbaae34 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69499056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 10.sram_ctrl_throughput_w_partial_write.69499056 |
Directory | /workspace/10.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_access_during_key_req.1965241585 |
Short name | T842 |
Test name | |
Test status | |
Simulation time | 48241041080 ps |
CPU time | 1190.56 seconds |
Started | Jun 27 06:49:42 PM PDT 24 |
Finished | Jun 27 07:09:37 PM PDT 24 |
Peak memory | 379788 kb |
Host | smart-934c71f9-13fd-41ae-977e-48689675830e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965241585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_access_during_key_req.1965241585 |
Directory | /workspace/11.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_alert_test.3557739824 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 26745270 ps |
CPU time | 0.67 seconds |
Started | Jun 27 06:49:40 PM PDT 24 |
Finished | Jun 27 06:49:44 PM PDT 24 |
Peak memory | 202372 kb |
Host | smart-03eca28b-4a09-400a-a471-3ab65c0bab4d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557739824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.3557739824 |
Directory | /workspace/11.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_bijection.2183365848 |
Short name | T769 |
Test name | |
Test status | |
Simulation time | 288228071025 ps |
CPU time | 1690.97 seconds |
Started | Jun 27 06:49:43 PM PDT 24 |
Finished | Jun 27 07:17:58 PM PDT 24 |
Peak memory | 203360 kb |
Host | smart-3ad4c308-cfb3-40d3-ba51-6f1022c05d2a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183365848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection .2183365848 |
Directory | /workspace/11.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_executable.4197292199 |
Short name | T540 |
Test name | |
Test status | |
Simulation time | 4974328809 ps |
CPU time | 78.33 seconds |
Started | Jun 27 06:49:43 PM PDT 24 |
Finished | Jun 27 06:51:05 PM PDT 24 |
Peak memory | 275236 kb |
Host | smart-e78b8d9a-a1e4-444c-8b70-ac2e7f3326be |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197292199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executab le.4197292199 |
Directory | /workspace/11.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_lc_escalation.1781062766 |
Short name | T831 |
Test name | |
Test status | |
Simulation time | 31668902411 ps |
CPU time | 71.5 seconds |
Started | Jun 27 06:49:41 PM PDT 24 |
Finished | Jun 27 06:50:57 PM PDT 24 |
Peak memory | 211128 kb |
Host | smart-9946ac73-6d40-4af8-a501-388a32676c3e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781062766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_es calation.1781062766 |
Directory | /workspace/11.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_max_throughput.345914043 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 819038677 ps |
CPU time | 65.03 seconds |
Started | Jun 27 06:49:46 PM PDT 24 |
Finished | Jun 27 06:50:56 PM PDT 24 |
Peak memory | 342792 kb |
Host | smart-34f59aaa-c2a4-4ced-ab4d-427fb78156b6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345914043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 11.sram_ctrl_max_throughput.345914043 |
Directory | /workspace/11.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_mem_partial_access.2591146365 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 8813702359 ps |
CPU time | 165.81 seconds |
Started | Jun 27 06:49:42 PM PDT 24 |
Finished | Jun 27 06:52:32 PM PDT 24 |
Peak memory | 211084 kb |
Host | smart-8a549519-4b99-4ac7-ad52-54238f8058b8 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591146365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_mem_partial_access.2591146365 |
Directory | /workspace/11.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_mem_walk.2399322745 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 4033569009 ps |
CPU time | 136.64 seconds |
Started | Jun 27 06:49:38 PM PDT 24 |
Finished | Jun 27 06:51:58 PM PDT 24 |
Peak memory | 211024 kb |
Host | smart-77c1f424-eb11-4c70-b371-eb198fe711dc |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399322745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctr l_mem_walk.2399322745 |
Directory | /workspace/11.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_multiple_keys.1864355515 |
Short name | T889 |
Test name | |
Test status | |
Simulation time | 53847927126 ps |
CPU time | 1418.7 seconds |
Started | Jun 27 06:49:40 PM PDT 24 |
Finished | Jun 27 07:13:22 PM PDT 24 |
Peak memory | 372956 kb |
Host | smart-4521c57d-3f83-4932-b831-526d0041992a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864355515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi ple_keys.1864355515 |
Directory | /workspace/11.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_partial_access.3937299322 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 679014178 ps |
CPU time | 5.92 seconds |
Started | Jun 27 06:49:44 PM PDT 24 |
Finished | Jun 27 06:49:55 PM PDT 24 |
Peak memory | 202612 kb |
Host | smart-506035c3-1a83-4194-86e8-168a796b0860 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937299322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11. sram_ctrl_partial_access.3937299322 |
Directory | /workspace/11.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3068134196 |
Short name | T495 |
Test name | |
Test status | |
Simulation time | 138834338776 ps |
CPU time | 559.12 seconds |
Started | Jun 27 06:49:38 PM PDT 24 |
Finished | Jun 27 06:58:59 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-93427072-9726-434f-b085-ed5d01baa4e5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068134196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 11.sram_ctrl_partial_access_b2b.3068134196 |
Directory | /workspace/11.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_ram_cfg.3857392336 |
Short name | T726 |
Test name | |
Test status | |
Simulation time | 354470473 ps |
CPU time | 3.15 seconds |
Started | Jun 27 06:49:39 PM PDT 24 |
Finished | Jun 27 06:49:45 PM PDT 24 |
Peak memory | 202828 kb |
Host | smart-48b0560e-6f45-45bd-81e4-52bc82d98cce |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857392336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.3857392336 |
Directory | /workspace/11.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_regwen.2981340572 |
Short name | T519 |
Test name | |
Test status | |
Simulation time | 84692359659 ps |
CPU time | 833.46 seconds |
Started | Jun 27 06:49:41 PM PDT 24 |
Finished | Jun 27 07:03:38 PM PDT 24 |
Peak memory | 365460 kb |
Host | smart-bc467ff0-8221-4de8-8748-f61f63e60c06 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981340572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.2981340572 |
Directory | /workspace/11.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_smoke.1091267914 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 1481900091 ps |
CPU time | 4.75 seconds |
Started | Jun 27 06:49:39 PM PDT 24 |
Finished | Jun 27 06:49:48 PM PDT 24 |
Peak memory | 202780 kb |
Host | smart-50c51b28-b66c-4669-846e-697a1fec351d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091267914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.1091267914 |
Directory | /workspace/11.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_all.3508065377 |
Short name | T866 |
Test name | |
Test status | |
Simulation time | 76865850474 ps |
CPU time | 1621.66 seconds |
Started | Jun 27 06:49:43 PM PDT 24 |
Finished | Jun 27 07:16:48 PM PDT 24 |
Peak memory | 387596 kb |
Host | smart-233ad522-18bc-4da9-a3fe-01ffee00699d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508065377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 11.sram_ctrl_stress_all.3508065377 |
Directory | /workspace/11.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.90633968 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 2660633584 ps |
CPU time | 45.85 seconds |
Started | Jun 27 06:49:46 PM PDT 24 |
Finished | Jun 27 06:50:36 PM PDT 24 |
Peak memory | 218440 kb |
Host | smart-91e1ffdb-b7b6-48a6-96b4-441146b19a76 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=90633968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.90633968 |
Directory | /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_pipeline.93736524 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 46173504242 ps |
CPU time | 394.04 seconds |
Started | Jun 27 06:49:46 PM PDT 24 |
Finished | Jun 27 06:56:24 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-04118b43-80eb-4c76-b62d-d8da7dd3cde5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93736524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11. sram_ctrl_stress_pipeline.93736524 |
Directory | /workspace/11.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1013908768 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 3047186086 ps |
CPU time | 115.16 seconds |
Started | Jun 27 06:49:44 PM PDT 24 |
Finished | Jun 27 06:51:44 PM PDT 24 |
Peak memory | 339480 kb |
Host | smart-dca7a5d6-b09b-4094-abbc-7fa5c817f76f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013908768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.1013908768 |
Directory | /workspace/11.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_access_during_key_req.1458895305 |
Short name | T914 |
Test name | |
Test status | |
Simulation time | 8629060693 ps |
CPU time | 669.52 seconds |
Started | Jun 27 06:49:47 PM PDT 24 |
Finished | Jun 27 07:01:01 PM PDT 24 |
Peak memory | 377700 kb |
Host | smart-928c8343-8a91-4866-8e95-378c2c564a4e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458895305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_access_during_key_req.1458895305 |
Directory | /workspace/12.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_alert_test.3172705012 |
Short name | T779 |
Test name | |
Test status | |
Simulation time | 26133827 ps |
CPU time | 0.64 seconds |
Started | Jun 27 06:49:52 PM PDT 24 |
Finished | Jun 27 06:49:55 PM PDT 24 |
Peak memory | 202436 kb |
Host | smart-6e92b6e3-447d-47b8-add9-f8595bc3efb6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172705012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.3172705012 |
Directory | /workspace/12.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_bijection.233032998 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 20010647750 ps |
CPU time | 1424.38 seconds |
Started | Jun 27 06:49:42 PM PDT 24 |
Finished | Jun 27 07:13:31 PM PDT 24 |
Peak memory | 203756 kb |
Host | smart-a17a4b22-16eb-4785-ab12-b34a00cb845e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233032998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection. 233032998 |
Directory | /workspace/12.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_executable.1074453562 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 11837017925 ps |
CPU time | 345.07 seconds |
Started | Jun 27 06:49:48 PM PDT 24 |
Finished | Jun 27 06:55:37 PM PDT 24 |
Peak memory | 373168 kb |
Host | smart-28632f39-a3ba-4a8e-98c0-4a3dc151069a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074453562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executab le.1074453562 |
Directory | /workspace/12.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_lc_escalation.281092637 |
Short name | T933 |
Test name | |
Test status | |
Simulation time | 14042625408 ps |
CPU time | 48.95 seconds |
Started | Jun 27 06:49:46 PM PDT 24 |
Finished | Jun 27 06:50:40 PM PDT 24 |
Peak memory | 211088 kb |
Host | smart-6320b48b-686b-468e-99ff-9750c65a8b6f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281092637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_esc alation.281092637 |
Directory | /workspace/12.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_max_throughput.3513900246 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 2938056738 ps |
CPU time | 158.31 seconds |
Started | Jun 27 06:49:44 PM PDT 24 |
Finished | Jun 27 06:52:27 PM PDT 24 |
Peak memory | 369352 kb |
Host | smart-448913d9-1004-4c37-9952-2c1d97b52650 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513900246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 12.sram_ctrl_max_throughput.3513900246 |
Directory | /workspace/12.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_mem_partial_access.3083401659 |
Short name | T595 |
Test name | |
Test status | |
Simulation time | 3253113574 ps |
CPU time | 142.83 seconds |
Started | Jun 27 06:49:43 PM PDT 24 |
Finished | Jun 27 06:52:10 PM PDT 24 |
Peak memory | 210996 kb |
Host | smart-933214a3-f5e5-4003-ba9e-cf5362d5b0b2 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083401659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_mem_partial_access.3083401659 |
Directory | /workspace/12.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_mem_walk.1918972492 |
Short name | T895 |
Test name | |
Test status | |
Simulation time | 8221054786 ps |
CPU time | 129 seconds |
Started | Jun 27 06:49:49 PM PDT 24 |
Finished | Jun 27 06:52:02 PM PDT 24 |
Peak memory | 211028 kb |
Host | smart-5276c362-610e-451c-9533-d18f7d6ac027 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918972492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr l_mem_walk.1918972492 |
Directory | /workspace/12.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_multiple_keys.1929017737 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 51303931828 ps |
CPU time | 1555.39 seconds |
Started | Jun 27 06:49:41 PM PDT 24 |
Finished | Jun 27 07:15:40 PM PDT 24 |
Peak memory | 380884 kb |
Host | smart-629b3f99-4502-4ed3-a001-01d14c86f4be |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929017737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi ple_keys.1929017737 |
Directory | /workspace/12.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_partial_access.4063685052 |
Short name | T633 |
Test name | |
Test status | |
Simulation time | 901023416 ps |
CPU time | 19.06 seconds |
Started | Jun 27 06:49:44 PM PDT 24 |
Finished | Jun 27 06:50:08 PM PDT 24 |
Peak memory | 202632 kb |
Host | smart-f5f75390-98a5-44b7-b1be-0ace0b2a55ac |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063685052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12. sram_ctrl_partial_access.4063685052 |
Directory | /workspace/12.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.4004811997 |
Short name | T529 |
Test name | |
Test status | |
Simulation time | 6488729303 ps |
CPU time | 392.04 seconds |
Started | Jun 27 06:49:45 PM PDT 24 |
Finished | Jun 27 06:56:22 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-f8daa827-ac02-4760-aaf1-022e71964484 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004811997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 12.sram_ctrl_partial_access_b2b.4004811997 |
Directory | /workspace/12.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_ram_cfg.1961396116 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 349224173 ps |
CPU time | 3.15 seconds |
Started | Jun 27 06:49:52 PM PDT 24 |
Finished | Jun 27 06:49:58 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-fd70876f-a9b5-4815-8a60-d869bd476460 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961396116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.1961396116 |
Directory | /workspace/12.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_regwen.1274827454 |
Short name | T631 |
Test name | |
Test status | |
Simulation time | 5506979144 ps |
CPU time | 502.8 seconds |
Started | Jun 27 06:49:50 PM PDT 24 |
Finished | Jun 27 06:58:16 PM PDT 24 |
Peak memory | 364404 kb |
Host | smart-17698cc1-5297-4565-963f-cc5fa0e652d2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274827454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.1274827454 |
Directory | /workspace/12.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_smoke.4066799610 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 4535792773 ps |
CPU time | 21.56 seconds |
Started | Jun 27 06:49:47 PM PDT 24 |
Finished | Jun 27 06:50:13 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-8c4bb997-ca94-4f6b-97bb-baa844fd4cb6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066799610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.4066799610 |
Directory | /workspace/12.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_pipeline.586518350 |
Short name | T753 |
Test name | |
Test status | |
Simulation time | 4872162076 ps |
CPU time | 325.15 seconds |
Started | Jun 27 06:49:42 PM PDT 24 |
Finished | Jun 27 06:55:11 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-37908daa-9123-48cb-88f4-57cfa78ddc3a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586518350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12 .sram_ctrl_stress_pipeline.586518350 |
Directory | /workspace/12.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1847966837 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 2972234965 ps |
CPU time | 8.59 seconds |
Started | Jun 27 06:49:43 PM PDT 24 |
Finished | Jun 27 06:49:57 PM PDT 24 |
Peak memory | 220600 kb |
Host | smart-e2ef2cfc-5bc6-4a06-9ca2-b6fe9fac3b5d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847966837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.1847966837 |
Directory | /workspace/12.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_access_during_key_req.1186427389 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 57240151759 ps |
CPU time | 609.31 seconds |
Started | Jun 27 06:49:51 PM PDT 24 |
Finished | Jun 27 07:00:03 PM PDT 24 |
Peak memory | 374656 kb |
Host | smart-405648ca-6739-4422-a785-e84c34d013f5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186427389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_access_during_key_req.1186427389 |
Directory | /workspace/13.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_alert_test.2787878270 |
Short name | T801 |
Test name | |
Test status | |
Simulation time | 11714467 ps |
CPU time | 0.65 seconds |
Started | Jun 27 06:50:00 PM PDT 24 |
Finished | Jun 27 06:50:04 PM PDT 24 |
Peak memory | 202440 kb |
Host | smart-52064a2f-006e-4255-baac-2e1ac7f44bfd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787878270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.2787878270 |
Directory | /workspace/13.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_bijection.4072540930 |
Short name | T596 |
Test name | |
Test status | |
Simulation time | 144022266308 ps |
CPU time | 1181.95 seconds |
Started | Jun 27 06:49:50 PM PDT 24 |
Finished | Jun 27 07:09:35 PM PDT 24 |
Peak memory | 203644 kb |
Host | smart-dfca9cf9-45d2-4cc7-8c39-940c71e9df15 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072540930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection .4072540930 |
Directory | /workspace/13.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_executable.1174086077 |
Short name | T563 |
Test name | |
Test status | |
Simulation time | 3263615158 ps |
CPU time | 49.45 seconds |
Started | Jun 27 06:49:41 PM PDT 24 |
Finished | Jun 27 06:50:34 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-7f4642b1-8500-4b2f-b592-343269862d69 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174086077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executab le.1174086077 |
Directory | /workspace/13.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_lc_escalation.320038626 |
Short name | T499 |
Test name | |
Test status | |
Simulation time | 7283033393 ps |
CPU time | 45.84 seconds |
Started | Jun 27 06:49:40 PM PDT 24 |
Finished | Jun 27 06:50:30 PM PDT 24 |
Peak memory | 211104 kb |
Host | smart-6d4dea98-399f-4fcd-9b68-781f2d6c763c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320038626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_esc alation.320038626 |
Directory | /workspace/13.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_max_throughput.559412322 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 3079774688 ps |
CPU time | 86.51 seconds |
Started | Jun 27 06:49:43 PM PDT 24 |
Finished | Jun 27 06:51:14 PM PDT 24 |
Peak memory | 323436 kb |
Host | smart-1440df30-a393-4f96-95e3-6a0b023d7fe9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559412322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 13.sram_ctrl_max_throughput.559412322 |
Directory | /workspace/13.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_mem_partial_access.2432545131 |
Short name | T558 |
Test name | |
Test status | |
Simulation time | 2842838400 ps |
CPU time | 71.8 seconds |
Started | Jun 27 06:49:55 PM PDT 24 |
Finished | Jun 27 06:51:10 PM PDT 24 |
Peak memory | 219196 kb |
Host | smart-1ce6d93d-cdc3-49e7-8056-7599ff90d1ea |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432545131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_mem_partial_access.2432545131 |
Directory | /workspace/13.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_mem_walk.2915795014 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 57476488624 ps |
CPU time | 377.75 seconds |
Started | Jun 27 06:49:50 PM PDT 24 |
Finished | Jun 27 06:56:11 PM PDT 24 |
Peak memory | 211060 kb |
Host | smart-6452b5c1-bb39-4973-8c0d-bb1106935659 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915795014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctr l_mem_walk.2915795014 |
Directory | /workspace/13.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_multiple_keys.1740532136 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 43591597512 ps |
CPU time | 1479.57 seconds |
Started | Jun 27 06:49:42 PM PDT 24 |
Finished | Jun 27 07:14:26 PM PDT 24 |
Peak memory | 378836 kb |
Host | smart-e3ea81f1-5209-4776-a4f7-fd67f23b4afd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740532136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multi ple_keys.1740532136 |
Directory | /workspace/13.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_partial_access.2575384557 |
Short name | T923 |
Test name | |
Test status | |
Simulation time | 1319772217 ps |
CPU time | 10.48 seconds |
Started | Jun 27 06:49:42 PM PDT 24 |
Finished | Jun 27 06:49:57 PM PDT 24 |
Peak memory | 202772 kb |
Host | smart-8518ea7b-5a09-4f0a-95e5-5a0ad79cc89c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575384557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13. sram_ctrl_partial_access.2575384557 |
Directory | /workspace/13.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.683609504 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 9629695971 ps |
CPU time | 265.47 seconds |
Started | Jun 27 06:49:43 PM PDT 24 |
Finished | Jun 27 06:54:13 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-2c48d78b-0853-40af-9ffd-fcd5a14c25d7 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683609504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 13.sram_ctrl_partial_access_b2b.683609504 |
Directory | /workspace/13.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_regwen.3998344342 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 2588686127 ps |
CPU time | 626.76 seconds |
Started | Jun 27 06:49:48 PM PDT 24 |
Finished | Jun 27 07:00:19 PM PDT 24 |
Peak memory | 374484 kb |
Host | smart-8defd487-c97f-4e70-868b-4a0ef9c7121d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998344342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.3998344342 |
Directory | /workspace/13.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_smoke.2735502937 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 822079052 ps |
CPU time | 10.98 seconds |
Started | Jun 27 06:49:53 PM PDT 24 |
Finished | Jun 27 06:50:06 PM PDT 24 |
Peak memory | 229160 kb |
Host | smart-7680c716-a112-4154-ae63-2268841a5dd3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735502937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.2735502937 |
Directory | /workspace/13.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_all.3763216373 |
Short name | T861 |
Test name | |
Test status | |
Simulation time | 34909703696 ps |
CPU time | 3180.15 seconds |
Started | Jun 27 06:49:49 PM PDT 24 |
Finished | Jun 27 07:42:53 PM PDT 24 |
Peak memory | 375740 kb |
Host | smart-4d782a08-37bd-4d65-b78c-ab9ad36c73aa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763216373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 13.sram_ctrl_stress_all.3763216373 |
Directory | /workspace/13.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1884022073 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 1266482759 ps |
CPU time | 20.47 seconds |
Started | Jun 27 06:49:53 PM PDT 24 |
Finished | Jun 27 06:50:16 PM PDT 24 |
Peak memory | 219208 kb |
Host | smart-5741aa7b-666e-409b-811c-148405e49a61 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1884022073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.1884022073 |
Directory | /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_pipeline.2104681536 |
Short name | T690 |
Test name | |
Test status | |
Simulation time | 24488251088 ps |
CPU time | 152.04 seconds |
Started | Jun 27 06:49:49 PM PDT 24 |
Finished | Jun 27 06:52:25 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-45d03225-d958-4d36-bd5e-2332f59ceb1c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104681536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_stress_pipeline.2104681536 |
Directory | /workspace/13.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3246055947 |
Short name | T764 |
Test name | |
Test status | |
Simulation time | 5368897791 ps |
CPU time | 16.53 seconds |
Started | Jun 27 06:49:43 PM PDT 24 |
Finished | Jun 27 06:50:04 PM PDT 24 |
Peak memory | 251808 kb |
Host | smart-d1b620de-f1a0-48cb-899a-03b31b92ed4f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246055947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.3246055947 |
Directory | /workspace/13.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_access_during_key_req.958751375 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 75998854662 ps |
CPU time | 1800.03 seconds |
Started | Jun 27 06:49:49 PM PDT 24 |
Finished | Jun 27 07:19:52 PM PDT 24 |
Peak memory | 379740 kb |
Host | smart-b3a05420-942d-4c3c-b4b4-f88d4ee8d6c7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958751375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 14.sram_ctrl_access_during_key_req.958751375 |
Directory | /workspace/14.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_alert_test.3315171215 |
Short name | T855 |
Test name | |
Test status | |
Simulation time | 25558849 ps |
CPU time | 0.68 seconds |
Started | Jun 27 06:50:01 PM PDT 24 |
Finished | Jun 27 06:50:06 PM PDT 24 |
Peak memory | 202388 kb |
Host | smart-ce764169-e2d5-48ab-a224-d02a8ecacbfd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315171215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.3315171215 |
Directory | /workspace/14.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_bijection.1128078954 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 181414974068 ps |
CPU time | 1216.96 seconds |
Started | Jun 27 06:49:50 PM PDT 24 |
Finished | Jun 27 07:10:10 PM PDT 24 |
Peak memory | 203496 kb |
Host | smart-82b49863-5096-4e1f-be15-de723d3ebc9c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128078954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection .1128078954 |
Directory | /workspace/14.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_executable.2578516987 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 3798625059 ps |
CPU time | 463.81 seconds |
Started | Jun 27 06:49:54 PM PDT 24 |
Finished | Jun 27 06:57:40 PM PDT 24 |
Peak memory | 376672 kb |
Host | smart-904c18c5-ad8e-467e-8e34-aa4671ce74c6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578516987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executab le.2578516987 |
Directory | /workspace/14.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_lc_escalation.1396195903 |
Short name | T645 |
Test name | |
Test status | |
Simulation time | 31336359263 ps |
CPU time | 101.39 seconds |
Started | Jun 27 06:50:02 PM PDT 24 |
Finished | Jun 27 06:51:47 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-0309eea8-c58d-4bb7-89f3-9f95f0f269e5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396195903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es calation.1396195903 |
Directory | /workspace/14.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_max_throughput.3115111018 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 676798703 ps |
CPU time | 7.57 seconds |
Started | Jun 27 06:49:48 PM PDT 24 |
Finished | Jun 27 06:50:00 PM PDT 24 |
Peak memory | 219084 kb |
Host | smart-98844879-8753-4b6c-91ea-03dc96506cc7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115111018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 14.sram_ctrl_max_throughput.3115111018 |
Directory | /workspace/14.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_mem_partial_access.2286446064 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 23158608001 ps |
CPU time | 184.81 seconds |
Started | Jun 27 06:50:00 PM PDT 24 |
Finished | Jun 27 06:53:09 PM PDT 24 |
Peak memory | 219196 kb |
Host | smart-461ad1b0-6c94-4290-bf16-6ef5565fe51c |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286446064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_mem_partial_access.2286446064 |
Directory | /workspace/14.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_mem_walk.4149992179 |
Short name | T887 |
Test name | |
Test status | |
Simulation time | 21871659376 ps |
CPU time | 303.03 seconds |
Started | Jun 27 06:50:02 PM PDT 24 |
Finished | Jun 27 06:55:09 PM PDT 24 |
Peak memory | 210992 kb |
Host | smart-a9183ecf-6db7-4118-b908-48b0ca21fe49 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149992179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr l_mem_walk.4149992179 |
Directory | /workspace/14.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_multiple_keys.3731762895 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 3923569377 ps |
CPU time | 384.29 seconds |
Started | Jun 27 06:49:56 PM PDT 24 |
Finished | Jun 27 06:56:22 PM PDT 24 |
Peak memory | 379232 kb |
Host | smart-c75b8a4c-995a-4691-b9c4-635523f92f12 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731762895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi ple_keys.3731762895 |
Directory | /workspace/14.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_partial_access.907893744 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 887654713 ps |
CPU time | 166.76 seconds |
Started | Jun 27 06:49:48 PM PDT 24 |
Finished | Jun 27 06:52:39 PM PDT 24 |
Peak memory | 366328 kb |
Host | smart-09b4fb82-3592-419e-8cc4-8ae6e1ae497f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907893744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.s ram_ctrl_partial_access.907893744 |
Directory | /workspace/14.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3988128640 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 73854556988 ps |
CPU time | 578.85 seconds |
Started | Jun 27 06:49:51 PM PDT 24 |
Finished | Jun 27 06:59:33 PM PDT 24 |
Peak memory | 203068 kb |
Host | smart-684ce200-bbac-40f9-b74d-27efef85b0d3 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988128640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 14.sram_ctrl_partial_access_b2b.3988128640 |
Directory | /workspace/14.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_ram_cfg.371094401 |
Short name | T937 |
Test name | |
Test status | |
Simulation time | 1355126951 ps |
CPU time | 3.14 seconds |
Started | Jun 27 06:49:56 PM PDT 24 |
Finished | Jun 27 06:50:01 PM PDT 24 |
Peak memory | 202852 kb |
Host | smart-636b9320-cb79-4b0d-8de7-582632d9ea22 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371094401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.371094401 |
Directory | /workspace/14.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_regwen.3555359583 |
Short name | T907 |
Test name | |
Test status | |
Simulation time | 27170088242 ps |
CPU time | 340.4 seconds |
Started | Jun 27 06:49:51 PM PDT 24 |
Finished | Jun 27 06:55:34 PM PDT 24 |
Peak memory | 372636 kb |
Host | smart-91a78a98-88e2-4638-b6b3-054ae355f1d6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555359583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.3555359583 |
Directory | /workspace/14.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_smoke.4172258591 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 2490386926 ps |
CPU time | 107.05 seconds |
Started | Jun 27 06:49:59 PM PDT 24 |
Finished | Jun 27 06:51:50 PM PDT 24 |
Peak memory | 349956 kb |
Host | smart-80140baf-eec2-46e9-b33d-f3f5187ea280 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172258591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.4172258591 |
Directory | /workspace/14.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_all.456539235 |
Short name | T930 |
Test name | |
Test status | |
Simulation time | 173184930380 ps |
CPU time | 4228.8 seconds |
Started | Jun 27 06:49:50 PM PDT 24 |
Finished | Jun 27 08:00:22 PM PDT 24 |
Peak memory | 378772 kb |
Host | smart-c8ae1780-d6d4-4fe5-bd64-8bae65faa33a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456539235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 14.sram_ctrl_stress_all.456539235 |
Directory | /workspace/14.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.874162825 |
Short name | T901 |
Test name | |
Test status | |
Simulation time | 8660287249 ps |
CPU time | 55.67 seconds |
Started | Jun 27 06:49:59 PM PDT 24 |
Finished | Jun 27 06:50:59 PM PDT 24 |
Peak memory | 214184 kb |
Host | smart-7dcce965-507c-4b60-bada-4a2bd6fc4c1a |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=874162825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.874162825 |
Directory | /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_pipeline.1036491804 |
Short name | T718 |
Test name | |
Test status | |
Simulation time | 3434816134 ps |
CPU time | 189.99 seconds |
Started | Jun 27 06:49:55 PM PDT 24 |
Finished | Jun 27 06:53:08 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-c5a52c9b-8ec3-497a-8883-f6ff8ad466f8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036491804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_stress_pipeline.1036491804 |
Directory | /workspace/14.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3039065933 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 738668306 ps |
CPU time | 22.81 seconds |
Started | Jun 27 06:49:49 PM PDT 24 |
Finished | Jun 27 06:50:15 PM PDT 24 |
Peak memory | 257112 kb |
Host | smart-cbb14749-0370-497b-9476-13bddf0e3588 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039065933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.3039065933 |
Directory | /workspace/14.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_access_during_key_req.473713648 |
Short name | T785 |
Test name | |
Test status | |
Simulation time | 20432742017 ps |
CPU time | 1435.37 seconds |
Started | Jun 27 06:49:52 PM PDT 24 |
Finished | Jun 27 07:13:50 PM PDT 24 |
Peak memory | 379128 kb |
Host | smart-1630c688-f0a1-4048-bf76-633fd6cbdb34 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473713648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 15.sram_ctrl_access_during_key_req.473713648 |
Directory | /workspace/15.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_alert_test.2533706319 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 23307033 ps |
CPU time | 0.64 seconds |
Started | Jun 27 06:49:57 PM PDT 24 |
Finished | Jun 27 06:49:59 PM PDT 24 |
Peak memory | 202376 kb |
Host | smart-ceb07cb4-f09f-4050-b97f-3a2612c4f51a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533706319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.2533706319 |
Directory | /workspace/15.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_bijection.2921594343 |
Short name | T694 |
Test name | |
Test status | |
Simulation time | 18107416864 ps |
CPU time | 1238.07 seconds |
Started | Jun 27 06:49:59 PM PDT 24 |
Finished | Jun 27 07:10:41 PM PDT 24 |
Peak memory | 203700 kb |
Host | smart-cc58f28f-5589-4e99-b58d-03d98585c2e6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921594343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection .2921594343 |
Directory | /workspace/15.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_executable.2746401556 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 101077385913 ps |
CPU time | 1517.05 seconds |
Started | Jun 27 06:49:52 PM PDT 24 |
Finished | Jun 27 07:15:11 PM PDT 24 |
Peak memory | 376716 kb |
Host | smart-cee51e45-8135-414c-a0ea-737559cee8ba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746401556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executab le.2746401556 |
Directory | /workspace/15.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_max_throughput.3227400598 |
Short name | T485 |
Test name | |
Test status | |
Simulation time | 2848619108 ps |
CPU time | 27.36 seconds |
Started | Jun 27 06:49:47 PM PDT 24 |
Finished | Jun 27 06:50:19 PM PDT 24 |
Peak memory | 278880 kb |
Host | smart-6742e3b7-ec75-4e0a-bad5-f0da0e2cddf9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227400598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 15.sram_ctrl_max_throughput.3227400598 |
Directory | /workspace/15.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_mem_partial_access.563521077 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 4978345011 ps |
CPU time | 151.43 seconds |
Started | Jun 27 06:49:56 PM PDT 24 |
Finished | Jun 27 06:52:30 PM PDT 24 |
Peak memory | 211052 kb |
Host | smart-1acee31b-fe48-445f-a869-68e84757c2ba |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563521077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15 .sram_ctrl_mem_partial_access.563521077 |
Directory | /workspace/15.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_mem_walk.4000572474 |
Short name | T508 |
Test name | |
Test status | |
Simulation time | 20695833115 ps |
CPU time | 331.91 seconds |
Started | Jun 27 06:50:02 PM PDT 24 |
Finished | Jun 27 06:55:37 PM PDT 24 |
Peak memory | 211000 kb |
Host | smart-e41f2863-a431-4fac-bfee-1320fd3e00bd |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000572474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr l_mem_walk.4000572474 |
Directory | /workspace/15.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_multiple_keys.1936602669 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 159283004681 ps |
CPU time | 1138.9 seconds |
Started | Jun 27 06:50:02 PM PDT 24 |
Finished | Jun 27 07:09:05 PM PDT 24 |
Peak memory | 377284 kb |
Host | smart-2cbcaf5f-7d7e-4d42-b248-02bba80dcdda |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936602669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multi ple_keys.1936602669 |
Directory | /workspace/15.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_partial_access.3660551250 |
Short name | T506 |
Test name | |
Test status | |
Simulation time | 1860004158 ps |
CPU time | 49.56 seconds |
Started | Jun 27 06:49:56 PM PDT 24 |
Finished | Jun 27 06:50:48 PM PDT 24 |
Peak memory | 296648 kb |
Host | smart-dc546fb9-aec8-4eb7-beda-e79d9f9410ba |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660551250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15. sram_ctrl_partial_access.3660551250 |
Directory | /workspace/15.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.2809129504 |
Short name | T475 |
Test name | |
Test status | |
Simulation time | 205192775506 ps |
CPU time | 435.8 seconds |
Started | Jun 27 06:49:59 PM PDT 24 |
Finished | Jun 27 06:57:18 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-c20cde39-efdd-4445-b9ec-f6c067e79870 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809129504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 15.sram_ctrl_partial_access_b2b.2809129504 |
Directory | /workspace/15.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_ram_cfg.1710019784 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 372472508 ps |
CPU time | 3.16 seconds |
Started | Jun 27 06:49:56 PM PDT 24 |
Finished | Jun 27 06:50:02 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-a36d5a94-68c7-43a5-80ef-b242fe40e0d2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710019784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.1710019784 |
Directory | /workspace/15.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_regwen.2227931919 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 36009545282 ps |
CPU time | 694.55 seconds |
Started | Jun 27 06:49:50 PM PDT 24 |
Finished | Jun 27 07:01:28 PM PDT 24 |
Peak memory | 376672 kb |
Host | smart-a0750a12-481b-48e6-92cb-5752be12fdc2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227931919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.2227931919 |
Directory | /workspace/15.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_smoke.2773082522 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 367137534 ps |
CPU time | 3.76 seconds |
Started | Jun 27 06:49:58 PM PDT 24 |
Finished | Jun 27 06:50:04 PM PDT 24 |
Peak memory | 202688 kb |
Host | smart-71659b89-7913-4d80-a704-0673fa66be3a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773082522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.2773082522 |
Directory | /workspace/15.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_all.910447025 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 28617244045 ps |
CPU time | 644.36 seconds |
Started | Jun 27 06:49:50 PM PDT 24 |
Finished | Jun 27 07:00:38 PM PDT 24 |
Peak memory | 362300 kb |
Host | smart-7d0de197-0209-43ed-b0e9-9b49f5f6fe1e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910447025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 15.sram_ctrl_stress_all.910447025 |
Directory | /workspace/15.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.81100971 |
Short name | T626 |
Test name | |
Test status | |
Simulation time | 940849811 ps |
CPU time | 13.05 seconds |
Started | Jun 27 06:49:47 PM PDT 24 |
Finished | Jun 27 06:50:04 PM PDT 24 |
Peak memory | 211136 kb |
Host | smart-745dc9f7-d6f9-4084-97d9-8315d538aacb |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=81100971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.81100971 |
Directory | /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_pipeline.2895858278 |
Short name | T573 |
Test name | |
Test status | |
Simulation time | 4833337699 ps |
CPU time | 319.96 seconds |
Started | Jun 27 06:49:55 PM PDT 24 |
Finished | Jun 27 06:55:17 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-6afff32b-2da4-40a2-b4f0-2b1f8b211bef |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895858278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_stress_pipeline.2895858278 |
Directory | /workspace/15.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2076923174 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 1573015886 ps |
CPU time | 151.14 seconds |
Started | Jun 27 06:49:56 PM PDT 24 |
Finished | Jun 27 06:52:29 PM PDT 24 |
Peak memory | 371484 kb |
Host | smart-c38592e0-0fcd-442e-a213-6b3b327de8a6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076923174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.2076923174 |
Directory | /workspace/15.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_access_during_key_req.1919178781 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 9229998320 ps |
CPU time | 860.84 seconds |
Started | Jun 27 06:50:02 PM PDT 24 |
Finished | Jun 27 07:04:28 PM PDT 24 |
Peak memory | 379848 kb |
Host | smart-aa99d063-9378-4b5f-9c0c-24974ea15f4f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919178781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_access_during_key_req.1919178781 |
Directory | /workspace/16.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_alert_test.2271800597 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 31022111 ps |
CPU time | 0.69 seconds |
Started | Jun 27 06:50:04 PM PDT 24 |
Finished | Jun 27 06:50:08 PM PDT 24 |
Peak memory | 202560 kb |
Host | smart-a1778827-25a9-4a01-abfa-f076e9a38aaa |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271800597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.2271800597 |
Directory | /workspace/16.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_bijection.199458032 |
Short name | T692 |
Test name | |
Test status | |
Simulation time | 368342154082 ps |
CPU time | 2258.03 seconds |
Started | Jun 27 06:49:53 PM PDT 24 |
Finished | Jun 27 07:27:34 PM PDT 24 |
Peak memory | 203412 kb |
Host | smart-d76a1d55-6007-46e5-9429-482dbeceda3d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199458032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection. 199458032 |
Directory | /workspace/16.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_executable.2774107663 |
Short name | T856 |
Test name | |
Test status | |
Simulation time | 22871178542 ps |
CPU time | 536.75 seconds |
Started | Jun 27 06:50:01 PM PDT 24 |
Finished | Jun 27 06:59:02 PM PDT 24 |
Peak memory | 357300 kb |
Host | smart-4a957760-029f-49ef-ada8-ec6e459b982c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774107663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executab le.2774107663 |
Directory | /workspace/16.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_lc_escalation.2107361840 |
Short name | T480 |
Test name | |
Test status | |
Simulation time | 8667914099 ps |
CPU time | 51.81 seconds |
Started | Jun 27 06:50:00 PM PDT 24 |
Finished | Jun 27 06:50:56 PM PDT 24 |
Peak memory | 211132 kb |
Host | smart-69bbe1fb-48b7-40db-8871-295ec293b1d8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107361840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_es calation.2107361840 |
Directory | /workspace/16.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_max_throughput.3318083829 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 1647110429 ps |
CPU time | 9 seconds |
Started | Jun 27 06:50:04 PM PDT 24 |
Finished | Jun 27 06:50:17 PM PDT 24 |
Peak memory | 219076 kb |
Host | smart-2b1fb172-26f7-4732-90be-0b1e54d45928 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318083829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 16.sram_ctrl_max_throughput.3318083829 |
Directory | /workspace/16.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_mem_partial_access.1372949531 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 29166707739 ps |
CPU time | 157.9 seconds |
Started | Jun 27 06:50:03 PM PDT 24 |
Finished | Jun 27 06:52:45 PM PDT 24 |
Peak memory | 211076 kb |
Host | smart-c39b4b3f-83b4-4dfd-9df5-e3330a0c2064 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372949531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_mem_partial_access.1372949531 |
Directory | /workspace/16.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_mem_walk.3662367849 |
Short name | T848 |
Test name | |
Test status | |
Simulation time | 5479465585 ps |
CPU time | 154.29 seconds |
Started | Jun 27 06:50:03 PM PDT 24 |
Finished | Jun 27 06:52:41 PM PDT 24 |
Peak memory | 210976 kb |
Host | smart-061b5b33-3f0d-470e-828b-26a515f9baff |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662367849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr l_mem_walk.3662367849 |
Directory | /workspace/16.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_multiple_keys.841901173 |
Short name | T737 |
Test name | |
Test status | |
Simulation time | 58978719255 ps |
CPU time | 588.31 seconds |
Started | Jun 27 06:50:02 PM PDT 24 |
Finished | Jun 27 06:59:54 PM PDT 24 |
Peak memory | 373660 kb |
Host | smart-77988249-8842-481f-bccd-21e587a6793a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841901173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multip le_keys.841901173 |
Directory | /workspace/16.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_partial_access.2852382159 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 1773053541 ps |
CPU time | 24.67 seconds |
Started | Jun 27 06:49:52 PM PDT 24 |
Finished | Jun 27 06:50:19 PM PDT 24 |
Peak memory | 265988 kb |
Host | smart-0b700497-b4a9-4990-bc02-86dc50b352d6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852382159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16. sram_ctrl_partial_access.2852382159 |
Directory | /workspace/16.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.2237333682 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 65939332382 ps |
CPU time | 406.84 seconds |
Started | Jun 27 06:50:03 PM PDT 24 |
Finished | Jun 27 06:56:53 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-9445d59b-9fdc-45dc-bdfd-9e6dc280717c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237333682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 16.sram_ctrl_partial_access_b2b.2237333682 |
Directory | /workspace/16.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_ram_cfg.2543246384 |
Short name | T900 |
Test name | |
Test status | |
Simulation time | 1271979622 ps |
CPU time | 3.15 seconds |
Started | Jun 27 06:50:01 PM PDT 24 |
Finished | Jun 27 06:50:08 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-0ccb5324-9937-42d5-8a41-72a10dfea085 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543246384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.2543246384 |
Directory | /workspace/16.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_regwen.1425251642 |
Short name | T731 |
Test name | |
Test status | |
Simulation time | 48280787727 ps |
CPU time | 333.35 seconds |
Started | Jun 27 06:50:05 PM PDT 24 |
Finished | Jun 27 06:55:41 PM PDT 24 |
Peak memory | 367476 kb |
Host | smart-266f30f9-c7ef-4c06-9e3f-bcaccb55fa5f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425251642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.1425251642 |
Directory | /workspace/16.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_smoke.1605324451 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 3481759048 ps |
CPU time | 19.71 seconds |
Started | Jun 27 06:49:51 PM PDT 24 |
Finished | Jun 27 06:50:13 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-dcd95b5b-0597-46ce-9c5f-88c845e666c6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605324451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.1605324451 |
Directory | /workspace/16.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_all.1376679482 |
Short name | T808 |
Test name | |
Test status | |
Simulation time | 137188568003 ps |
CPU time | 4385.35 seconds |
Started | Jun 27 06:50:03 PM PDT 24 |
Finished | Jun 27 08:03:13 PM PDT 24 |
Peak memory | 380784 kb |
Host | smart-425c2004-499b-4725-9771-e79318201b8d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376679482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 16.sram_ctrl_stress_all.1376679482 |
Directory | /workspace/16.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3242339417 |
Short name | T658 |
Test name | |
Test status | |
Simulation time | 2730428267 ps |
CPU time | 22.14 seconds |
Started | Jun 27 06:50:01 PM PDT 24 |
Finished | Jun 27 06:50:26 PM PDT 24 |
Peak memory | 211116 kb |
Host | smart-df691a2b-070f-41c4-ae50-d8017fc7c8f8 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3242339417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.3242339417 |
Directory | /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_pipeline.3960806097 |
Short name | T876 |
Test name | |
Test status | |
Simulation time | 4753855590 ps |
CPU time | 300.4 seconds |
Started | Jun 27 06:49:49 PM PDT 24 |
Finished | Jun 27 06:54:53 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-d2a91af1-835b-4069-8944-8232007bef9f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960806097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_stress_pipeline.3960806097 |
Directory | /workspace/16.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.20011798 |
Short name | T689 |
Test name | |
Test status | |
Simulation time | 2893885576 ps |
CPU time | 43.38 seconds |
Started | Jun 27 06:50:02 PM PDT 24 |
Finished | Jun 27 06:50:49 PM PDT 24 |
Peak memory | 287656 kb |
Host | smart-c1cd923c-0401-4940-9671-b0dfe0ef2c38 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20011798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 16.sram_ctrl_throughput_w_partial_write.20011798 |
Directory | /workspace/16.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_access_during_key_req.1205955985 |
Short name | T916 |
Test name | |
Test status | |
Simulation time | 8574851806 ps |
CPU time | 321.53 seconds |
Started | Jun 27 06:50:02 PM PDT 24 |
Finished | Jun 27 06:55:28 PM PDT 24 |
Peak memory | 372608 kb |
Host | smart-695e7c87-8819-462d-ae6e-e6ebda369247 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205955985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 17.sram_ctrl_access_during_key_req.1205955985 |
Directory | /workspace/17.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_alert_test.214277859 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 12304832 ps |
CPU time | 0.67 seconds |
Started | Jun 27 06:50:23 PM PDT 24 |
Finished | Jun 27 06:50:26 PM PDT 24 |
Peak memory | 202596 kb |
Host | smart-4c9e2326-1edf-4d50-8a6b-bb5e35ee76d2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214277859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.214277859 |
Directory | /workspace/17.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_bijection.1397068392 |
Short name | T913 |
Test name | |
Test status | |
Simulation time | 119932876573 ps |
CPU time | 1462.36 seconds |
Started | Jun 27 06:50:02 PM PDT 24 |
Finished | Jun 27 07:14:29 PM PDT 24 |
Peak memory | 203440 kb |
Host | smart-4ef43e1a-8912-4107-8988-1680835a9196 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397068392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection .1397068392 |
Directory | /workspace/17.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_executable.641748861 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 25358582468 ps |
CPU time | 652.32 seconds |
Started | Jun 27 06:50:02 PM PDT 24 |
Finished | Jun 27 07:00:59 PM PDT 24 |
Peak memory | 378768 kb |
Host | smart-39aa6c07-55e8-4b55-bed6-c96edbd818c4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641748861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executabl e.641748861 |
Directory | /workspace/17.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_lc_escalation.564073031 |
Short name | T556 |
Test name | |
Test status | |
Simulation time | 3773064508 ps |
CPU time | 13.01 seconds |
Started | Jun 27 06:50:03 PM PDT 24 |
Finished | Jun 27 06:50:20 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-e646f90f-3c16-43d5-96e5-b31f7571bae6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564073031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_esc alation.564073031 |
Directory | /workspace/17.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_max_throughput.1522044387 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 1935020710 ps |
CPU time | 18.42 seconds |
Started | Jun 27 06:50:02 PM PDT 24 |
Finished | Jun 27 06:50:24 PM PDT 24 |
Peak memory | 251768 kb |
Host | smart-6792e1d0-6d93-40eb-bbde-9594d40ef961 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522044387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 17.sram_ctrl_max_throughput.1522044387 |
Directory | /workspace/17.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_mem_partial_access.1576106493 |
Short name | T879 |
Test name | |
Test status | |
Simulation time | 5559013207 ps |
CPU time | 75.73 seconds |
Started | Jun 27 06:50:00 PM PDT 24 |
Finished | Jun 27 06:51:20 PM PDT 24 |
Peak memory | 211096 kb |
Host | smart-e7f45454-a98c-41e5-b62b-1711db2e9829 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576106493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_mem_partial_access.1576106493 |
Directory | /workspace/17.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_mem_walk.346660845 |
Short name | T834 |
Test name | |
Test status | |
Simulation time | 115168648643 ps |
CPU time | 360.55 seconds |
Started | Jun 27 06:50:01 PM PDT 24 |
Finished | Jun 27 06:56:05 PM PDT 24 |
Peak memory | 204152 kb |
Host | smart-5c6ff8ca-550a-4d3f-b668-69aecf35ca15 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346660845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl _mem_walk.346660845 |
Directory | /workspace/17.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_multiple_keys.2938367678 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 4223716829 ps |
CPU time | 380.86 seconds |
Started | Jun 27 06:50:01 PM PDT 24 |
Finished | Jun 27 06:56:26 PM PDT 24 |
Peak memory | 370528 kb |
Host | smart-d0d2cf6a-9138-41f4-9654-61800694b58e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938367678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi ple_keys.2938367678 |
Directory | /workspace/17.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_partial_access.1564572588 |
Short name | T586 |
Test name | |
Test status | |
Simulation time | 1014629881 ps |
CPU time | 35.76 seconds |
Started | Jun 27 06:50:01 PM PDT 24 |
Finished | Jun 27 06:50:41 PM PDT 24 |
Peak memory | 276588 kb |
Host | smart-3f3dcc75-eb37-4780-8347-eb30b1b8d46e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564572588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17. sram_ctrl_partial_access.1564572588 |
Directory | /workspace/17.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.4040534082 |
Short name | T639 |
Test name | |
Test status | |
Simulation time | 34787863633 ps |
CPU time | 213.13 seconds |
Started | Jun 27 06:50:01 PM PDT 24 |
Finished | Jun 27 06:53:39 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-988ebde6-0022-48ec-a418-9e780462ffb3 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040534082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 17.sram_ctrl_partial_access_b2b.4040534082 |
Directory | /workspace/17.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_ram_cfg.117299523 |
Short name | T544 |
Test name | |
Test status | |
Simulation time | 1343175678 ps |
CPU time | 3.56 seconds |
Started | Jun 27 06:50:05 PM PDT 24 |
Finished | Jun 27 06:50:12 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-49dd4744-1a58-49f3-a70a-b0b089e389c2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117299523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.117299523 |
Directory | /workspace/17.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_regwen.3839511562 |
Short name | T863 |
Test name | |
Test status | |
Simulation time | 106052665396 ps |
CPU time | 1120.6 seconds |
Started | Jun 27 06:50:01 PM PDT 24 |
Finished | Jun 27 07:08:46 PM PDT 24 |
Peak memory | 373672 kb |
Host | smart-03896252-3670-4e27-bc49-af71ee62eedc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839511562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.3839511562 |
Directory | /workspace/17.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_smoke.2752289173 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 5131841443 ps |
CPU time | 13.59 seconds |
Started | Jun 27 06:50:02 PM PDT 24 |
Finished | Jun 27 06:50:20 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-51a8376d-bde8-4f58-8bfb-2e7b0564cb93 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752289173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.2752289173 |
Directory | /workspace/17.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_all.1079618610 |
Short name | T721 |
Test name | |
Test status | |
Simulation time | 989308966091 ps |
CPU time | 5170.12 seconds |
Started | Jun 27 06:50:22 PM PDT 24 |
Finished | Jun 27 08:16:34 PM PDT 24 |
Peak memory | 382848 kb |
Host | smart-15665ec0-a6f7-44dd-a9fb-db8314f3b2a2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079618610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 17.sram_ctrl_stress_all.1079618610 |
Directory | /workspace/17.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.3553603014 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 8005864352 ps |
CPU time | 56.04 seconds |
Started | Jun 27 06:50:03 PM PDT 24 |
Finished | Jun 27 06:51:03 PM PDT 24 |
Peak memory | 212312 kb |
Host | smart-3986ce45-95f6-4d1d-bd53-045d9054b5ba |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3553603014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.3553603014 |
Directory | /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_pipeline.1914822663 |
Short name | T652 |
Test name | |
Test status | |
Simulation time | 39577456622 ps |
CPU time | 398.33 seconds |
Started | Jun 27 06:50:04 PM PDT 24 |
Finished | Jun 27 06:56:46 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-036ece97-551c-4792-a31d-b33d347d2449 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914822663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_stress_pipeline.1914822663 |
Directory | /workspace/17.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.4251041264 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 1502392220 ps |
CPU time | 48.35 seconds |
Started | Jun 27 06:50:01 PM PDT 24 |
Finished | Jun 27 06:50:53 PM PDT 24 |
Peak memory | 291324 kb |
Host | smart-1bc0c3ae-4fff-42aa-a062-a4e3dd22fe18 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251041264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.4251041264 |
Directory | /workspace/17.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_access_during_key_req.1634995458 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 11878806167 ps |
CPU time | 857.74 seconds |
Started | Jun 27 06:50:22 PM PDT 24 |
Finished | Jun 27 07:04:41 PM PDT 24 |
Peak memory | 378740 kb |
Host | smart-6200d3a8-7f3b-46b3-af3f-8132f3f548a8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634995458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_access_during_key_req.1634995458 |
Directory | /workspace/18.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_alert_test.4052269040 |
Short name | T678 |
Test name | |
Test status | |
Simulation time | 23857511 ps |
CPU time | 0.68 seconds |
Started | Jun 27 06:50:22 PM PDT 24 |
Finished | Jun 27 06:50:24 PM PDT 24 |
Peak memory | 202580 kb |
Host | smart-4554fdfc-c47c-4ed6-9a58-79bca4a8cbf5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052269040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.4052269040 |
Directory | /workspace/18.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_bijection.3381543443 |
Short name | T460 |
Test name | |
Test status | |
Simulation time | 67667530454 ps |
CPU time | 2269.7 seconds |
Started | Jun 27 06:50:23 PM PDT 24 |
Finished | Jun 27 07:28:15 PM PDT 24 |
Peak memory | 202964 kb |
Host | smart-ba1df114-459a-45d6-9eec-db90491b3c00 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381543443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection .3381543443 |
Directory | /workspace/18.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_executable.1884398166 |
Short name | T741 |
Test name | |
Test status | |
Simulation time | 39695621798 ps |
CPU time | 1505.94 seconds |
Started | Jun 27 06:50:21 PM PDT 24 |
Finished | Jun 27 07:15:29 PM PDT 24 |
Peak memory | 379800 kb |
Host | smart-620c33a8-40b9-4281-ba33-a15bf8c481a3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884398166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executab le.1884398166 |
Directory | /workspace/18.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_lc_escalation.3208173230 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 11406990627 ps |
CPU time | 67.92 seconds |
Started | Jun 27 06:50:24 PM PDT 24 |
Finished | Jun 27 06:51:33 PM PDT 24 |
Peak memory | 211272 kb |
Host | smart-0888bab8-cfd1-41ab-95d5-4787d7859562 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208173230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_es calation.3208173230 |
Directory | /workspace/18.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_max_throughput.2344098948 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 2905060163 ps |
CPU time | 61.66 seconds |
Started | Jun 27 06:50:22 PM PDT 24 |
Finished | Jun 27 06:51:25 PM PDT 24 |
Peak memory | 300944 kb |
Host | smart-f6cbb574-4303-4618-b87a-2bc16eb21a20 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344098948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 18.sram_ctrl_max_throughput.2344098948 |
Directory | /workspace/18.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_mem_partial_access.2104432612 |
Short name | T854 |
Test name | |
Test status | |
Simulation time | 11635014731 ps |
CPU time | 91.41 seconds |
Started | Jun 27 06:50:23 PM PDT 24 |
Finished | Jun 27 06:51:56 PM PDT 24 |
Peak memory | 211004 kb |
Host | smart-9fc41261-fbf0-42fe-b4eb-0b07454adfa1 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104432612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_mem_partial_access.2104432612 |
Directory | /workspace/18.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_mem_walk.2690239045 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 5308576248 ps |
CPU time | 299.2 seconds |
Started | Jun 27 06:50:22 PM PDT 24 |
Finished | Jun 27 06:55:23 PM PDT 24 |
Peak memory | 211024 kb |
Host | smart-73cb35ef-fcd3-404f-962f-2587e84502a2 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690239045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr l_mem_walk.2690239045 |
Directory | /workspace/18.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_multiple_keys.3240610302 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 19044621633 ps |
CPU time | 870.01 seconds |
Started | Jun 27 06:50:23 PM PDT 24 |
Finished | Jun 27 07:04:54 PM PDT 24 |
Peak memory | 381104 kb |
Host | smart-ee45bf95-c34b-4f0c-969a-1c24ce7b3e20 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240610302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multi ple_keys.3240610302 |
Directory | /workspace/18.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_partial_access.424270741 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 2205584786 ps |
CPU time | 15.3 seconds |
Started | Jun 27 06:50:23 PM PDT 24 |
Finished | Jun 27 06:50:40 PM PDT 24 |
Peak memory | 240768 kb |
Host | smart-c06fba8b-d223-44c7-8e7c-10c455bf3776 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424270741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.s ram_ctrl_partial_access.424270741 |
Directory | /workspace/18.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.2027242547 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 124867951122 ps |
CPU time | 540.74 seconds |
Started | Jun 27 06:50:23 PM PDT 24 |
Finished | Jun 27 06:59:25 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-f435b02a-3c37-4cb4-804b-b18c31d3ae39 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027242547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 18.sram_ctrl_partial_access_b2b.2027242547 |
Directory | /workspace/18.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_ram_cfg.2027153260 |
Short name | T816 |
Test name | |
Test status | |
Simulation time | 709008982 ps |
CPU time | 3.28 seconds |
Started | Jun 27 06:50:23 PM PDT 24 |
Finished | Jun 27 06:50:28 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-4b536d68-466b-4808-81e0-c58960d30da2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027153260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.2027153260 |
Directory | /workspace/18.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_regwen.2795097866 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 2851182024 ps |
CPU time | 698.32 seconds |
Started | Jun 27 06:50:24 PM PDT 24 |
Finished | Jun 27 07:02:03 PM PDT 24 |
Peak memory | 368460 kb |
Host | smart-8c0a650e-4e7a-44a7-8d4f-43336a68a7ba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795097866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.2795097866 |
Directory | /workspace/18.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_smoke.4125573378 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 1083671126 ps |
CPU time | 17.9 seconds |
Started | Jun 27 06:50:23 PM PDT 24 |
Finished | Jun 27 06:50:42 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-88f8746c-2cb9-4f23-ac8d-b556aca19ecc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125573378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.4125573378 |
Directory | /workspace/18.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_all.1712809712 |
Short name | T672 |
Test name | |
Test status | |
Simulation time | 25907912032 ps |
CPU time | 210.37 seconds |
Started | Jun 27 06:50:24 PM PDT 24 |
Finished | Jun 27 06:53:55 PM PDT 24 |
Peak memory | 334688 kb |
Host | smart-eaadf223-35d2-4a00-bf44-4b7432d86bdf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712809712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 18.sram_ctrl_stress_all.1712809712 |
Directory | /workspace/18.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.301633694 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 335586574 ps |
CPU time | 14.99 seconds |
Started | Jun 27 06:50:22 PM PDT 24 |
Finished | Jun 27 06:50:39 PM PDT 24 |
Peak memory | 211064 kb |
Host | smart-fee0e3d7-9e56-49ce-a343-4fef8bbf55a9 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=301633694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.301633694 |
Directory | /workspace/18.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_pipeline.3261494195 |
Short name | T477 |
Test name | |
Test status | |
Simulation time | 2873930132 ps |
CPU time | 191.71 seconds |
Started | Jun 27 06:50:23 PM PDT 24 |
Finished | Jun 27 06:53:37 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-96c84b6c-c298-4a91-aa09-a54ceed15c54 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261494195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_stress_pipeline.3261494195 |
Directory | /workspace/18.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.3833347366 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 3151287447 ps |
CPU time | 178.97 seconds |
Started | Jun 27 06:50:23 PM PDT 24 |
Finished | Jun 27 06:53:24 PM PDT 24 |
Peak memory | 371584 kb |
Host | smart-845b3d56-961b-4602-903f-5e80b28ba378 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833347366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.3833347366 |
Directory | /workspace/18.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_access_during_key_req.2083424646 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 29158218896 ps |
CPU time | 216.41 seconds |
Started | Jun 27 06:50:34 PM PDT 24 |
Finished | Jun 27 06:54:12 PM PDT 24 |
Peak memory | 343656 kb |
Host | smart-9012c5fd-10c6-4e88-bb06-00bb17fee660 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083424646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 19.sram_ctrl_access_during_key_req.2083424646 |
Directory | /workspace/19.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_alert_test.1066722460 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 54010402 ps |
CPU time | 0.67 seconds |
Started | Jun 27 06:50:37 PM PDT 24 |
Finished | Jun 27 06:50:42 PM PDT 24 |
Peak memory | 202444 kb |
Host | smart-b32aa7d7-2ca8-4167-a856-955c02299fdf |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066722460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.1066722460 |
Directory | /workspace/19.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_executable.1339519780 |
Short name | T612 |
Test name | |
Test status | |
Simulation time | 4350941093 ps |
CPU time | 214.52 seconds |
Started | Jun 27 06:50:37 PM PDT 24 |
Finished | Jun 27 06:54:15 PM PDT 24 |
Peak memory | 376672 kb |
Host | smart-4987d1ae-b81a-46d1-9bd4-54f357fde577 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339519780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executab le.1339519780 |
Directory | /workspace/19.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_lc_escalation.1705581866 |
Short name | T905 |
Test name | |
Test status | |
Simulation time | 23139901558 ps |
CPU time | 67.61 seconds |
Started | Jun 27 06:50:37 PM PDT 24 |
Finished | Jun 27 06:51:49 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-7285edbd-1f7f-4d6a-818d-2ef3af2e1383 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705581866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es calation.1705581866 |
Directory | /workspace/19.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_max_throughput.1543490586 |
Short name | T461 |
Test name | |
Test status | |
Simulation time | 761687480 ps |
CPU time | 37.69 seconds |
Started | Jun 27 06:50:38 PM PDT 24 |
Finished | Jun 27 06:51:21 PM PDT 24 |
Peak memory | 295788 kb |
Host | smart-220c7f2a-41c5-4ef8-a649-ffc82dfb5bae |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543490586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 19.sram_ctrl_max_throughput.1543490586 |
Directory | /workspace/19.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_mem_partial_access.2842414910 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 19991682446 ps |
CPU time | 157.78 seconds |
Started | Jun 27 06:50:39 PM PDT 24 |
Finished | Jun 27 06:53:21 PM PDT 24 |
Peak memory | 211056 kb |
Host | smart-aa9e0503-0d2f-4f2a-83b0-c34e97ddbb25 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842414910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_mem_partial_access.2842414910 |
Directory | /workspace/19.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_mem_walk.603170902 |
Short name | T864 |
Test name | |
Test status | |
Simulation time | 10448676780 ps |
CPU time | 182.2 seconds |
Started | Jun 27 06:50:41 PM PDT 24 |
Finished | Jun 27 06:53:46 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-d9b0966b-85d0-4fdd-857f-107b6a3fc702 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603170902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl _mem_walk.603170902 |
Directory | /workspace/19.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_multiple_keys.2776457710 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 13401928864 ps |
CPU time | 1046.04 seconds |
Started | Jun 27 06:50:35 PM PDT 24 |
Finished | Jun 27 07:08:05 PM PDT 24 |
Peak memory | 379820 kb |
Host | smart-d81f7cee-35d1-433c-a886-5e58d31b6c06 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776457710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi ple_keys.2776457710 |
Directory | /workspace/19.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_partial_access.3809067833 |
Short name | T466 |
Test name | |
Test status | |
Simulation time | 2069848333 ps |
CPU time | 15.41 seconds |
Started | Jun 27 06:50:37 PM PDT 24 |
Finished | Jun 27 06:50:57 PM PDT 24 |
Peak memory | 202772 kb |
Host | smart-fb9fd305-727d-4591-a4d4-21ac27709e36 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809067833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19. sram_ctrl_partial_access.3809067833 |
Directory | /workspace/19.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.3985963970 |
Short name | T903 |
Test name | |
Test status | |
Simulation time | 11139409798 ps |
CPU time | 251.27 seconds |
Started | Jun 27 06:50:41 PM PDT 24 |
Finished | Jun 27 06:54:55 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-9870542d-408a-4f3d-a78d-2ba12cdca16f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985963970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 19.sram_ctrl_partial_access_b2b.3985963970 |
Directory | /workspace/19.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_ram_cfg.1511736840 |
Short name | T687 |
Test name | |
Test status | |
Simulation time | 354897759 ps |
CPU time | 3.66 seconds |
Started | Jun 27 06:50:35 PM PDT 24 |
Finished | Jun 27 06:50:42 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-e1ccddee-e2a9-4d04-a2ce-5b074e72cbb9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511736840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.1511736840 |
Directory | /workspace/19.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_regwen.3064390548 |
Short name | T843 |
Test name | |
Test status | |
Simulation time | 25273074291 ps |
CPU time | 993.01 seconds |
Started | Jun 27 06:50:36 PM PDT 24 |
Finished | Jun 27 07:07:14 PM PDT 24 |
Peak memory | 378760 kb |
Host | smart-b6639f31-464a-4117-b77c-f1fc6793950f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064390548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.3064390548 |
Directory | /workspace/19.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_smoke.4033757229 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 844483775 ps |
CPU time | 19.98 seconds |
Started | Jun 27 06:50:34 PM PDT 24 |
Finished | Jun 27 06:50:56 PM PDT 24 |
Peak memory | 202752 kb |
Host | smart-b881d9e7-6fda-4ff5-a843-4581a20be7ef |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033757229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.4033757229 |
Directory | /workspace/19.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_all.706213882 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 219081848715 ps |
CPU time | 7889.12 seconds |
Started | Jun 27 06:50:40 PM PDT 24 |
Finished | Jun 27 09:02:13 PM PDT 24 |
Peak memory | 382848 kb |
Host | smart-02f5724a-e066-48e7-95e2-964b62905dfe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706213882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 19.sram_ctrl_stress_all.706213882 |
Directory | /workspace/19.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.516403677 |
Short name | T524 |
Test name | |
Test status | |
Simulation time | 1028216245 ps |
CPU time | 9.63 seconds |
Started | Jun 27 06:50:36 PM PDT 24 |
Finished | Jun 27 06:50:49 PM PDT 24 |
Peak memory | 219308 kb |
Host | smart-107cd964-7a8f-42f2-8716-188c39439fa9 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=516403677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.516403677 |
Directory | /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_pipeline.536182160 |
Short name | T512 |
Test name | |
Test status | |
Simulation time | 22477252663 ps |
CPU time | 386.6 seconds |
Started | Jun 27 06:50:35 PM PDT 24 |
Finished | Jun 27 06:57:04 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-e1a37b1c-6b3a-4e1a-886e-ce982a880599 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536182160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19 .sram_ctrl_stress_pipeline.536182160 |
Directory | /workspace/19.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.1024406367 |
Short name | T800 |
Test name | |
Test status | |
Simulation time | 1883569991 ps |
CPU time | 8.2 seconds |
Started | Jun 27 06:50:38 PM PDT 24 |
Finished | Jun 27 06:50:51 PM PDT 24 |
Peak memory | 219104 kb |
Host | smart-36dd5d5b-84af-4929-9549-699a06cc3012 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024406367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.1024406367 |
Directory | /workspace/19.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_access_during_key_req.1748434253 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 50732991818 ps |
CPU time | 1369.35 seconds |
Started | Jun 27 06:49:12 PM PDT 24 |
Finished | Jun 27 07:12:04 PM PDT 24 |
Peak memory | 380700 kb |
Host | smart-33540384-70dc-4e7e-b2d6-0d0e2bc69c5c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748434253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_access_during_key_req.1748434253 |
Directory | /workspace/2.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_alert_test.2189445671 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 13426306 ps |
CPU time | 0.69 seconds |
Started | Jun 27 06:49:14 PM PDT 24 |
Finished | Jun 27 06:49:18 PM PDT 24 |
Peak memory | 202424 kb |
Host | smart-ac2f0ebd-e82e-4ccf-9495-365bc2fd2b1f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189445671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.2189445671 |
Directory | /workspace/2.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_bijection.1872046579 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 191966923994 ps |
CPU time | 2180.75 seconds |
Started | Jun 27 06:49:13 PM PDT 24 |
Finished | Jun 27 07:25:36 PM PDT 24 |
Peak memory | 202976 kb |
Host | smart-9c7161f8-3da7-4be5-9740-16589909534c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872046579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection. 1872046579 |
Directory | /workspace/2.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_executable.4000025379 |
Short name | T814 |
Test name | |
Test status | |
Simulation time | 23799078585 ps |
CPU time | 729.82 seconds |
Started | Jun 27 06:49:12 PM PDT 24 |
Finished | Jun 27 07:01:24 PM PDT 24 |
Peak memory | 373612 kb |
Host | smart-ea71b153-2bd1-4ca2-be20-b61687e06a8c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000025379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executabl e.4000025379 |
Directory | /workspace/2.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_lc_escalation.2875532360 |
Short name | T617 |
Test name | |
Test status | |
Simulation time | 191484461434 ps |
CPU time | 115.86 seconds |
Started | Jun 27 06:49:13 PM PDT 24 |
Finished | Jun 27 06:51:12 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-51205c9b-e3e3-4e41-95cb-d173bf3d86cf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875532360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc alation.2875532360 |
Directory | /workspace/2.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_max_throughput.4066565345 |
Short name | T660 |
Test name | |
Test status | |
Simulation time | 716271022 ps |
CPU time | 8.98 seconds |
Started | Jun 27 06:49:16 PM PDT 24 |
Finished | Jun 27 06:49:28 PM PDT 24 |
Peak memory | 219152 kb |
Host | smart-7853a9ae-5e60-49ab-a28b-ac2701ea1d8a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066565345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.sram_ctrl_max_throughput.4066565345 |
Directory | /workspace/2.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_mem_partial_access.3460028306 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 5227964258 ps |
CPU time | 151.19 seconds |
Started | Jun 27 06:49:16 PM PDT 24 |
Finished | Jun 27 06:51:51 PM PDT 24 |
Peak memory | 211108 kb |
Host | smart-dde63703-f2b4-45dd-93b2-548ac5b1d6d1 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460028306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_mem_partial_access.3460028306 |
Directory | /workspace/2.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_mem_walk.2210279049 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 35799570983 ps |
CPU time | 266.82 seconds |
Started | Jun 27 06:49:12 PM PDT 24 |
Finished | Jun 27 06:53:41 PM PDT 24 |
Peak memory | 211056 kb |
Host | smart-941e5d8d-252c-482b-8c17-e6e306144e3c |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210279049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl _mem_walk.2210279049 |
Directory | /workspace/2.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_multiple_keys.2163436230 |
Short name | T522 |
Test name | |
Test status | |
Simulation time | 19221885210 ps |
CPU time | 656.91 seconds |
Started | Jun 27 06:49:15 PM PDT 24 |
Finished | Jun 27 07:00:16 PM PDT 24 |
Peak memory | 367120 kb |
Host | smart-116189d8-f45b-4a2a-98d3-4f724cbe7371 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163436230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip le_keys.2163436230 |
Directory | /workspace/2.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_partial_access.1957206547 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 963167712 ps |
CPU time | 149.17 seconds |
Started | Jun 27 06:49:14 PM PDT 24 |
Finished | Jun 27 06:51:47 PM PDT 24 |
Peak memory | 361180 kb |
Host | smart-aa6bcaeb-3386-4ed3-9640-fbc98ecf68bd |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957206547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s ram_ctrl_partial_access.1957206547 |
Directory | /workspace/2.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.774756864 |
Short name | T613 |
Test name | |
Test status | |
Simulation time | 19801262860 ps |
CPU time | 235.62 seconds |
Started | Jun 27 06:49:13 PM PDT 24 |
Finished | Jun 27 06:53:13 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-4d09951c-feb2-4398-b93e-79ee245ff34f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774756864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.sram_ctrl_partial_access_b2b.774756864 |
Directory | /workspace/2.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_ram_cfg.3377964726 |
Short name | T629 |
Test name | |
Test status | |
Simulation time | 403446595 ps |
CPU time | 3.58 seconds |
Started | Jun 27 06:49:15 PM PDT 24 |
Finished | Jun 27 06:49:22 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-210004b7-9e51-476a-b151-31a2272f440e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377964726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.3377964726 |
Directory | /workspace/2.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_regwen.1842257491 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 5249368764 ps |
CPU time | 1320.82 seconds |
Started | Jun 27 06:49:12 PM PDT 24 |
Finished | Jun 27 07:11:16 PM PDT 24 |
Peak memory | 378720 kb |
Host | smart-71ec6bbe-ac69-4b28-82db-b9c1c703b31d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842257491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.1842257491 |
Directory | /workspace/2.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_sec_cm.3534964940 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 214984592 ps |
CPU time | 2.01 seconds |
Started | Jun 27 06:49:13 PM PDT 24 |
Finished | Jun 27 06:49:18 PM PDT 24 |
Peak memory | 222320 kb |
Host | smart-df747ab5-84bd-45d0-b7fa-0c575b6fc782 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534964940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.3534964940 |
Directory | /workspace/2.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_smoke.1646183920 |
Short name | T751 |
Test name | |
Test status | |
Simulation time | 1424945384 ps |
CPU time | 3.57 seconds |
Started | Jun 27 06:48:59 PM PDT 24 |
Finished | Jun 27 06:49:07 PM PDT 24 |
Peak memory | 202636 kb |
Host | smart-96c3ac1a-fd27-495b-b4e6-51292ab6bb4c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646183920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.1646183920 |
Directory | /workspace/2.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_all.4186963475 |
Short name | T538 |
Test name | |
Test status | |
Simulation time | 58479766808 ps |
CPU time | 4335.91 seconds |
Started | Jun 27 06:49:13 PM PDT 24 |
Finished | Jun 27 08:01:33 PM PDT 24 |
Peak memory | 381812 kb |
Host | smart-22fc53e9-95b2-4118-93c3-2d7ed9aa0d81 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186963475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 2.sram_ctrl_stress_all.4186963475 |
Directory | /workspace/2.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.1285749700 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 1923820141 ps |
CPU time | 266.8 seconds |
Started | Jun 27 06:49:16 PM PDT 24 |
Finished | Jun 27 06:53:46 PM PDT 24 |
Peak memory | 374552 kb |
Host | smart-93fccd7f-67d5-4166-9fd4-a010b16a7252 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1285749700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.1285749700 |
Directory | /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_pipeline.1300129756 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 3293132304 ps |
CPU time | 216.03 seconds |
Started | Jun 27 06:49:16 PM PDT 24 |
Finished | Jun 27 06:52:56 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-f873e58f-a6cc-4d29-8d34-1ed6ed5982cf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300129756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_stress_pipeline.1300129756 |
Directory | /workspace/2.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.308932439 |
Short name | T827 |
Test name | |
Test status | |
Simulation time | 2958676121 ps |
CPU time | 121.06 seconds |
Started | Jun 27 06:49:15 PM PDT 24 |
Finished | Jun 27 06:51:20 PM PDT 24 |
Peak memory | 347936 kb |
Host | smart-f7823a32-3740-4569-ad9a-093224d51fd4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308932439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.sram_ctrl_throughput_w_partial_write.308932439 |
Directory | /workspace/2.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_access_during_key_req.1943001432 |
Short name | T469 |
Test name | |
Test status | |
Simulation time | 320883234273 ps |
CPU time | 1265.01 seconds |
Started | Jun 27 06:50:36 PM PDT 24 |
Finished | Jun 27 07:11:45 PM PDT 24 |
Peak memory | 379768 kb |
Host | smart-00012ff2-6dd6-47d4-a002-bc988da74bba |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943001432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 20.sram_ctrl_access_during_key_req.1943001432 |
Directory | /workspace/20.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_alert_test.4254143818 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 104612745 ps |
CPU time | 0.64 seconds |
Started | Jun 27 06:50:35 PM PDT 24 |
Finished | Jun 27 06:50:38 PM PDT 24 |
Peak memory | 202584 kb |
Host | smart-018ee207-ab44-4a7e-a3ce-b2e83bf5d546 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254143818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.4254143818 |
Directory | /workspace/20.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_bijection.483894023 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 43361546663 ps |
CPU time | 827.01 seconds |
Started | Jun 27 06:50:38 PM PDT 24 |
Finished | Jun 27 07:04:29 PM PDT 24 |
Peak memory | 203500 kb |
Host | smart-e16d35a5-d83f-45a6-82a6-633a37bbc8fe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483894023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection. 483894023 |
Directory | /workspace/20.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_executable.3650226723 |
Short name | T578 |
Test name | |
Test status | |
Simulation time | 3431871954 ps |
CPU time | 210.14 seconds |
Started | Jun 27 06:50:35 PM PDT 24 |
Finished | Jun 27 06:54:08 PM PDT 24 |
Peak memory | 370528 kb |
Host | smart-7e6c31a5-3ff4-4bb5-ac05-b458e2776e2d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650226723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executab le.3650226723 |
Directory | /workspace/20.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_lc_escalation.841002298 |
Short name | T661 |
Test name | |
Test status | |
Simulation time | 8359955438 ps |
CPU time | 42.99 seconds |
Started | Jun 27 06:50:37 PM PDT 24 |
Finished | Jun 27 06:51:24 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-3cc8c5db-1a8b-4ece-9535-a650f382c68f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841002298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_esc alation.841002298 |
Directory | /workspace/20.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_max_throughput.1235738155 |
Short name | T707 |
Test name | |
Test status | |
Simulation time | 1309828152 ps |
CPU time | 6.4 seconds |
Started | Jun 27 06:50:36 PM PDT 24 |
Finished | Jun 27 06:50:46 PM PDT 24 |
Peak memory | 210856 kb |
Host | smart-7a198431-8810-4242-8cee-a3bf8bfe9b48 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235738155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 20.sram_ctrl_max_throughput.1235738155 |
Directory | /workspace/20.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_mem_partial_access.2833998914 |
Short name | T473 |
Test name | |
Test status | |
Simulation time | 24175625669 ps |
CPU time | 176.16 seconds |
Started | Jun 27 06:50:35 PM PDT 24 |
Finished | Jun 27 06:53:35 PM PDT 24 |
Peak memory | 219164 kb |
Host | smart-d6a5cddf-67de-4e30-998f-9ea6225e8146 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833998914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_mem_partial_access.2833998914 |
Directory | /workspace/20.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_mem_walk.1714069240 |
Short name | T904 |
Test name | |
Test status | |
Simulation time | 21009296816 ps |
CPU time | 326.11 seconds |
Started | Jun 27 06:50:37 PM PDT 24 |
Finished | Jun 27 06:56:08 PM PDT 24 |
Peak memory | 211012 kb |
Host | smart-6befd23d-c309-4508-b302-2a9178282863 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714069240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr l_mem_walk.1714069240 |
Directory | /workspace/20.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_multiple_keys.1570022646 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 38923114563 ps |
CPU time | 1109.54 seconds |
Started | Jun 27 06:50:37 PM PDT 24 |
Finished | Jun 27 07:09:12 PM PDT 24 |
Peak memory | 377700 kb |
Host | smart-5805b974-1974-4444-89e5-683ba371db34 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570022646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multi ple_keys.1570022646 |
Directory | /workspace/20.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_partial_access.4228292077 |
Short name | T570 |
Test name | |
Test status | |
Simulation time | 1037788558 ps |
CPU time | 61.16 seconds |
Started | Jun 27 06:50:35 PM PDT 24 |
Finished | Jun 27 06:51:40 PM PDT 24 |
Peak memory | 322280 kb |
Host | smart-1101fb0f-d6b0-41b6-a659-ca73602b06c9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228292077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20. sram_ctrl_partial_access.4228292077 |
Directory | /workspace/20.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.101695470 |
Short name | T496 |
Test name | |
Test status | |
Simulation time | 37982533084 ps |
CPU time | 239.11 seconds |
Started | Jun 27 06:50:38 PM PDT 24 |
Finished | Jun 27 06:54:42 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-7444b761-2e76-417b-b093-62eeb2e22e36 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101695470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 20.sram_ctrl_partial_access_b2b.101695470 |
Directory | /workspace/20.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_ram_cfg.3612590427 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 1354191334 ps |
CPU time | 3.73 seconds |
Started | Jun 27 06:50:36 PM PDT 24 |
Finished | Jun 27 06:50:44 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-95549a4e-8389-4254-8460-e9ff2bed889d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612590427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.3612590427 |
Directory | /workspace/20.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_regwen.1109978720 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 29032193974 ps |
CPU time | 427.13 seconds |
Started | Jun 27 06:50:36 PM PDT 24 |
Finished | Jun 27 06:57:47 PM PDT 24 |
Peak memory | 374680 kb |
Host | smart-506481d2-e4e2-4e21-a140-70be10e82576 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109978720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.1109978720 |
Directory | /workspace/20.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_smoke.4117587847 |
Short name | T935 |
Test name | |
Test status | |
Simulation time | 824298997 ps |
CPU time | 12.95 seconds |
Started | Jun 27 06:50:36 PM PDT 24 |
Finished | Jun 27 06:50:53 PM PDT 24 |
Peak memory | 202768 kb |
Host | smart-1ec23a9f-b448-4e51-9742-62972a38707e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117587847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.4117587847 |
Directory | /workspace/20.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_all.2149182737 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 542637243188 ps |
CPU time | 8073.9 seconds |
Started | Jun 27 06:50:36 PM PDT 24 |
Finished | Jun 27 09:05:14 PM PDT 24 |
Peak memory | 381992 kb |
Host | smart-66fe77e4-705e-4cad-9bf2-39a0eb046fc7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149182737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 20.sram_ctrl_stress_all.2149182737 |
Directory | /workspace/20.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_pipeline.1534216647 |
Short name | T787 |
Test name | |
Test status | |
Simulation time | 5476699695 ps |
CPU time | 191.72 seconds |
Started | Jun 27 06:50:36 PM PDT 24 |
Finished | Jun 27 06:53:51 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-6e5a216c-ea2e-42d3-aee2-995da2371cd1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534216647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_stress_pipeline.1534216647 |
Directory | /workspace/20.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.2240109249 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 1302345914 ps |
CPU time | 38.82 seconds |
Started | Jun 27 06:50:35 PM PDT 24 |
Finished | Jun 27 06:51:18 PM PDT 24 |
Peak memory | 288584 kb |
Host | smart-a96ecdc4-c6e1-4633-ae32-c1b59e6e6697 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240109249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.2240109249 |
Directory | /workspace/20.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_access_during_key_req.114259280 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 14509568468 ps |
CPU time | 1135.69 seconds |
Started | Jun 27 06:50:50 PM PDT 24 |
Finished | Jun 27 07:09:48 PM PDT 24 |
Peak memory | 380824 kb |
Host | smart-88d14ac0-32e7-4787-91ba-a38d4c897e36 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114259280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 21.sram_ctrl_access_during_key_req.114259280 |
Directory | /workspace/21.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_alert_test.4049424457 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 86976568 ps |
CPU time | 0.68 seconds |
Started | Jun 27 06:50:51 PM PDT 24 |
Finished | Jun 27 06:50:54 PM PDT 24 |
Peak memory | 202348 kb |
Host | smart-50c8c0fa-520d-48c6-9b63-3fa529a91359 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049424457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.4049424457 |
Directory | /workspace/21.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_bijection.3472382538 |
Short name | T885 |
Test name | |
Test status | |
Simulation time | 105203770203 ps |
CPU time | 1706.38 seconds |
Started | Jun 27 06:50:39 PM PDT 24 |
Finished | Jun 27 07:19:10 PM PDT 24 |
Peak memory | 202944 kb |
Host | smart-e6d6da40-b996-476a-8a0d-c64b529bcf31 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472382538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection .3472382538 |
Directory | /workspace/21.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_executable.1439991761 |
Short name | T516 |
Test name | |
Test status | |
Simulation time | 49189297703 ps |
CPU time | 1553.6 seconds |
Started | Jun 27 06:50:55 PM PDT 24 |
Finished | Jun 27 07:16:51 PM PDT 24 |
Peak memory | 379756 kb |
Host | smart-e4bd8916-48b4-4719-8a12-c3d38391c4a9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439991761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executab le.1439991761 |
Directory | /workspace/21.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_lc_escalation.2165326042 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 19287467895 ps |
CPU time | 56.28 seconds |
Started | Jun 27 06:50:51 PM PDT 24 |
Finished | Jun 27 06:51:50 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-c1a2d22f-b143-4179-ad8d-6d1b99fde05d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165326042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_es calation.2165326042 |
Directory | /workspace/21.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_max_throughput.3408091763 |
Short name | T634 |
Test name | |
Test status | |
Simulation time | 743712656 ps |
CPU time | 79.85 seconds |
Started | Jun 27 06:50:35 PM PDT 24 |
Finished | Jun 27 06:51:59 PM PDT 24 |
Peak memory | 317124 kb |
Host | smart-5f72cb2c-c882-4e00-b6cd-64d0dc7af48f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408091763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 21.sram_ctrl_max_throughput.3408091763 |
Directory | /workspace/21.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_mem_partial_access.318547721 |
Short name | T756 |
Test name | |
Test status | |
Simulation time | 20693256192 ps |
CPU time | 166.79 seconds |
Started | Jun 27 06:50:51 PM PDT 24 |
Finished | Jun 27 06:53:40 PM PDT 24 |
Peak memory | 211128 kb |
Host | smart-04d3ab24-ae26-4490-9a03-83e41da773b5 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318547721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21 .sram_ctrl_mem_partial_access.318547721 |
Directory | /workspace/21.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_mem_walk.770200344 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 5599876255 ps |
CPU time | 151.33 seconds |
Started | Jun 27 06:50:49 PM PDT 24 |
Finished | Jun 27 06:53:21 PM PDT 24 |
Peak memory | 211024 kb |
Host | smart-54d1cc55-1cab-41b9-958f-173644c5e610 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770200344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl _mem_walk.770200344 |
Directory | /workspace/21.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_multiple_keys.127516918 |
Short name | T674 |
Test name | |
Test status | |
Simulation time | 12870552588 ps |
CPU time | 911.79 seconds |
Started | Jun 27 06:50:37 PM PDT 24 |
Finished | Jun 27 07:05:53 PM PDT 24 |
Peak memory | 379460 kb |
Host | smart-9e711353-3755-4ade-9ba0-39412eee32e0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127516918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multip le_keys.127516918 |
Directory | /workspace/21.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_partial_access.2397631198 |
Short name | T647 |
Test name | |
Test status | |
Simulation time | 2993797276 ps |
CPU time | 26.25 seconds |
Started | Jun 27 06:50:37 PM PDT 24 |
Finished | Jun 27 06:51:07 PM PDT 24 |
Peak memory | 275944 kb |
Host | smart-f3cee722-b027-4895-9d20-70b88292cb6b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397631198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21. sram_ctrl_partial_access.2397631198 |
Directory | /workspace/21.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.3056320504 |
Short name | T686 |
Test name | |
Test status | |
Simulation time | 11639229292 ps |
CPU time | 278.17 seconds |
Started | Jun 27 06:50:37 PM PDT 24 |
Finished | Jun 27 06:55:19 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-d5454d2f-230d-4541-a6d5-a42aac28710f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056320504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 21.sram_ctrl_partial_access_b2b.3056320504 |
Directory | /workspace/21.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_ram_cfg.1890891745 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 1469350068 ps |
CPU time | 3.66 seconds |
Started | Jun 27 06:50:51 PM PDT 24 |
Finished | Jun 27 06:50:57 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-75d18078-0604-4fca-9d61-d3c42dafecd3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890891745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.1890891745 |
Directory | /workspace/21.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_regwen.2188514239 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 15927493217 ps |
CPU time | 808.23 seconds |
Started | Jun 27 06:50:50 PM PDT 24 |
Finished | Jun 27 07:04:20 PM PDT 24 |
Peak memory | 376656 kb |
Host | smart-bd9c134a-e481-4528-8a62-f7745d1941fc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188514239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.2188514239 |
Directory | /workspace/21.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_smoke.4105257404 |
Short name | T534 |
Test name | |
Test status | |
Simulation time | 7916087243 ps |
CPU time | 45.3 seconds |
Started | Jun 27 06:50:37 PM PDT 24 |
Finished | Jun 27 06:51:26 PM PDT 24 |
Peak memory | 291204 kb |
Host | smart-104545dd-1068-4850-957c-3cc809485e84 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105257404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.4105257404 |
Directory | /workspace/21.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_all.1476746852 |
Short name | T891 |
Test name | |
Test status | |
Simulation time | 29313772683 ps |
CPU time | 3411.36 seconds |
Started | Jun 27 06:50:53 PM PDT 24 |
Finished | Jun 27 07:47:48 PM PDT 24 |
Peak memory | 378748 kb |
Host | smart-67195d4b-3cf7-4a86-83a9-695849612fa4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476746852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 21.sram_ctrl_stress_all.1476746852 |
Directory | /workspace/21.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.1207497524 |
Short name | T606 |
Test name | |
Test status | |
Simulation time | 2226404451 ps |
CPU time | 171.24 seconds |
Started | Jun 27 06:50:51 PM PDT 24 |
Finished | Jun 27 06:53:44 PM PDT 24 |
Peak memory | 346112 kb |
Host | smart-00a37ed2-c5bd-4fb6-b2c8-0963d129f4c4 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1207497524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.1207497524 |
Directory | /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_pipeline.1183819687 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 12953738165 ps |
CPU time | 191.77 seconds |
Started | Jun 27 06:50:35 PM PDT 24 |
Finished | Jun 27 06:53:50 PM PDT 24 |
Peak memory | 203024 kb |
Host | smart-0c221b79-0d71-431e-8e3b-690c446c0164 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183819687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.sram_ctrl_stress_pipeline.1183819687 |
Directory | /workspace/21.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.3929323399 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 1602986999 ps |
CPU time | 179.77 seconds |
Started | Jun 27 06:50:51 PM PDT 24 |
Finished | Jun 27 06:53:54 PM PDT 24 |
Peak memory | 372504 kb |
Host | smart-680af2f9-c521-41d1-89a2-9f461b444754 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929323399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.3929323399 |
Directory | /workspace/21.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_access_during_key_req.2554701125 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 61998540909 ps |
CPU time | 898.25 seconds |
Started | Jun 27 06:50:54 PM PDT 24 |
Finished | Jun 27 07:05:56 PM PDT 24 |
Peak memory | 376724 kb |
Host | smart-3d4f83e6-0407-438d-b691-c24e6a84b90b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554701125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 22.sram_ctrl_access_during_key_req.2554701125 |
Directory | /workspace/22.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_alert_test.1025324205 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 14334621 ps |
CPU time | 0.65 seconds |
Started | Jun 27 06:50:51 PM PDT 24 |
Finished | Jun 27 06:50:54 PM PDT 24 |
Peak memory | 202560 kb |
Host | smart-94c03e3d-a667-4f4e-bae8-b92fd34d68a2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025324205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.1025324205 |
Directory | /workspace/22.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_bijection.1300226913 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 441680447300 ps |
CPU time | 1974.33 seconds |
Started | Jun 27 06:50:52 PM PDT 24 |
Finished | Jun 27 07:23:50 PM PDT 24 |
Peak memory | 203616 kb |
Host | smart-5350b3e3-5446-4a69-814b-19b686a2d566 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300226913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection .1300226913 |
Directory | /workspace/22.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_executable.3565719753 |
Short name | T714 |
Test name | |
Test status | |
Simulation time | 61497471520 ps |
CPU time | 966.76 seconds |
Started | Jun 27 06:50:54 PM PDT 24 |
Finished | Jun 27 07:07:04 PM PDT 24 |
Peak memory | 370568 kb |
Host | smart-a010598b-615a-448e-8d93-c710f130c61b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565719753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executab le.3565719753 |
Directory | /workspace/22.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_lc_escalation.2148882245 |
Short name | T471 |
Test name | |
Test status | |
Simulation time | 12574599346 ps |
CPU time | 66.8 seconds |
Started | Jun 27 06:50:53 PM PDT 24 |
Finished | Jun 27 06:52:03 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-1c5770ca-1c51-436c-809e-ce9d7e39706b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148882245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_es calation.2148882245 |
Directory | /workspace/22.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_max_throughput.2211356435 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 3181681861 ps |
CPU time | 177.65 seconds |
Started | Jun 27 06:50:55 PM PDT 24 |
Finished | Jun 27 06:53:55 PM PDT 24 |
Peak memory | 370740 kb |
Host | smart-deed9e66-3309-410c-8073-71669f11eb26 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211356435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 22.sram_ctrl_max_throughput.2211356435 |
Directory | /workspace/22.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_mem_partial_access.3600442641 |
Short name | T713 |
Test name | |
Test status | |
Simulation time | 2674534346 ps |
CPU time | 79.07 seconds |
Started | Jun 27 06:50:52 PM PDT 24 |
Finished | Jun 27 06:52:14 PM PDT 24 |
Peak memory | 211052 kb |
Host | smart-b29ec102-096b-4395-96f4-73e45057cdc4 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600442641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_mem_partial_access.3600442641 |
Directory | /workspace/22.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_mem_walk.2090968400 |
Short name | T517 |
Test name | |
Test status | |
Simulation time | 7397692303 ps |
CPU time | 310.2 seconds |
Started | Jun 27 06:50:52 PM PDT 24 |
Finished | Jun 27 06:56:06 PM PDT 24 |
Peak memory | 211032 kb |
Host | smart-03f3629a-5644-4017-85ed-8b3a64458b4d |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090968400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr l_mem_walk.2090968400 |
Directory | /workspace/22.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_multiple_keys.3954999246 |
Short name | T569 |
Test name | |
Test status | |
Simulation time | 12395803801 ps |
CPU time | 977.28 seconds |
Started | Jun 27 06:50:51 PM PDT 24 |
Finished | Jun 27 07:07:10 PM PDT 24 |
Peak memory | 372716 kb |
Host | smart-6286956b-1876-4c09-959e-67cd0d686754 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954999246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi ple_keys.3954999246 |
Directory | /workspace/22.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_partial_access.42254689 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 1580910475 ps |
CPU time | 58.74 seconds |
Started | Jun 27 06:50:52 PM PDT 24 |
Finished | Jun 27 06:51:54 PM PDT 24 |
Peak memory | 318280 kb |
Host | smart-3ce86be9-a420-4485-a5dc-1608092a7c07 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42254689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sr am_ctrl_partial_access.42254689 |
Directory | /workspace/22.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.841368478 |
Short name | T786 |
Test name | |
Test status | |
Simulation time | 45738045215 ps |
CPU time | 317.16 seconds |
Started | Jun 27 06:50:52 PM PDT 24 |
Finished | Jun 27 06:56:12 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-a2cdbb44-6915-49b4-bb18-28b62e9e9fc3 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841368478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 22.sram_ctrl_partial_access_b2b.841368478 |
Directory | /workspace/22.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_ram_cfg.4025622577 |
Short name | T458 |
Test name | |
Test status | |
Simulation time | 1300675288 ps |
CPU time | 3.43 seconds |
Started | Jun 27 06:50:53 PM PDT 24 |
Finished | Jun 27 06:51:00 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-d22d8130-0bc4-4923-b5c3-99fbed07328f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025622577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.4025622577 |
Directory | /workspace/22.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_regwen.2202065735 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 24709167708 ps |
CPU time | 1114.69 seconds |
Started | Jun 27 06:50:53 PM PDT 24 |
Finished | Jun 27 07:09:31 PM PDT 24 |
Peak memory | 377836 kb |
Host | smart-c41580df-d459-42f0-b5a1-1ddc7eba0527 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202065735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.2202065735 |
Directory | /workspace/22.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_smoke.1404450133 |
Short name | T868 |
Test name | |
Test status | |
Simulation time | 954559675 ps |
CPU time | 13.62 seconds |
Started | Jun 27 06:50:51 PM PDT 24 |
Finished | Jun 27 06:51:06 PM PDT 24 |
Peak memory | 248648 kb |
Host | smart-a28a7a20-465e-4d2d-9e21-38319e8e5c6d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404450133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.1404450133 |
Directory | /workspace/22.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_all.3360549462 |
Short name | T653 |
Test name | |
Test status | |
Simulation time | 690568539716 ps |
CPU time | 5464.28 seconds |
Started | Jun 27 06:50:52 PM PDT 24 |
Finished | Jun 27 08:22:00 PM PDT 24 |
Peak memory | 397416 kb |
Host | smart-8b748383-ef8a-4186-b023-c2d21ef569b7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360549462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 22.sram_ctrl_stress_all.3360549462 |
Directory | /workspace/22.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.2453618501 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 3888401905 ps |
CPU time | 29.1 seconds |
Started | Jun 27 06:50:53 PM PDT 24 |
Finished | Jun 27 06:51:25 PM PDT 24 |
Peak memory | 212196 kb |
Host | smart-93f8db28-c8a0-4ae9-8e19-d32ef54c326c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2453618501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.2453618501 |
Directory | /workspace/22.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_pipeline.4130377465 |
Short name | T747 |
Test name | |
Test status | |
Simulation time | 31170159708 ps |
CPU time | 331.37 seconds |
Started | Jun 27 06:50:52 PM PDT 24 |
Finished | Jun 27 06:56:26 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-686dd66a-994b-4a87-be3d-02566ee77069 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130377465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_stress_pipeline.4130377465 |
Directory | /workspace/22.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.3046486595 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 732820785 ps |
CPU time | 16.52 seconds |
Started | Jun 27 06:50:52 PM PDT 24 |
Finished | Jun 27 06:51:12 PM PDT 24 |
Peak memory | 251572 kb |
Host | smart-ed0e6058-337d-4c5b-a107-f777ffc32a45 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046486595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.3046486595 |
Directory | /workspace/22.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_access_during_key_req.2018381438 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 29159060989 ps |
CPU time | 993.04 seconds |
Started | Jun 27 06:51:12 PM PDT 24 |
Finished | Jun 27 07:07:53 PM PDT 24 |
Peak memory | 377952 kb |
Host | smart-fb911a5d-00b4-423c-a250-ab11099af52b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018381438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 23.sram_ctrl_access_during_key_req.2018381438 |
Directory | /workspace/23.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_alert_test.2309459112 |
Short name | T624 |
Test name | |
Test status | |
Simulation time | 12300517 ps |
CPU time | 0.68 seconds |
Started | Jun 27 06:51:05 PM PDT 24 |
Finished | Jun 27 06:51:14 PM PDT 24 |
Peak memory | 202572 kb |
Host | smart-9d833551-3cf7-4062-b42d-9e6a5163446b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309459112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.2309459112 |
Directory | /workspace/23.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_bijection.1773852330 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 72769153157 ps |
CPU time | 1143.72 seconds |
Started | Jun 27 06:51:06 PM PDT 24 |
Finished | Jun 27 07:10:17 PM PDT 24 |
Peak memory | 203460 kb |
Host | smart-4c644a93-7df6-479d-b18a-5a144d3e8a21 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773852330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection .1773852330 |
Directory | /workspace/23.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_executable.3807433667 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 93782954271 ps |
CPU time | 1604.55 seconds |
Started | Jun 27 06:51:05 PM PDT 24 |
Finished | Jun 27 07:17:57 PM PDT 24 |
Peak memory | 376592 kb |
Host | smart-dfd2b87b-b385-4b15-9342-4c26f1b771c4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807433667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab le.3807433667 |
Directory | /workspace/23.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_lc_escalation.1705862973 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 10711625909 ps |
CPU time | 64.39 seconds |
Started | Jun 27 06:51:04 PM PDT 24 |
Finished | Jun 27 06:52:14 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-8a5d6c21-65f6-4bc4-af3a-64fc623cb32f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705862973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_es calation.1705862973 |
Directory | /workspace/23.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_max_throughput.1088977610 |
Short name | T535 |
Test name | |
Test status | |
Simulation time | 1485221366 ps |
CPU time | 93.87 seconds |
Started | Jun 27 06:51:04 PM PDT 24 |
Finished | Jun 27 06:52:45 PM PDT 24 |
Peak memory | 329268 kb |
Host | smart-a4927f7a-e8ae-4147-bc9d-1519ffcf08a1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088977610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 23.sram_ctrl_max_throughput.1088977610 |
Directory | /workspace/23.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_mem_walk.3840976650 |
Short name | T598 |
Test name | |
Test status | |
Simulation time | 7049915752 ps |
CPU time | 169.11 seconds |
Started | Jun 27 06:51:04 PM PDT 24 |
Finished | Jun 27 06:53:59 PM PDT 24 |
Peak memory | 210992 kb |
Host | smart-76bfd0f7-b853-42f8-9dec-24231e38eb2b |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840976650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr l_mem_walk.3840976650 |
Directory | /workspace/23.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_multiple_keys.851125142 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 13747630960 ps |
CPU time | 854.55 seconds |
Started | Jun 27 06:50:53 PM PDT 24 |
Finished | Jun 27 07:05:11 PM PDT 24 |
Peak memory | 377732 kb |
Host | smart-efc509ff-23a1-46e8-9984-f432f7d72126 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851125142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multip le_keys.851125142 |
Directory | /workspace/23.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_partial_access.2250514880 |
Short name | T847 |
Test name | |
Test status | |
Simulation time | 424881904 ps |
CPU time | 24.17 seconds |
Started | Jun 27 06:51:11 PM PDT 24 |
Finished | Jun 27 06:51:43 PM PDT 24 |
Peak memory | 260868 kb |
Host | smart-f303d3fc-8b7a-4e2d-af56-8c04a04ba13d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250514880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23. sram_ctrl_partial_access.2250514880 |
Directory | /workspace/23.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.1470676391 |
Short name | T543 |
Test name | |
Test status | |
Simulation time | 16729195876 ps |
CPU time | 411.62 seconds |
Started | Jun 27 06:51:05 PM PDT 24 |
Finished | Jun 27 06:58:03 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-cde12ad5-c51f-41f5-8572-5c49ef1d3862 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470676391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 23.sram_ctrl_partial_access_b2b.1470676391 |
Directory | /workspace/23.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_ram_cfg.2127041285 |
Short name | T925 |
Test name | |
Test status | |
Simulation time | 355314740 ps |
CPU time | 3.34 seconds |
Started | Jun 27 06:51:11 PM PDT 24 |
Finished | Jun 27 06:51:22 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-61c41441-04e5-4030-843a-6b224215f287 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127041285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.2127041285 |
Directory | /workspace/23.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_regwen.3914287374 |
Short name | T886 |
Test name | |
Test status | |
Simulation time | 14447310447 ps |
CPU time | 1154.15 seconds |
Started | Jun 27 06:51:07 PM PDT 24 |
Finished | Jun 27 07:10:29 PM PDT 24 |
Peak memory | 382880 kb |
Host | smart-c9f4f7d9-6041-4fc2-9518-9e699a39d01f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914287374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.3914287374 |
Directory | /workspace/23.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_smoke.2976568397 |
Short name | T659 |
Test name | |
Test status | |
Simulation time | 3013662305 ps |
CPU time | 80.04 seconds |
Started | Jun 27 06:50:53 PM PDT 24 |
Finished | Jun 27 06:52:16 PM PDT 24 |
Peak memory | 312484 kb |
Host | smart-0a5bacfd-80d7-4b7d-9aeb-53b3583b5adf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976568397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.2976568397 |
Directory | /workspace/23.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_all.3195089553 |
Short name | T618 |
Test name | |
Test status | |
Simulation time | 169527910610 ps |
CPU time | 4049.28 seconds |
Started | Jun 27 06:51:05 PM PDT 24 |
Finished | Jun 27 07:58:42 PM PDT 24 |
Peak memory | 386952 kb |
Host | smart-3948d6a3-710e-4786-a8b4-1bb72bc35b17 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195089553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 23.sram_ctrl_stress_all.3195089553 |
Directory | /workspace/23.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3641176371 |
Short name | T872 |
Test name | |
Test status | |
Simulation time | 7150468599 ps |
CPU time | 57.77 seconds |
Started | Jun 27 06:51:06 PM PDT 24 |
Finished | Jun 27 06:52:12 PM PDT 24 |
Peak memory | 211184 kb |
Host | smart-304b46a3-4fbd-4308-9a65-2fb6612bf3ca |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3641176371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.3641176371 |
Directory | /workspace/23.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_pipeline.3862697310 |
Short name | T565 |
Test name | |
Test status | |
Simulation time | 5660826696 ps |
CPU time | 244.17 seconds |
Started | Jun 27 06:51:05 PM PDT 24 |
Finished | Jun 27 06:55:16 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-003d465c-3b49-4bf3-a069-bf596a6112d3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862697310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_stress_pipeline.3862697310 |
Directory | /workspace/23.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.2616697942 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 9182142176 ps |
CPU time | 60.25 seconds |
Started | Jun 27 06:51:05 PM PDT 24 |
Finished | Jun 27 06:52:13 PM PDT 24 |
Peak memory | 300984 kb |
Host | smart-409a0508-259b-4548-92c4-a5fddfa24209 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616697942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.2616697942 |
Directory | /workspace/23.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_access_during_key_req.1742753671 |
Short name | T603 |
Test name | |
Test status | |
Simulation time | 22283974315 ps |
CPU time | 1177.16 seconds |
Started | Jun 27 06:51:11 PM PDT 24 |
Finished | Jun 27 07:10:56 PM PDT 24 |
Peak memory | 379752 kb |
Host | smart-a621dd27-00f5-4f80-8290-da56023857ac |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742753671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 24.sram_ctrl_access_during_key_req.1742753671 |
Directory | /workspace/24.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_alert_test.775870757 |
Short name | T588 |
Test name | |
Test status | |
Simulation time | 85583768 ps |
CPU time | 0.76 seconds |
Started | Jun 27 06:51:17 PM PDT 24 |
Finished | Jun 27 06:51:23 PM PDT 24 |
Peak memory | 202780 kb |
Host | smart-206f7efa-0093-42d6-872c-e39f0e821ff4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775870757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.775870757 |
Directory | /workspace/24.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_bijection.3688987297 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 150846701105 ps |
CPU time | 2345.81 seconds |
Started | Jun 27 06:51:07 PM PDT 24 |
Finished | Jun 27 07:30:21 PM PDT 24 |
Peak memory | 202980 kb |
Host | smart-5b8c53a4-b3a8-4832-9ba7-a2c6ba27459a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688987297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection .3688987297 |
Directory | /workspace/24.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_executable.1920311622 |
Short name | T777 |
Test name | |
Test status | |
Simulation time | 33060210112 ps |
CPU time | 838.13 seconds |
Started | Jun 27 06:51:06 PM PDT 24 |
Finished | Jun 27 07:05:12 PM PDT 24 |
Peak memory | 379740 kb |
Host | smart-b2ea19ea-4d5e-46f3-bfa9-b259f453c3d5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920311622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executab le.1920311622 |
Directory | /workspace/24.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_lc_escalation.3804635939 |
Short name | T743 |
Test name | |
Test status | |
Simulation time | 17862043867 ps |
CPU time | 57.94 seconds |
Started | Jun 27 06:51:04 PM PDT 24 |
Finished | Jun 27 06:52:09 PM PDT 24 |
Peak memory | 211108 kb |
Host | smart-2682131a-e5b9-43c9-9bd9-f887637b5659 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804635939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_es calation.3804635939 |
Directory | /workspace/24.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_max_throughput.2498691961 |
Short name | T757 |
Test name | |
Test status | |
Simulation time | 796516544 ps |
CPU time | 126.97 seconds |
Started | Jun 27 06:51:08 PM PDT 24 |
Finished | Jun 27 06:53:23 PM PDT 24 |
Peak memory | 355036 kb |
Host | smart-4da4c9fd-ae3c-4c27-8ec4-6f13ca440740 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498691961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 24.sram_ctrl_max_throughput.2498691961 |
Directory | /workspace/24.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_mem_partial_access.1845270111 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 2799272951 ps |
CPU time | 89.75 seconds |
Started | Jun 27 06:51:05 PM PDT 24 |
Finished | Jun 27 06:52:43 PM PDT 24 |
Peak memory | 219052 kb |
Host | smart-ef9eb6f9-ddda-4992-9f6c-c484790d8136 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845270111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_mem_partial_access.1845270111 |
Directory | /workspace/24.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_mem_walk.2656998745 |
Short name | T770 |
Test name | |
Test status | |
Simulation time | 20733342645 ps |
CPU time | 252.88 seconds |
Started | Jun 27 06:51:12 PM PDT 24 |
Finished | Jun 27 06:55:32 PM PDT 24 |
Peak memory | 211024 kb |
Host | smart-95c45486-b29b-4ff9-920e-667f2d311c06 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656998745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctr l_mem_walk.2656998745 |
Directory | /workspace/24.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_multiple_keys.124314225 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 1613720737 ps |
CPU time | 62.41 seconds |
Started | Jun 27 06:51:06 PM PDT 24 |
Finished | Jun 27 06:52:17 PM PDT 24 |
Peak memory | 280220 kb |
Host | smart-33435287-dcb7-4b5e-a1c4-06310661a339 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124314225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multip le_keys.124314225 |
Directory | /workspace/24.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_partial_access.3519960597 |
Short name | T828 |
Test name | |
Test status | |
Simulation time | 799621397 ps |
CPU time | 14.2 seconds |
Started | Jun 27 06:51:05 PM PDT 24 |
Finished | Jun 27 06:51:26 PM PDT 24 |
Peak memory | 231324 kb |
Host | smart-1c7abc38-32c3-482c-ba38-dcb1f619d843 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519960597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24. sram_ctrl_partial_access.3519960597 |
Directory | /workspace/24.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.847483714 |
Short name | T850 |
Test name | |
Test status | |
Simulation time | 53603148418 ps |
CPU time | 298.12 seconds |
Started | Jun 27 06:51:08 PM PDT 24 |
Finished | Jun 27 06:56:14 PM PDT 24 |
Peak memory | 202828 kb |
Host | smart-ace2225c-da2d-4a7a-aeee-1cc711bd468d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847483714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 24.sram_ctrl_partial_access_b2b.847483714 |
Directory | /workspace/24.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_ram_cfg.2226718433 |
Short name | T759 |
Test name | |
Test status | |
Simulation time | 345729264 ps |
CPU time | 3.07 seconds |
Started | Jun 27 06:51:06 PM PDT 24 |
Finished | Jun 27 06:51:17 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-b6d7ba36-1ad5-494f-bfed-feafdc440b43 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226718433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.2226718433 |
Directory | /workspace/24.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_regwen.2431445905 |
Short name | T562 |
Test name | |
Test status | |
Simulation time | 7092476391 ps |
CPU time | 184.74 seconds |
Started | Jun 27 06:51:04 PM PDT 24 |
Finished | Jun 27 06:54:15 PM PDT 24 |
Peak memory | 355712 kb |
Host | smart-331114eb-5548-4de8-b040-f22ebfe85197 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431445905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.2431445905 |
Directory | /workspace/24.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_smoke.754771586 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 1696427858 ps |
CPU time | 15.63 seconds |
Started | Jun 27 06:51:05 PM PDT 24 |
Finished | Jun 27 06:51:28 PM PDT 24 |
Peak memory | 202772 kb |
Host | smart-d2b9e9a3-2f1a-4d9b-9467-9c50e1b3175e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754771586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.754771586 |
Directory | /workspace/24.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_all.1087016754 |
Short name | T504 |
Test name | |
Test status | |
Simulation time | 178448804769 ps |
CPU time | 1730.44 seconds |
Started | Jun 27 06:51:23 PM PDT 24 |
Finished | Jun 27 07:20:16 PM PDT 24 |
Peak memory | 379716 kb |
Host | smart-6e9245ec-edaa-4251-9052-ec98fead5559 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087016754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 24.sram_ctrl_stress_all.1087016754 |
Directory | /workspace/24.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3478781030 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 206406963 ps |
CPU time | 10.36 seconds |
Started | Jun 27 06:51:17 PM PDT 24 |
Finished | Jun 27 06:51:32 PM PDT 24 |
Peak memory | 211008 kb |
Host | smart-5a1ec563-8cef-410b-9bbc-34eef6d453f1 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3478781030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.3478781030 |
Directory | /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_pipeline.3771240007 |
Short name | T584 |
Test name | |
Test status | |
Simulation time | 17814409300 ps |
CPU time | 341.48 seconds |
Started | Jun 27 06:51:04 PM PDT 24 |
Finished | Jun 27 06:56:52 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-71b44e88-6d52-424a-9355-f4560b83cca6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771240007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_stress_pipeline.3771240007 |
Directory | /workspace/24.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.2991306819 |
Short name | T605 |
Test name | |
Test status | |
Simulation time | 783673170 ps |
CPU time | 53.06 seconds |
Started | Jun 27 06:51:06 PM PDT 24 |
Finished | Jun 27 06:52:07 PM PDT 24 |
Peak memory | 300924 kb |
Host | smart-f87c122c-4ce9-49f7-9fc7-85ac4784cfbb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991306819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.2991306819 |
Directory | /workspace/24.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_access_during_key_req.2279387779 |
Short name | T663 |
Test name | |
Test status | |
Simulation time | 15096195176 ps |
CPU time | 648.33 seconds |
Started | Jun 27 06:51:18 PM PDT 24 |
Finished | Jun 27 07:02:11 PM PDT 24 |
Peak memory | 379848 kb |
Host | smart-e442f3cb-e192-4284-93ad-bef76853be5e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279387779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 25.sram_ctrl_access_during_key_req.2279387779 |
Directory | /workspace/25.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_alert_test.4250719515 |
Short name | T882 |
Test name | |
Test status | |
Simulation time | 37015560 ps |
CPU time | 0.67 seconds |
Started | Jun 27 06:51:37 PM PDT 24 |
Finished | Jun 27 06:51:41 PM PDT 24 |
Peak memory | 202512 kb |
Host | smart-fc505956-72cf-4613-aaa0-cfcad33babf7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250719515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.4250719515 |
Directory | /workspace/25.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_bijection.2394224053 |
Short name | T669 |
Test name | |
Test status | |
Simulation time | 340172954645 ps |
CPU time | 1517.84 seconds |
Started | Jun 27 06:51:15 PM PDT 24 |
Finished | Jun 27 07:16:39 PM PDT 24 |
Peak memory | 203512 kb |
Host | smart-e51ab533-eda6-465f-840d-1e24ef1232e1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394224053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection .2394224053 |
Directory | /workspace/25.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_executable.266417787 |
Short name | T908 |
Test name | |
Test status | |
Simulation time | 48148227035 ps |
CPU time | 1474.69 seconds |
Started | Jun 27 06:51:18 PM PDT 24 |
Finished | Jun 27 07:15:57 PM PDT 24 |
Peak memory | 375692 kb |
Host | smart-df47197c-024f-4d49-8418-e9f12ca8ff27 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266417787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executabl e.266417787 |
Directory | /workspace/25.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_lc_escalation.3997833390 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 22338093987 ps |
CPU time | 74.58 seconds |
Started | Jun 27 06:51:18 PM PDT 24 |
Finished | Jun 27 06:52:38 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-e42740e1-e06e-480a-8146-c27f14ee8ae2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997833390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_es calation.3997833390 |
Directory | /workspace/25.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_max_throughput.988388630 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 680476063 ps |
CPU time | 5.99 seconds |
Started | Jun 27 06:51:23 PM PDT 24 |
Finished | Jun 27 06:51:31 PM PDT 24 |
Peak memory | 210916 kb |
Host | smart-b72d5830-0fe2-4a1c-9a95-42dd2f1fb578 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988388630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 25.sram_ctrl_max_throughput.988388630 |
Directory | /workspace/25.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_mem_partial_access.3766230583 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 9428821946 ps |
CPU time | 82.96 seconds |
Started | Jun 27 06:51:29 PM PDT 24 |
Finished | Jun 27 06:52:54 PM PDT 24 |
Peak memory | 211072 kb |
Host | smart-6b5c1132-20e6-4f8d-b242-6d2db2c61874 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766230583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_mem_partial_access.3766230583 |
Directory | /workspace/25.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_mem_walk.3339841544 |
Short name | T616 |
Test name | |
Test status | |
Simulation time | 3955540294 ps |
CPU time | 133.32 seconds |
Started | Jun 27 06:51:29 PM PDT 24 |
Finished | Jun 27 06:53:45 PM PDT 24 |
Peak memory | 203052 kb |
Host | smart-5ac50f4b-1c7e-477e-8ba2-d1d9e854fc09 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339841544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr l_mem_walk.3339841544 |
Directory | /workspace/25.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_multiple_keys.1972775390 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 5618078938 ps |
CPU time | 122.97 seconds |
Started | Jun 27 06:51:18 PM PDT 24 |
Finished | Jun 27 06:53:26 PM PDT 24 |
Peak memory | 323700 kb |
Host | smart-cb8fb0dd-a0cc-45e7-bba7-4433ab18cb48 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972775390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi ple_keys.1972775390 |
Directory | /workspace/25.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_partial_access.3129806203 |
Short name | T632 |
Test name | |
Test status | |
Simulation time | 1473034687 ps |
CPU time | 22.43 seconds |
Started | Jun 27 06:51:18 PM PDT 24 |
Finished | Jun 27 06:51:45 PM PDT 24 |
Peak memory | 202700 kb |
Host | smart-23c3e174-8012-4e74-b72a-17b85272815c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129806203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25. sram_ctrl_partial_access.3129806203 |
Directory | /workspace/25.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3019231600 |
Short name | T541 |
Test name | |
Test status | |
Simulation time | 7017817980 ps |
CPU time | 409.56 seconds |
Started | Jun 27 06:51:19 PM PDT 24 |
Finished | Jun 27 06:58:13 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-8b00b485-ddd8-4633-8fce-c2c16287ec1e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019231600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 25.sram_ctrl_partial_access_b2b.3019231600 |
Directory | /workspace/25.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_ram_cfg.4178111402 |
Short name | T738 |
Test name | |
Test status | |
Simulation time | 356899863 ps |
CPU time | 3.26 seconds |
Started | Jun 27 06:51:39 PM PDT 24 |
Finished | Jun 27 06:51:45 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-b7edcc5b-26c9-4307-8e5b-e1207526a5a9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178111402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.4178111402 |
Directory | /workspace/25.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_regwen.3456630094 |
Short name | T683 |
Test name | |
Test status | |
Simulation time | 3388260746 ps |
CPU time | 554.77 seconds |
Started | Jun 27 06:52:35 PM PDT 24 |
Finished | Jun 27 07:01:53 PM PDT 24 |
Peak memory | 365336 kb |
Host | smart-3d36c8ff-8058-4da9-b18e-04a8d54ed6bd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456630094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.3456630094 |
Directory | /workspace/25.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_smoke.598369524 |
Short name | T774 |
Test name | |
Test status | |
Simulation time | 358192045 ps |
CPU time | 7.26 seconds |
Started | Jun 27 06:51:23 PM PDT 24 |
Finished | Jun 27 06:51:32 PM PDT 24 |
Peak memory | 223352 kb |
Host | smart-dc87a454-a3fd-41aa-9a55-00fb61f8f48f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598369524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.598369524 |
Directory | /workspace/25.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_all.1643703586 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 85651286052 ps |
CPU time | 2408.45 seconds |
Started | Jun 27 06:51:30 PM PDT 24 |
Finished | Jun 27 07:31:40 PM PDT 24 |
Peak memory | 368488 kb |
Host | smart-f1d4ac29-4989-434d-9fae-00cba9b6ef38 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643703586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 25.sram_ctrl_stress_all.1643703586 |
Directory | /workspace/25.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2553170022 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 323045642 ps |
CPU time | 6.83 seconds |
Started | Jun 27 06:51:29 PM PDT 24 |
Finished | Jun 27 06:51:37 PM PDT 24 |
Peak memory | 211104 kb |
Host | smart-7a30c0a5-f06f-4750-80b0-a083a4e6a19a |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2553170022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.2553170022 |
Directory | /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_pipeline.1181680892 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 10176071839 ps |
CPU time | 407.23 seconds |
Started | Jun 27 06:51:18 PM PDT 24 |
Finished | Jun 27 06:58:10 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-0f31c7e4-7beb-458f-9be0-459d0db9e5d6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181680892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_stress_pipeline.1181680892 |
Directory | /workspace/25.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.1359539675 |
Short name | T760 |
Test name | |
Test status | |
Simulation time | 751738184 ps |
CPU time | 80.7 seconds |
Started | Jun 27 06:51:17 PM PDT 24 |
Finished | Jun 27 06:52:43 PM PDT 24 |
Peak memory | 317292 kb |
Host | smart-f0e00bfd-dacb-4505-bffa-c23d356927aa |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359539675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.1359539675 |
Directory | /workspace/25.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_access_during_key_req.1106413571 |
Short name | T736 |
Test name | |
Test status | |
Simulation time | 16346630326 ps |
CPU time | 1239.31 seconds |
Started | Jun 27 06:51:31 PM PDT 24 |
Finished | Jun 27 07:12:12 PM PDT 24 |
Peak memory | 380100 kb |
Host | smart-4113aee8-73ce-41e2-b417-7ace06f3279f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106413571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 26.sram_ctrl_access_during_key_req.1106413571 |
Directory | /workspace/26.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_alert_test.2650898943 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 38826968 ps |
CPU time | 0.67 seconds |
Started | Jun 27 06:51:42 PM PDT 24 |
Finished | Jun 27 06:51:46 PM PDT 24 |
Peak memory | 202400 kb |
Host | smart-397ebbfb-664b-47ed-8f5c-209f56227496 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650898943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.2650898943 |
Directory | /workspace/26.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_bijection.1670209448 |
Short name | T851 |
Test name | |
Test status | |
Simulation time | 508082755892 ps |
CPU time | 2206.89 seconds |
Started | Jun 27 06:51:29 PM PDT 24 |
Finished | Jun 27 07:28:18 PM PDT 24 |
Peak memory | 203428 kb |
Host | smart-3bdf9c92-bab6-45d8-8ffd-612da252bc40 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670209448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection .1670209448 |
Directory | /workspace/26.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_executable.3767120001 |
Short name | T881 |
Test name | |
Test status | |
Simulation time | 48517322042 ps |
CPU time | 691.83 seconds |
Started | Jun 27 06:51:28 PM PDT 24 |
Finished | Jun 27 07:03:01 PM PDT 24 |
Peak memory | 357376 kb |
Host | smart-95e405a5-24ab-4e61-af3d-4d059a6f5de3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767120001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executab le.3767120001 |
Directory | /workspace/26.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_lc_escalation.643214780 |
Short name | T796 |
Test name | |
Test status | |
Simulation time | 8462006127 ps |
CPU time | 52.92 seconds |
Started | Jun 27 06:51:37 PM PDT 24 |
Finished | Jun 27 06:52:33 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-040f484e-4022-4c6e-9ce0-20ae50f4542d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643214780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_esc alation.643214780 |
Directory | /workspace/26.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_max_throughput.2292386242 |
Short name | T730 |
Test name | |
Test status | |
Simulation time | 1375003459 ps |
CPU time | 33.77 seconds |
Started | Jun 27 06:51:29 PM PDT 24 |
Finished | Jun 27 06:52:05 PM PDT 24 |
Peak memory | 279548 kb |
Host | smart-e3c77e5a-724b-4386-be47-ddf2f47ca075 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292386242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 26.sram_ctrl_max_throughput.2292386242 |
Directory | /workspace/26.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_mem_partial_access.261355117 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 4479656143 ps |
CPU time | 151.41 seconds |
Started | Jun 27 06:51:42 PM PDT 24 |
Finished | Jun 27 06:54:17 PM PDT 24 |
Peak memory | 211080 kb |
Host | smart-cfa75231-ffaf-42dd-a670-49b152731672 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261355117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26 .sram_ctrl_mem_partial_access.261355117 |
Directory | /workspace/26.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_mem_walk.3565418991 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 79558925276 ps |
CPU time | 189.69 seconds |
Started | Jun 27 06:51:28 PM PDT 24 |
Finished | Jun 27 06:54:40 PM PDT 24 |
Peak memory | 211684 kb |
Host | smart-6be686bd-a391-4921-b4ac-5b617491a5b7 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565418991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr l_mem_walk.3565418991 |
Directory | /workspace/26.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_multiple_keys.4137014750 |
Short name | T873 |
Test name | |
Test status | |
Simulation time | 3588978048 ps |
CPU time | 113.32 seconds |
Started | Jun 27 06:51:30 PM PDT 24 |
Finished | Jun 27 06:53:25 PM PDT 24 |
Peak memory | 284668 kb |
Host | smart-38d283d0-db62-40ba-9ecd-3563b5401262 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137014750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi ple_keys.4137014750 |
Directory | /workspace/26.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_partial_access.2980801718 |
Short name | T798 |
Test name | |
Test status | |
Simulation time | 598519544 ps |
CPU time | 18.28 seconds |
Started | Jun 27 06:51:31 PM PDT 24 |
Finished | Jun 27 06:51:51 PM PDT 24 |
Peak memory | 202724 kb |
Host | smart-38bd1cd4-ff2f-48b1-aa93-8184d5e2a630 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980801718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26. sram_ctrl_partial_access.2980801718 |
Directory | /workspace/26.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.586374873 |
Short name | T655 |
Test name | |
Test status | |
Simulation time | 12801672344 ps |
CPU time | 332.98 seconds |
Started | Jun 27 06:51:36 PM PDT 24 |
Finished | Jun 27 06:57:10 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-e513f1ed-7434-41d4-b91b-66e1669f42ef |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586374873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 26.sram_ctrl_partial_access_b2b.586374873 |
Directory | /workspace/26.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_ram_cfg.127098749 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 1413475531 ps |
CPU time | 3.87 seconds |
Started | Jun 27 06:51:40 PM PDT 24 |
Finished | Jun 27 06:51:46 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-75be4c4a-1908-4a94-88d2-49c63282a4c5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127098749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.127098749 |
Directory | /workspace/26.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_regwen.3663290854 |
Short name | T695 |
Test name | |
Test status | |
Simulation time | 21993862541 ps |
CPU time | 1027.36 seconds |
Started | Jun 27 06:51:30 PM PDT 24 |
Finished | Jun 27 07:08:40 PM PDT 24 |
Peak memory | 377704 kb |
Host | smart-442bfc8d-4a31-490f-9ea2-fa7be796d34f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663290854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.3663290854 |
Directory | /workspace/26.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_smoke.2417399359 |
Short name | T572 |
Test name | |
Test status | |
Simulation time | 971597384 ps |
CPU time | 160.11 seconds |
Started | Jun 27 06:51:30 PM PDT 24 |
Finished | Jun 27 06:54:12 PM PDT 24 |
Peak memory | 370404 kb |
Host | smart-ac287b1e-d748-462a-aee0-e8740f881bed |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417399359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.2417399359 |
Directory | /workspace/26.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_all.1765925624 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 48358925045 ps |
CPU time | 6170.06 seconds |
Started | Jun 27 06:51:42 PM PDT 24 |
Finished | Jun 27 08:34:37 PM PDT 24 |
Peak memory | 386964 kb |
Host | smart-fc551018-8d9e-41a7-9aa7-b2fb763b629f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765925624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 26.sram_ctrl_stress_all.1765925624 |
Directory | /workspace/26.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3677570794 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 408275609 ps |
CPU time | 12.61 seconds |
Started | Jun 27 06:51:44 PM PDT 24 |
Finished | Jun 27 06:51:59 PM PDT 24 |
Peak memory | 211172 kb |
Host | smart-f700cffb-4632-452b-982e-5752f3a599c2 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3677570794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.3677570794 |
Directory | /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_pipeline.3955238773 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 3734449199 ps |
CPU time | 223.13 seconds |
Started | Jun 27 06:51:29 PM PDT 24 |
Finished | Jun 27 06:55:14 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-dc400610-4543-4c5b-a73d-a040d0f5d001 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955238773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.sram_ctrl_stress_pipeline.3955238773 |
Directory | /workspace/26.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.1694995491 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 745487119 ps |
CPU time | 29.99 seconds |
Started | Jun 27 06:52:48 PM PDT 24 |
Finished | Jun 27 06:53:21 PM PDT 24 |
Peak memory | 300568 kb |
Host | smart-8a1750c4-d7c8-4729-a6a3-256b47639872 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694995491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.1694995491 |
Directory | /workspace/26.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_access_during_key_req.3216785356 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 4643673634 ps |
CPU time | 130.69 seconds |
Started | Jun 27 06:51:42 PM PDT 24 |
Finished | Jun 27 06:53:56 PM PDT 24 |
Peak memory | 314252 kb |
Host | smart-e4885364-cd95-4427-ba41-b0843fefb673 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216785356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 27.sram_ctrl_access_during_key_req.3216785356 |
Directory | /workspace/27.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_alert_test.886530347 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 12538259 ps |
CPU time | 0.67 seconds |
Started | Jun 27 06:51:56 PM PDT 24 |
Finished | Jun 27 06:51:58 PM PDT 24 |
Peak memory | 202560 kb |
Host | smart-aad256a4-df6c-4e76-83e0-73660a69b6ee |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886530347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.886530347 |
Directory | /workspace/27.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_bijection.3121853898 |
Short name | T481 |
Test name | |
Test status | |
Simulation time | 356618660619 ps |
CPU time | 1748.22 seconds |
Started | Jun 27 06:51:42 PM PDT 24 |
Finished | Jun 27 07:20:54 PM PDT 24 |
Peak memory | 202996 kb |
Host | smart-4d88c435-0117-4ed6-9013-11723f9bae49 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121853898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection .3121853898 |
Directory | /workspace/27.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_executable.1920681454 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 6758453349 ps |
CPU time | 945.73 seconds |
Started | Jun 27 06:51:44 PM PDT 24 |
Finished | Jun 27 07:07:33 PM PDT 24 |
Peak memory | 375652 kb |
Host | smart-29054015-e8c7-4d75-8659-a1130c3eccac |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920681454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executab le.1920681454 |
Directory | /workspace/27.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_lc_escalation.736593869 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 18653130354 ps |
CPU time | 65.09 seconds |
Started | Jun 27 06:51:43 PM PDT 24 |
Finished | Jun 27 06:52:51 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-ac28a425-57f7-475e-ab83-d02e0f72d9fd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736593869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_esc alation.736593869 |
Directory | /workspace/27.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_max_throughput.1282722496 |
Short name | T594 |
Test name | |
Test status | |
Simulation time | 704839021 ps |
CPU time | 18.53 seconds |
Started | Jun 27 06:51:43 PM PDT 24 |
Finished | Jun 27 06:52:05 PM PDT 24 |
Peak memory | 251800 kb |
Host | smart-a004c8e8-bf0a-4d92-942e-dbd5f9b77150 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282722496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 27.sram_ctrl_max_throughput.1282722496 |
Directory | /workspace/27.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_mem_partial_access.647834952 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 2885576645 ps |
CPU time | 68.84 seconds |
Started | Jun 27 06:51:43 PM PDT 24 |
Finished | Jun 27 06:52:55 PM PDT 24 |
Peak memory | 211020 kb |
Host | smart-164a5903-a761-49e8-bc0f-1697eb491905 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647834952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27 .sram_ctrl_mem_partial_access.647834952 |
Directory | /workspace/27.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_mem_walk.710340043 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 41295953021 ps |
CPU time | 185.27 seconds |
Started | Jun 27 06:51:41 PM PDT 24 |
Finished | Jun 27 06:54:50 PM PDT 24 |
Peak memory | 211032 kb |
Host | smart-a5ea70ad-3c4e-4538-a2fb-2574bc7ae5c5 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710340043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl _mem_walk.710340043 |
Directory | /workspace/27.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_multiple_keys.872820559 |
Short name | T698 |
Test name | |
Test status | |
Simulation time | 23427291912 ps |
CPU time | 357.46 seconds |
Started | Jun 27 06:51:41 PM PDT 24 |
Finished | Jun 27 06:57:42 PM PDT 24 |
Peak memory | 345316 kb |
Host | smart-675e2eca-e698-4986-8e6c-c65f450b787d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872820559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multip le_keys.872820559 |
Directory | /workspace/27.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_partial_access.630692114 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 3726225305 ps |
CPU time | 18.05 seconds |
Started | Jun 27 06:51:43 PM PDT 24 |
Finished | Jun 27 06:52:04 PM PDT 24 |
Peak memory | 203060 kb |
Host | smart-e7907cf9-4187-4db4-a861-6dc163115bc4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630692114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.s ram_ctrl_partial_access.630692114 |
Directory | /workspace/27.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2458277580 |
Short name | T479 |
Test name | |
Test status | |
Simulation time | 16458976639 ps |
CPU time | 381.09 seconds |
Started | Jun 27 06:51:41 PM PDT 24 |
Finished | Jun 27 06:58:06 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-87cff855-bbc8-491b-a412-d9358c7c7c4e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458277580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 27.sram_ctrl_partial_access_b2b.2458277580 |
Directory | /workspace/27.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_ram_cfg.249707443 |
Short name | T735 |
Test name | |
Test status | |
Simulation time | 1414388507 ps |
CPU time | 3.11 seconds |
Started | Jun 27 06:52:48 PM PDT 24 |
Finished | Jun 27 06:52:54 PM PDT 24 |
Peak memory | 202468 kb |
Host | smart-7ecc39f6-eeba-49e2-8453-4e637416d085 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249707443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.249707443 |
Directory | /workspace/27.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_regwen.3038222597 |
Short name | T780 |
Test name | |
Test status | |
Simulation time | 7640648257 ps |
CPU time | 1314.14 seconds |
Started | Jun 27 06:51:42 PM PDT 24 |
Finished | Jun 27 07:13:40 PM PDT 24 |
Peak memory | 380820 kb |
Host | smart-280b23cd-def8-4a9e-ac42-65e14bca8e43 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038222597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.3038222597 |
Directory | /workspace/27.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_smoke.2936708224 |
Short name | T767 |
Test name | |
Test status | |
Simulation time | 722140705 ps |
CPU time | 8.72 seconds |
Started | Jun 27 06:51:41 PM PDT 24 |
Finished | Jun 27 06:51:53 PM PDT 24 |
Peak memory | 202768 kb |
Host | smart-da486b83-0eeb-42cb-ae50-068b29d347e5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936708224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.2936708224 |
Directory | /workspace/27.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1116772795 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 1359761879 ps |
CPU time | 6.25 seconds |
Started | Jun 27 06:51:42 PM PDT 24 |
Finished | Jun 27 06:51:51 PM PDT 24 |
Peak memory | 211048 kb |
Host | smart-144b9bc7-8c5f-4c0d-a34d-6d011ff8ce91 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1116772795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.1116772795 |
Directory | /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_pipeline.3757618606 |
Short name | T822 |
Test name | |
Test status | |
Simulation time | 3601909224 ps |
CPU time | 110.5 seconds |
Started | Jun 27 06:51:41 PM PDT 24 |
Finished | Jun 27 06:53:35 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-cec679c7-a515-40b8-9fac-f1c07092966d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757618606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_stress_pipeline.3757618606 |
Directory | /workspace/27.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.63689011 |
Short name | T775 |
Test name | |
Test status | |
Simulation time | 1371722830 ps |
CPU time | 5.72 seconds |
Started | Jun 27 06:51:41 PM PDT 24 |
Finished | Jun 27 06:51:51 PM PDT 24 |
Peak memory | 210884 kb |
Host | smart-2860bf07-f46b-43e8-b68e-f90131dddc06 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63689011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 27.sram_ctrl_throughput_w_partial_write.63689011 |
Directory | /workspace/27.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_access_during_key_req.1513785163 |
Short name | T841 |
Test name | |
Test status | |
Simulation time | 26640548335 ps |
CPU time | 687.27 seconds |
Started | Jun 27 06:51:53 PM PDT 24 |
Finished | Jun 27 07:03:22 PM PDT 24 |
Peak memory | 367652 kb |
Host | smart-07c13629-59fc-4591-9c90-1ed982a4b6b5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513785163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 28.sram_ctrl_access_during_key_req.1513785163 |
Directory | /workspace/28.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_alert_test.1539178372 |
Short name | T906 |
Test name | |
Test status | |
Simulation time | 21581638 ps |
CPU time | 0.67 seconds |
Started | Jun 27 06:52:05 PM PDT 24 |
Finished | Jun 27 06:52:07 PM PDT 24 |
Peak memory | 202344 kb |
Host | smart-1af4febb-2fbd-47f1-bb0e-fdeb48683fa2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539178372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.1539178372 |
Directory | /workspace/28.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_bijection.3222071554 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 335233073862 ps |
CPU time | 1662.6 seconds |
Started | Jun 27 06:53:03 PM PDT 24 |
Finished | Jun 27 07:20:46 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-8174ccbc-f973-4569-aab5-94b75128a7f6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222071554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection .3222071554 |
Directory | /workspace/28.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_executable.1357596704 |
Short name | T819 |
Test name | |
Test status | |
Simulation time | 21119770629 ps |
CPU time | 526.2 seconds |
Started | Jun 27 06:51:55 PM PDT 24 |
Finished | Jun 27 07:00:43 PM PDT 24 |
Peak memory | 365708 kb |
Host | smart-7d26f50a-be21-4ccb-8bc4-f048852e0af7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357596704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executab le.1357596704 |
Directory | /workspace/28.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_lc_escalation.429732961 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 179204626949 ps |
CPU time | 79.61 seconds |
Started | Jun 27 06:51:55 PM PDT 24 |
Finished | Jun 27 06:53:16 PM PDT 24 |
Peak memory | 210756 kb |
Host | smart-86bf15f6-38fb-4711-9093-3015c302c02b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429732961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_esc alation.429732961 |
Directory | /workspace/28.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_max_throughput.2575012352 |
Short name | T939 |
Test name | |
Test status | |
Simulation time | 1511631268 ps |
CPU time | 5.87 seconds |
Started | Jun 27 06:51:53 PM PDT 24 |
Finished | Jun 27 06:52:00 PM PDT 24 |
Peak memory | 202664 kb |
Host | smart-2a65be9e-e6e2-4cae-921d-abcd072189e8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575012352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 28.sram_ctrl_max_throughput.2575012352 |
Directory | /workspace/28.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_mem_partial_access.3642883032 |
Short name | T719 |
Test name | |
Test status | |
Simulation time | 10521323645 ps |
CPU time | 81.85 seconds |
Started | Jun 27 06:51:53 PM PDT 24 |
Finished | Jun 27 06:53:16 PM PDT 24 |
Peak memory | 219184 kb |
Host | smart-af6553f2-5312-4979-b867-496947d88764 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642883032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_mem_partial_access.3642883032 |
Directory | /workspace/28.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_mem_walk.2375540553 |
Short name | T623 |
Test name | |
Test status | |
Simulation time | 7902596760 ps |
CPU time | 131.04 seconds |
Started | Jun 27 06:51:54 PM PDT 24 |
Finished | Jun 27 06:54:06 PM PDT 24 |
Peak memory | 211760 kb |
Host | smart-8189f879-8e15-4012-8445-62e21d8ba694 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375540553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctr l_mem_walk.2375540553 |
Directory | /workspace/28.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_multiple_keys.3043570997 |
Short name | T582 |
Test name | |
Test status | |
Simulation time | 33725328574 ps |
CPU time | 1457.23 seconds |
Started | Jun 27 06:51:55 PM PDT 24 |
Finished | Jun 27 07:16:14 PM PDT 24 |
Peak memory | 379740 kb |
Host | smart-ef59cf14-14fe-4c89-9d68-f7092bded8da |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043570997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi ple_keys.3043570997 |
Directory | /workspace/28.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_partial_access.1999752055 |
Short name | T510 |
Test name | |
Test status | |
Simulation time | 2616733844 ps |
CPU time | 27.29 seconds |
Started | Jun 27 06:51:55 PM PDT 24 |
Finished | Jun 27 06:52:24 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-4c89d360-b54a-4b01-98c5-103daa21598c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999752055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28. sram_ctrl_partial_access.1999752055 |
Directory | /workspace/28.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1841298110 |
Short name | T591 |
Test name | |
Test status | |
Simulation time | 13581261000 ps |
CPU time | 355.35 seconds |
Started | Jun 27 06:51:54 PM PDT 24 |
Finished | Jun 27 06:57:50 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-8acf73cc-0eec-40dc-b179-a7ecbd5e92b8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841298110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 28.sram_ctrl_partial_access_b2b.1841298110 |
Directory | /workspace/28.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_ram_cfg.3744600006 |
Short name | T799 |
Test name | |
Test status | |
Simulation time | 711164232 ps |
CPU time | 3.35 seconds |
Started | Jun 27 06:52:04 PM PDT 24 |
Finished | Jun 27 06:52:09 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-4108d374-b22d-4770-9520-fd3c361b84d0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744600006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.3744600006 |
Directory | /workspace/28.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_regwen.2936267517 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 16383971535 ps |
CPU time | 1354.61 seconds |
Started | Jun 27 06:51:54 PM PDT 24 |
Finished | Jun 27 07:14:30 PM PDT 24 |
Peak memory | 380844 kb |
Host | smart-edf6e2d5-e85f-44df-a245-989ac7f14ba0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936267517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.2936267517 |
Directory | /workspace/28.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_smoke.3158607423 |
Short name | T526 |
Test name | |
Test status | |
Simulation time | 894074166 ps |
CPU time | 21.87 seconds |
Started | Jun 27 06:52:05 PM PDT 24 |
Finished | Jun 27 06:52:28 PM PDT 24 |
Peak memory | 202804 kb |
Host | smart-d1f3e58d-9f85-40de-92db-95fa954e0f5d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158607423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.3158607423 |
Directory | /workspace/28.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_all.2511342478 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 167411534498 ps |
CPU time | 5979.31 seconds |
Started | Jun 27 06:52:07 PM PDT 24 |
Finished | Jun 27 08:31:48 PM PDT 24 |
Peak memory | 383112 kb |
Host | smart-34671a00-57be-4d60-a888-b029110346c0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511342478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 28.sram_ctrl_stress_all.2511342478 |
Directory | /workspace/28.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2290495096 |
Short name | T585 |
Test name | |
Test status | |
Simulation time | 2205641831 ps |
CPU time | 179.33 seconds |
Started | Jun 27 06:52:07 PM PDT 24 |
Finished | Jun 27 06:55:08 PM PDT 24 |
Peak memory | 361540 kb |
Host | smart-5f9f8b20-b025-4f45-a683-e148a461eb23 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2290495096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.2290495096 |
Directory | /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_pipeline.3964216132 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 3569575171 ps |
CPU time | 199.92 seconds |
Started | Jun 27 06:51:55 PM PDT 24 |
Finished | Jun 27 06:55:17 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-5b94d6b9-e60b-49bd-b9a1-762655476d8d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964216132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_stress_pipeline.3964216132 |
Directory | /workspace/28.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.367243056 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 3124569128 ps |
CPU time | 135.61 seconds |
Started | Jun 27 06:51:57 PM PDT 24 |
Finished | Jun 27 06:54:13 PM PDT 24 |
Peak memory | 371480 kb |
Host | smart-64e843ba-8053-47cb-9f9e-b8ef2d0e70d5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367243056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 28.sram_ctrl_throughput_w_partial_write.367243056 |
Directory | /workspace/28.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_access_during_key_req.1899009831 |
Short name | T673 |
Test name | |
Test status | |
Simulation time | 37327855268 ps |
CPU time | 1231.09 seconds |
Started | Jun 27 06:52:20 PM PDT 24 |
Finished | Jun 27 07:12:53 PM PDT 24 |
Peak memory | 377768 kb |
Host | smart-a3a24b8a-cf10-4b29-94c5-c9acd3fc90a0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899009831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 29.sram_ctrl_access_during_key_req.1899009831 |
Directory | /workspace/29.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_alert_test.939943666 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 37978823 ps |
CPU time | 0.67 seconds |
Started | Jun 27 06:52:21 PM PDT 24 |
Finished | Jun 27 06:52:23 PM PDT 24 |
Peak memory | 202380 kb |
Host | smart-f5f8e70b-d6ce-41e5-a30b-2c4fa6ff055c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939943666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.939943666 |
Directory | /workspace/29.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_bijection.2282004230 |
Short name | T501 |
Test name | |
Test status | |
Simulation time | 253619979054 ps |
CPU time | 2119.6 seconds |
Started | Jun 27 06:52:06 PM PDT 24 |
Finished | Jun 27 07:27:28 PM PDT 24 |
Peak memory | 202992 kb |
Host | smart-94ef754d-6198-41e0-8f4e-e7e49cddd77b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282004230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection .2282004230 |
Directory | /workspace/29.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_executable.3136227283 |
Short name | T724 |
Test name | |
Test status | |
Simulation time | 17589641022 ps |
CPU time | 1348.54 seconds |
Started | Jun 27 06:52:20 PM PDT 24 |
Finished | Jun 27 07:14:50 PM PDT 24 |
Peak memory | 379916 kb |
Host | smart-d3d3362e-2b80-48cd-9218-b3e6c3a261c3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136227283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab le.3136227283 |
Directory | /workspace/29.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_lc_escalation.3971265062 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 14752448236 ps |
CPU time | 25.5 seconds |
Started | Jun 27 06:52:07 PM PDT 24 |
Finished | Jun 27 06:52:34 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-8e0939e2-375c-48fc-b77e-ed9ad5ecc7af |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971265062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_es calation.3971265062 |
Directory | /workspace/29.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_max_throughput.2272676297 |
Short name | T811 |
Test name | |
Test status | |
Simulation time | 798970291 ps |
CPU time | 156.51 seconds |
Started | Jun 27 06:52:09 PM PDT 24 |
Finished | Jun 27 06:54:47 PM PDT 24 |
Peak memory | 370424 kb |
Host | smart-a82b6b02-ee9d-4238-8987-d042f893baac |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272676297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 29.sram_ctrl_max_throughput.2272676297 |
Directory | /workspace/29.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_mem_partial_access.211518108 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 5226064725 ps |
CPU time | 183.12 seconds |
Started | Jun 27 06:52:19 PM PDT 24 |
Finished | Jun 27 06:55:23 PM PDT 24 |
Peak memory | 211076 kb |
Host | smart-d9991365-5664-40d1-817e-b98cbe5a3098 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211518108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29 .sram_ctrl_mem_partial_access.211518108 |
Directory | /workspace/29.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_mem_walk.699417605 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 13841326106 ps |
CPU time | 154.87 seconds |
Started | Jun 27 06:52:18 PM PDT 24 |
Finished | Jun 27 06:54:54 PM PDT 24 |
Peak memory | 211048 kb |
Host | smart-3fbd9dac-be8e-4132-9da0-a7e7cf827e62 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699417605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl _mem_walk.699417605 |
Directory | /workspace/29.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_multiple_keys.3839547174 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 39495040615 ps |
CPU time | 1154.4 seconds |
Started | Jun 27 06:52:06 PM PDT 24 |
Finished | Jun 27 07:11:22 PM PDT 24 |
Peak memory | 379772 kb |
Host | smart-8445b9ba-ba6b-4c30-be51-197d2a5b128b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839547174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi ple_keys.3839547174 |
Directory | /workspace/29.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_partial_access.366425824 |
Short name | T742 |
Test name | |
Test status | |
Simulation time | 1664987141 ps |
CPU time | 12.42 seconds |
Started | Jun 27 06:52:08 PM PDT 24 |
Finished | Jun 27 06:52:22 PM PDT 24 |
Peak memory | 202752 kb |
Host | smart-3c9cd574-3aa4-4840-a04b-4b8865cdcef6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366425824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.s ram_ctrl_partial_access.366425824 |
Directory | /workspace/29.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.2887642835 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 89892155290 ps |
CPU time | 580.31 seconds |
Started | Jun 27 06:52:08 PM PDT 24 |
Finished | Jun 27 07:01:50 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-9be1f905-45c4-42b7-ac66-21af43171937 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887642835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 29.sram_ctrl_partial_access_b2b.2887642835 |
Directory | /workspace/29.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_ram_cfg.3088410553 |
Short name | T870 |
Test name | |
Test status | |
Simulation time | 684445385 ps |
CPU time | 3.37 seconds |
Started | Jun 27 06:52:17 PM PDT 24 |
Finished | Jun 27 06:52:21 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-ab1c5c14-584b-4130-92c8-435555afa87d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088410553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.3088410553 |
Directory | /workspace/29.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_regwen.2252112503 |
Short name | T728 |
Test name | |
Test status | |
Simulation time | 17364264560 ps |
CPU time | 203.53 seconds |
Started | Jun 27 06:52:18 PM PDT 24 |
Finished | Jun 27 06:55:43 PM PDT 24 |
Peak memory | 376736 kb |
Host | smart-c2a09d57-e8a0-4779-9564-0d6a65d0688e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252112503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.2252112503 |
Directory | /workspace/29.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_smoke.3251226880 |
Short name | T705 |
Test name | |
Test status | |
Simulation time | 3005751007 ps |
CPU time | 10.62 seconds |
Started | Jun 27 06:52:07 PM PDT 24 |
Finished | Jun 27 06:52:19 PM PDT 24 |
Peak memory | 218624 kb |
Host | smart-11ff60bf-3f6f-4b30-b02d-023840d826c4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251226880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.3251226880 |
Directory | /workspace/29.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_all.2037271318 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 219124034361 ps |
CPU time | 2229.58 seconds |
Started | Jun 27 06:52:17 PM PDT 24 |
Finished | Jun 27 07:29:28 PM PDT 24 |
Peak memory | 380768 kb |
Host | smart-3f3b9802-6ef5-4947-b351-e6a5ffded16a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037271318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 29.sram_ctrl_stress_all.2037271318 |
Directory | /workspace/29.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.3511826035 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 1374414563 ps |
CPU time | 16.72 seconds |
Started | Jun 27 06:52:21 PM PDT 24 |
Finished | Jun 27 06:52:39 PM PDT 24 |
Peak memory | 211092 kb |
Host | smart-aa07b05d-4b8b-47dc-a2b4-5600dad12da1 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3511826035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.3511826035 |
Directory | /workspace/29.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_pipeline.4113732102 |
Short name | T456 |
Test name | |
Test status | |
Simulation time | 26981674052 ps |
CPU time | 402.37 seconds |
Started | Jun 27 06:52:07 PM PDT 24 |
Finished | Jun 27 06:58:51 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-92021d21-2925-4152-b556-83188fa9d106 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113732102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_stress_pipeline.4113732102 |
Directory | /workspace/29.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.4242933271 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 3131702905 ps |
CPU time | 147.99 seconds |
Started | Jun 27 06:52:07 PM PDT 24 |
Finished | Jun 27 06:54:36 PM PDT 24 |
Peak memory | 370464 kb |
Host | smart-9a114c3f-9f49-438b-b7c8-0959f0ec9a51 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242933271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.4242933271 |
Directory | /workspace/29.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_access_during_key_req.3024921953 |
Short name | T615 |
Test name | |
Test status | |
Simulation time | 28075039496 ps |
CPU time | 1151.61 seconds |
Started | Jun 27 06:49:14 PM PDT 24 |
Finished | Jun 27 07:08:30 PM PDT 24 |
Peak memory | 378728 kb |
Host | smart-b78cbcde-80bc-4c9a-b164-e9836a7946ca |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024921953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_access_during_key_req.3024921953 |
Directory | /workspace/3.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_alert_test.2069567985 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 14026134 ps |
CPU time | 0.65 seconds |
Started | Jun 27 06:49:14 PM PDT 24 |
Finished | Jun 27 06:49:18 PM PDT 24 |
Peak memory | 202160 kb |
Host | smart-85881def-3eee-4698-aaad-8a9ae0ac1dc7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069567985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.2069567985 |
Directory | /workspace/3.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_bijection.2723722050 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 61850935443 ps |
CPU time | 1433.94 seconds |
Started | Jun 27 06:49:16 PM PDT 24 |
Finished | Jun 27 07:13:14 PM PDT 24 |
Peak memory | 203728 kb |
Host | smart-e2dc5158-40e2-4187-b1b8-dac2f5c47a32 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723722050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection. 2723722050 |
Directory | /workspace/3.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_executable.3131963873 |
Short name | T642 |
Test name | |
Test status | |
Simulation time | 13676484057 ps |
CPU time | 459.29 seconds |
Started | Jun 27 06:49:12 PM PDT 24 |
Finished | Jun 27 06:56:53 PM PDT 24 |
Peak memory | 372356 kb |
Host | smart-18e1b617-23c4-426f-8569-8de34f8125a3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131963873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl e.3131963873 |
Directory | /workspace/3.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_lc_escalation.1062116337 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 84474786954 ps |
CPU time | 53.79 seconds |
Started | Jun 27 06:49:14 PM PDT 24 |
Finished | Jun 27 06:50:11 PM PDT 24 |
Peak memory | 212436 kb |
Host | smart-47f2e457-943a-4cea-a46c-4c597b3fe869 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062116337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc alation.1062116337 |
Directory | /workspace/3.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_max_throughput.4009816083 |
Short name | T494 |
Test name | |
Test status | |
Simulation time | 776961022 ps |
CPU time | 67.17 seconds |
Started | Jun 27 06:49:12 PM PDT 24 |
Finished | Jun 27 06:50:22 PM PDT 24 |
Peak memory | 314172 kb |
Host | smart-39f8cecf-8a79-4fea-ac24-07d49acde3c5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009816083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_max_throughput.4009816083 |
Directory | /workspace/3.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_mem_partial_access.3070021916 |
Short name | T802 |
Test name | |
Test status | |
Simulation time | 18708658334 ps |
CPU time | 87.65 seconds |
Started | Jun 27 06:49:13 PM PDT 24 |
Finished | Jun 27 06:50:44 PM PDT 24 |
Peak memory | 211380 kb |
Host | smart-8916504d-ac54-4508-acdc-092b020738f6 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070021916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_mem_partial_access.3070021916 |
Directory | /workspace/3.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_mem_walk.1183253105 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 128415448483 ps |
CPU time | 357.55 seconds |
Started | Jun 27 06:49:12 PM PDT 24 |
Finished | Jun 27 06:55:13 PM PDT 24 |
Peak memory | 212172 kb |
Host | smart-dc32100b-749c-49d6-8345-25faa8fceabd |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183253105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl _mem_walk.1183253105 |
Directory | /workspace/3.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_multiple_keys.2923348614 |
Short name | T918 |
Test name | |
Test status | |
Simulation time | 105400357339 ps |
CPU time | 993.85 seconds |
Started | Jun 27 06:49:12 PM PDT 24 |
Finished | Jun 27 07:05:49 PM PDT 24 |
Peak memory | 377748 kb |
Host | smart-a0e6172d-28e9-4789-9083-f711f401ec04 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923348614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip le_keys.2923348614 |
Directory | /workspace/3.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_partial_access.3642437781 |
Short name | T666 |
Test name | |
Test status | |
Simulation time | 397876960 ps |
CPU time | 4.85 seconds |
Started | Jun 27 06:49:12 PM PDT 24 |
Finished | Jun 27 06:49:20 PM PDT 24 |
Peak memory | 202728 kb |
Host | smart-5880752d-3b43-4fb4-bd38-19de6962ea3e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642437781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s ram_ctrl_partial_access.3642437781 |
Directory | /workspace/3.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3230818933 |
Short name | T813 |
Test name | |
Test status | |
Simulation time | 30072937689 ps |
CPU time | 443.64 seconds |
Started | Jun 27 06:49:14 PM PDT 24 |
Finished | Jun 27 06:56:41 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-66490e12-585f-4e21-944d-6f8a2f418801 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230818933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 3.sram_ctrl_partial_access_b2b.3230818933 |
Directory | /workspace/3.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_ram_cfg.3348266953 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 679525468 ps |
CPU time | 3.43 seconds |
Started | Jun 27 06:49:14 PM PDT 24 |
Finished | Jun 27 06:49:21 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-eb43e8e8-2329-4f55-9efb-aed6b2333bef |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348266953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.3348266953 |
Directory | /workspace/3.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_regwen.2503912466 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 7558524884 ps |
CPU time | 258.3 seconds |
Started | Jun 27 06:49:16 PM PDT 24 |
Finished | Jun 27 06:53:38 PM PDT 24 |
Peak memory | 351252 kb |
Host | smart-68bc3455-abab-47d8-8372-f741113f3b25 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503912466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.2503912466 |
Directory | /workspace/3.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_sec_cm.991776131 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 476274163 ps |
CPU time | 2.75 seconds |
Started | Jun 27 06:49:14 PM PDT 24 |
Finished | Jun 27 06:49:20 PM PDT 24 |
Peak memory | 222252 kb |
Host | smart-9261c43b-861a-41d1-9d02-792023c79480 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991776131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_sec_cm.991776131 |
Directory | /workspace/3.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_smoke.2219666818 |
Short name | T703 |
Test name | |
Test status | |
Simulation time | 13585047772 ps |
CPU time | 26.55 seconds |
Started | Jun 27 06:49:16 PM PDT 24 |
Finished | Jun 27 06:49:47 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-740a1359-e1bf-4e57-b750-035e1bc9e367 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219666818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.2219666818 |
Directory | /workspace/3.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3674284227 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 341193605 ps |
CPU time | 8.42 seconds |
Started | Jun 27 06:49:13 PM PDT 24 |
Finished | Jun 27 06:49:26 PM PDT 24 |
Peak memory | 211072 kb |
Host | smart-b978269b-14b0-427c-a957-016a2bc8f497 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3674284227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.3674284227 |
Directory | /workspace/3.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_pipeline.3612184046 |
Short name | T486 |
Test name | |
Test status | |
Simulation time | 4080309416 ps |
CPU time | 212.16 seconds |
Started | Jun 27 06:49:12 PM PDT 24 |
Finished | Jun 27 06:52:47 PM PDT 24 |
Peak memory | 202828 kb |
Host | smart-17ffb25d-8d7b-4680-85ba-27f33f5649a2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612184046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_stress_pipeline.3612184046 |
Directory | /workspace/3.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.2650299479 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 746020575 ps |
CPU time | 47.66 seconds |
Started | Jun 27 06:49:14 PM PDT 24 |
Finished | Jun 27 06:50:05 PM PDT 24 |
Peak memory | 291256 kb |
Host | smart-0b6785d3-0db9-42f1-9ffa-c0e17d78319a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650299479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.2650299479 |
Directory | /workspace/3.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_access_during_key_req.435038204 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 37284837652 ps |
CPU time | 501.9 seconds |
Started | Jun 27 06:52:36 PM PDT 24 |
Finished | Jun 27 07:01:00 PM PDT 24 |
Peak memory | 370556 kb |
Host | smart-d459e1f6-e80e-42ef-b0c9-4e4b95988ef2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435038204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 30.sram_ctrl_access_during_key_req.435038204 |
Directory | /workspace/30.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_alert_test.764846015 |
Short name | T488 |
Test name | |
Test status | |
Simulation time | 22724130 ps |
CPU time | 0.67 seconds |
Started | Jun 27 06:52:36 PM PDT 24 |
Finished | Jun 27 06:52:39 PM PDT 24 |
Peak memory | 202592 kb |
Host | smart-e480d323-1669-40a2-822c-7c669f0674c0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764846015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.764846015 |
Directory | /workspace/30.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_bijection.201169893 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 364527947630 ps |
CPU time | 2104.14 seconds |
Started | Jun 27 06:52:18 PM PDT 24 |
Finished | Jun 27 07:27:23 PM PDT 24 |
Peak memory | 203456 kb |
Host | smart-b324c600-9190-440d-9dab-b689ce06d576 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201169893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection. 201169893 |
Directory | /workspace/30.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_executable.127231304 |
Short name | T862 |
Test name | |
Test status | |
Simulation time | 26929152250 ps |
CPU time | 488.29 seconds |
Started | Jun 27 06:52:36 PM PDT 24 |
Finished | Jun 27 07:00:46 PM PDT 24 |
Peak memory | 368500 kb |
Host | smart-77029b14-e4bb-4d2c-94e9-421d8c9529a3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127231304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executabl e.127231304 |
Directory | /workspace/30.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_lc_escalation.4013584376 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 8344434492 ps |
CPU time | 48.99 seconds |
Started | Jun 27 06:52:38 PM PDT 24 |
Finished | Jun 27 06:53:29 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-7fa10c4a-c74e-433d-87ba-493a12576598 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013584376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es calation.4013584376 |
Directory | /workspace/30.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_max_throughput.3798564575 |
Short name | T921 |
Test name | |
Test status | |
Simulation time | 2974665094 ps |
CPU time | 77.33 seconds |
Started | Jun 27 06:52:36 PM PDT 24 |
Finished | Jun 27 06:53:55 PM PDT 24 |
Peak memory | 333640 kb |
Host | smart-cb119024-6a64-4930-88d5-ee2b430efde0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798564575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 30.sram_ctrl_max_throughput.3798564575 |
Directory | /workspace/30.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_mem_partial_access.3184266323 |
Short name | T922 |
Test name | |
Test status | |
Simulation time | 10892810358 ps |
CPU time | 86.55 seconds |
Started | Jun 27 06:52:37 PM PDT 24 |
Finished | Jun 27 06:54:05 PM PDT 24 |
Peak memory | 211104 kb |
Host | smart-ec67faf5-b7d9-47db-b7f6-0739e2e9a08d |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184266323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_mem_partial_access.3184266323 |
Directory | /workspace/30.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_mem_walk.3042448623 |
Short name | T646 |
Test name | |
Test status | |
Simulation time | 21350319687 ps |
CPU time | 363.3 seconds |
Started | Jun 27 06:52:35 PM PDT 24 |
Finished | Jun 27 06:58:41 PM PDT 24 |
Peak memory | 211008 kb |
Host | smart-06195692-a001-4a66-8704-92eca08c99ee |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042448623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr l_mem_walk.3042448623 |
Directory | /workspace/30.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_multiple_keys.784450845 |
Short name | T912 |
Test name | |
Test status | |
Simulation time | 38392502887 ps |
CPU time | 1063.4 seconds |
Started | Jun 27 06:52:18 PM PDT 24 |
Finished | Jun 27 07:10:03 PM PDT 24 |
Peak memory | 376608 kb |
Host | smart-f1e401d1-6c75-47e5-83cf-7725461acd22 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784450845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multip le_keys.784450845 |
Directory | /workspace/30.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_partial_access.925305214 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 2167088649 ps |
CPU time | 34.77 seconds |
Started | Jun 27 06:52:20 PM PDT 24 |
Finished | Jun 27 06:52:55 PM PDT 24 |
Peak memory | 283476 kb |
Host | smart-9a066d96-3086-4546-b24d-138bb620e391 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925305214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.s ram_ctrl_partial_access.925305214 |
Directory | /workspace/30.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.3100759578 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 7304717534 ps |
CPU time | 353.63 seconds |
Started | Jun 27 06:52:37 PM PDT 24 |
Finished | Jun 27 06:58:32 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-1191e994-9dda-4744-879a-ee4baea38584 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100759578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 30.sram_ctrl_partial_access_b2b.3100759578 |
Directory | /workspace/30.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_ram_cfg.3593365492 |
Short name | T776 |
Test name | |
Test status | |
Simulation time | 356762171 ps |
CPU time | 3.05 seconds |
Started | Jun 27 06:52:35 PM PDT 24 |
Finished | Jun 27 06:52:40 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-cc60ca52-ef43-4a74-9081-d4173b717ddb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593365492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.3593365492 |
Directory | /workspace/30.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_regwen.1997522018 |
Short name | T880 |
Test name | |
Test status | |
Simulation time | 6096828599 ps |
CPU time | 1095.48 seconds |
Started | Jun 27 06:52:36 PM PDT 24 |
Finished | Jun 27 07:10:54 PM PDT 24 |
Peak memory | 381820 kb |
Host | smart-82b19121-f650-433e-8d17-7ce6e645b6b8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997522018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.1997522018 |
Directory | /workspace/30.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_smoke.2238336 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 485179155 ps |
CPU time | 12.22 seconds |
Started | Jun 27 06:52:21 PM PDT 24 |
Finished | Jun 27 06:52:35 PM PDT 24 |
Peak memory | 202748 kb |
Host | smart-24fa3bcf-79bf-4428-af22-4b7306d15cf1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.2238336 |
Directory | /workspace/30.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_all.3567573508 |
Short name | T809 |
Test name | |
Test status | |
Simulation time | 68469808984 ps |
CPU time | 5461.08 seconds |
Started | Jun 27 06:52:36 PM PDT 24 |
Finished | Jun 27 08:23:40 PM PDT 24 |
Peak memory | 381408 kb |
Host | smart-0e6c8c51-facc-43ad-be0e-3f0a8c25cfaa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567573508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 30.sram_ctrl_stress_all.3567573508 |
Directory | /workspace/30.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.1278194296 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 1017876942 ps |
CPU time | 27.03 seconds |
Started | Jun 27 06:52:36 PM PDT 24 |
Finished | Jun 27 06:53:05 PM PDT 24 |
Peak memory | 211144 kb |
Host | smart-2ad38572-1471-49f6-8031-b1dd2581f937 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1278194296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.1278194296 |
Directory | /workspace/30.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_pipeline.2390157022 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 26427837135 ps |
CPU time | 343.67 seconds |
Started | Jun 27 06:52:17 PM PDT 24 |
Finished | Jun 27 06:58:01 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-a670baea-1815-45a6-98d5-a0cd4b2abdcf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390157022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_stress_pipeline.2390157022 |
Directory | /workspace/30.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.210176804 |
Short name | T551 |
Test name | |
Test status | |
Simulation time | 788110661 ps |
CPU time | 167.14 seconds |
Started | Jun 27 06:52:37 PM PDT 24 |
Finished | Jun 27 06:55:26 PM PDT 24 |
Peak memory | 366552 kb |
Host | smart-0af5cbba-6b38-4538-98e2-2e1baab3c252 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210176804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 30.sram_ctrl_throughput_w_partial_write.210176804 |
Directory | /workspace/30.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_access_during_key_req.3961018783 |
Short name | T725 |
Test name | |
Test status | |
Simulation time | 6656682796 ps |
CPU time | 389.52 seconds |
Started | Jun 27 06:52:49 PM PDT 24 |
Finished | Jun 27 06:59:21 PM PDT 24 |
Peak memory | 372264 kb |
Host | smart-ccfa3611-c63d-4f77-9625-c349052061af |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961018783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 31.sram_ctrl_access_during_key_req.3961018783 |
Directory | /workspace/31.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_alert_test.2193325999 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 43327939 ps |
CPU time | 0.67 seconds |
Started | Jun 27 06:52:50 PM PDT 24 |
Finished | Jun 27 06:52:53 PM PDT 24 |
Peak memory | 202524 kb |
Host | smart-51c80975-674b-4a86-8a85-1b848a28d26a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193325999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.2193325999 |
Directory | /workspace/31.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_bijection.1087624582 |
Short name | T619 |
Test name | |
Test status | |
Simulation time | 13073088449 ps |
CPU time | 738.13 seconds |
Started | Jun 27 06:52:35 PM PDT 24 |
Finished | Jun 27 07:04:55 PM PDT 24 |
Peak memory | 203424 kb |
Host | smart-4c365ac4-0c54-47e6-b749-dbf307e31847 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087624582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection .1087624582 |
Directory | /workspace/31.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_executable.3655502880 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 28761786719 ps |
CPU time | 223.2 seconds |
Started | Jun 27 06:52:55 PM PDT 24 |
Finished | Jun 27 06:56:39 PM PDT 24 |
Peak memory | 376656 kb |
Host | smart-75373522-1e2a-4e4b-9a7e-5abe9ca19da2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655502880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executab le.3655502880 |
Directory | /workspace/31.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_lc_escalation.2897177181 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 33467389538 ps |
CPU time | 112.7 seconds |
Started | Jun 27 06:52:49 PM PDT 24 |
Finished | Jun 27 06:54:44 PM PDT 24 |
Peak memory | 211136 kb |
Host | smart-1765ad0e-2d97-4224-a7a5-819fb53eeed2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897177181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es calation.2897177181 |
Directory | /workspace/31.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_max_throughput.3381130545 |
Short name | T896 |
Test name | |
Test status | |
Simulation time | 2937834301 ps |
CPU time | 24.16 seconds |
Started | Jun 27 06:52:55 PM PDT 24 |
Finished | Jun 27 06:53:20 PM PDT 24 |
Peak memory | 271332 kb |
Host | smart-cf2198f0-70bb-4b08-9ee2-7bb30d4cdc82 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381130545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 31.sram_ctrl_max_throughput.3381130545 |
Directory | /workspace/31.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_mem_partial_access.38909640 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 2507878532 ps |
CPU time | 74.24 seconds |
Started | Jun 27 06:52:48 PM PDT 24 |
Finished | Jun 27 06:54:05 PM PDT 24 |
Peak memory | 211060 kb |
Host | smart-52b2f71b-54d6-4a42-9e2d-f54d7ffd02b1 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38909640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31. sram_ctrl_mem_partial_access.38909640 |
Directory | /workspace/31.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_mem_walk.4055569330 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 6935664481 ps |
CPU time | 157.12 seconds |
Started | Jun 27 06:52:50 PM PDT 24 |
Finished | Jun 27 06:55:29 PM PDT 24 |
Peak memory | 211036 kb |
Host | smart-49bca4d0-8cd5-4aac-a8a2-cf1594c49b03 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055569330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr l_mem_walk.4055569330 |
Directory | /workspace/31.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_multiple_keys.785164342 |
Short name | T611 |
Test name | |
Test status | |
Simulation time | 4121247140 ps |
CPU time | 459.92 seconds |
Started | Jun 27 06:52:36 PM PDT 24 |
Finished | Jun 27 07:00:18 PM PDT 24 |
Peak memory | 356212 kb |
Host | smart-6025f16b-da11-4f55-ad16-5e9a3aec8882 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785164342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multip le_keys.785164342 |
Directory | /workspace/31.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_partial_access.1421086618 |
Short name | T550 |
Test name | |
Test status | |
Simulation time | 8645606590 ps |
CPU time | 36.67 seconds |
Started | Jun 27 06:52:48 PM PDT 24 |
Finished | Jun 27 06:53:28 PM PDT 24 |
Peak memory | 285620 kb |
Host | smart-7bd6dd4f-bc89-4f85-877c-a919211be9a9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421086618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31. sram_ctrl_partial_access.1421086618 |
Directory | /workspace/31.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.365122434 |
Short name | T840 |
Test name | |
Test status | |
Simulation time | 102574473887 ps |
CPU time | 304.89 seconds |
Started | Jun 27 06:52:47 PM PDT 24 |
Finished | Jun 27 06:57:55 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-da2b5041-444c-44c1-a1cd-35dcf0c64027 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365122434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 31.sram_ctrl_partial_access_b2b.365122434 |
Directory | /workspace/31.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_ram_cfg.1605633541 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 1360556070 ps |
CPU time | 3.37 seconds |
Started | Jun 27 06:52:48 PM PDT 24 |
Finished | Jun 27 06:52:53 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-59a0cb5f-2490-4018-8299-0ee450c17eed |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605633541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.1605633541 |
Directory | /workspace/31.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_regwen.2583916327 |
Short name | T593 |
Test name | |
Test status | |
Simulation time | 17786501220 ps |
CPU time | 454.56 seconds |
Started | Jun 27 06:52:48 PM PDT 24 |
Finished | Jun 27 07:00:25 PM PDT 24 |
Peak memory | 376668 kb |
Host | smart-b0d5797c-4832-4a94-a629-41953b6a0dc6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583916327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.2583916327 |
Directory | /workspace/31.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_smoke.3285740693 |
Short name | T869 |
Test name | |
Test status | |
Simulation time | 982238425 ps |
CPU time | 16.18 seconds |
Started | Jun 27 06:52:35 PM PDT 24 |
Finished | Jun 27 06:52:53 PM PDT 24 |
Peak memory | 202768 kb |
Host | smart-d0cee374-af94-46c3-9ce6-33dbc75e6cbc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285740693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.3285740693 |
Directory | /workspace/31.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_all.12936510 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 31476830170 ps |
CPU time | 1753.53 seconds |
Started | Jun 27 06:52:49 PM PDT 24 |
Finished | Jun 27 07:22:05 PM PDT 24 |
Peak memory | 380040 kb |
Host | smart-b0e8ab7e-2eba-41a3-ae9c-7435ae2a5d1b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12936510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test + UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 31.sram_ctrl_stress_all.12936510 |
Directory | /workspace/31.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3817645334 |
Short name | T667 |
Test name | |
Test status | |
Simulation time | 6005719052 ps |
CPU time | 48.76 seconds |
Started | Jun 27 06:52:50 PM PDT 24 |
Finished | Jun 27 06:53:41 PM PDT 24 |
Peak memory | 219268 kb |
Host | smart-fba44946-554b-44fe-a1e9-3ec722fa432d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3817645334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.3817645334 |
Directory | /workspace/31.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_pipeline.3201031300 |
Short name | T789 |
Test name | |
Test status | |
Simulation time | 4506380376 ps |
CPU time | 354.34 seconds |
Started | Jun 27 06:52:48 PM PDT 24 |
Finished | Jun 27 06:58:45 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-5908f15c-a1d9-4224-b3a6-f588a01cea7c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201031300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_stress_pipeline.3201031300 |
Directory | /workspace/31.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.1818260816 |
Short name | T778 |
Test name | |
Test status | |
Simulation time | 1560745230 ps |
CPU time | 99.65 seconds |
Started | Jun 27 06:52:50 PM PDT 24 |
Finished | Jun 27 06:54:32 PM PDT 24 |
Peak memory | 364296 kb |
Host | smart-48c75da0-3d8c-457e-9f8f-09103c019ee1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818260816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.1818260816 |
Directory | /workspace/31.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_access_during_key_req.128938098 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 38719132043 ps |
CPU time | 627.79 seconds |
Started | Jun 27 06:52:55 PM PDT 24 |
Finished | Jun 27 07:03:23 PM PDT 24 |
Peak memory | 376696 kb |
Host | smart-928fa2c3-0b78-42a2-a4c3-db61407a5807 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128938098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 32.sram_ctrl_access_during_key_req.128938098 |
Directory | /workspace/32.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_alert_test.2625823254 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 34527115 ps |
CPU time | 0.67 seconds |
Started | Jun 27 06:53:00 PM PDT 24 |
Finished | Jun 27 06:53:02 PM PDT 24 |
Peak memory | 202548 kb |
Host | smart-8e7bc932-4486-42aa-86ec-4047eca8f64b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625823254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.2625823254 |
Directory | /workspace/32.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_bijection.3065445985 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 12710071058 ps |
CPU time | 542.75 seconds |
Started | Jun 27 06:52:50 PM PDT 24 |
Finished | Jun 27 07:01:55 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-825e6096-2a51-40c6-abab-96ff5cf9dd81 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065445985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection .3065445985 |
Directory | /workspace/32.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_executable.1791473749 |
Short name | T702 |
Test name | |
Test status | |
Simulation time | 26967669657 ps |
CPU time | 602.76 seconds |
Started | Jun 27 06:53:01 PM PDT 24 |
Finished | Jun 27 07:03:06 PM PDT 24 |
Peak memory | 372580 kb |
Host | smart-9a52eeb4-4d89-447f-a83f-4b0ac7b93c50 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791473749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executab le.1791473749 |
Directory | /workspace/32.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_lc_escalation.3293887504 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 56210400462 ps |
CPU time | 76.66 seconds |
Started | Jun 27 06:52:55 PM PDT 24 |
Finished | Jun 27 06:54:13 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-f1dc8b09-9f27-4f11-ac37-4c499091fe1b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293887504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_es calation.3293887504 |
Directory | /workspace/32.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_max_throughput.203274460 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 2031435728 ps |
CPU time | 6.64 seconds |
Started | Jun 27 06:52:50 PM PDT 24 |
Finished | Jun 27 06:52:59 PM PDT 24 |
Peak memory | 210948 kb |
Host | smart-4dbdff9c-5fb0-40be-855f-27314737564f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203274460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 32.sram_ctrl_max_throughput.203274460 |
Directory | /workspace/32.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_mem_partial_access.2750171792 |
Short name | T498 |
Test name | |
Test status | |
Simulation time | 2709087644 ps |
CPU time | 89.19 seconds |
Started | Jun 27 06:53:00 PM PDT 24 |
Finished | Jun 27 06:54:31 PM PDT 24 |
Peak memory | 211228 kb |
Host | smart-c9285f07-9492-4e13-87e0-be0acbb32e38 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750171792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_mem_partial_access.2750171792 |
Directory | /workspace/32.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_mem_walk.1470367468 |
Short name | T710 |
Test name | |
Test status | |
Simulation time | 17504796139 ps |
CPU time | 311.96 seconds |
Started | Jun 27 06:53:00 PM PDT 24 |
Finished | Jun 27 06:58:14 PM PDT 24 |
Peak memory | 211020 kb |
Host | smart-be28bda0-faf0-4077-b51b-ac11976fb77c |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470367468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr l_mem_walk.1470367468 |
Directory | /workspace/32.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_multiple_keys.2376402518 |
Short name | T478 |
Test name | |
Test status | |
Simulation time | 35350940698 ps |
CPU time | 1570.83 seconds |
Started | Jun 27 06:52:47 PM PDT 24 |
Finished | Jun 27 07:19:01 PM PDT 24 |
Peak memory | 377672 kb |
Host | smart-5cca229d-a92b-48eb-86d4-da1197d1798b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376402518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multi ple_keys.2376402518 |
Directory | /workspace/32.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_partial_access.2106095933 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 1798449929 ps |
CPU time | 113.25 seconds |
Started | Jun 27 06:52:48 PM PDT 24 |
Finished | Jun 27 06:54:44 PM PDT 24 |
Peak memory | 349004 kb |
Host | smart-41bba0d2-37bb-4690-a1ae-b5fa75cb5b15 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106095933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32. sram_ctrl_partial_access.2106095933 |
Directory | /workspace/32.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.1076631551 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 7484638714 ps |
CPU time | 396.61 seconds |
Started | Jun 27 06:52:55 PM PDT 24 |
Finished | Jun 27 06:59:33 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-7feed260-dc4a-488a-b327-c700c1490b11 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076631551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 32.sram_ctrl_partial_access_b2b.1076631551 |
Directory | /workspace/32.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_ram_cfg.2920902328 |
Short name | T794 |
Test name | |
Test status | |
Simulation time | 412556426 ps |
CPU time | 3.46 seconds |
Started | Jun 27 06:53:00 PM PDT 24 |
Finished | Jun 27 06:53:04 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-18223462-662e-487a-bc04-c3a019e9445c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920902328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.2920902328 |
Directory | /workspace/32.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_regwen.1052617741 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 2807897480 ps |
CPU time | 769.7 seconds |
Started | Jun 27 06:53:01 PM PDT 24 |
Finished | Jun 27 07:05:52 PM PDT 24 |
Peak memory | 352956 kb |
Host | smart-98039ff2-41aa-435d-8f63-2f3c9d457b37 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052617741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.1052617741 |
Directory | /workspace/32.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_smoke.1665973368 |
Short name | T893 |
Test name | |
Test status | |
Simulation time | 8686779402 ps |
CPU time | 18.14 seconds |
Started | Jun 27 06:52:49 PM PDT 24 |
Finished | Jun 27 06:53:09 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-00d25e18-eb95-4132-a07f-3dd88ad02257 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665973368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.1665973368 |
Directory | /workspace/32.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_all.1349939032 |
Short name | T792 |
Test name | |
Test status | |
Simulation time | 73486161017 ps |
CPU time | 6904.91 seconds |
Started | Jun 27 06:53:00 PM PDT 24 |
Finished | Jun 27 08:48:07 PM PDT 24 |
Peak memory | 381888 kb |
Host | smart-2495fa12-21de-4d98-b93d-b2ab83e1b797 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349939032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 32.sram_ctrl_stress_all.1349939032 |
Directory | /workspace/32.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.767780314 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 836986480 ps |
CPU time | 6.72 seconds |
Started | Jun 27 06:53:00 PM PDT 24 |
Finished | Jun 27 06:53:09 PM PDT 24 |
Peak memory | 211116 kb |
Host | smart-e634f447-41ee-4b03-b9ba-a085b4d7f051 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=767780314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.767780314 |
Directory | /workspace/32.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_pipeline.2497096641 |
Short name | T782 |
Test name | |
Test status | |
Simulation time | 27657803019 ps |
CPU time | 305.24 seconds |
Started | Jun 27 06:52:48 PM PDT 24 |
Finished | Jun 27 06:57:56 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-4f3434ea-864a-4ad4-a112-3177e869417b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497096641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_stress_pipeline.2497096641 |
Directory | /workspace/32.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.1671454665 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 3131865367 ps |
CPU time | 81.88 seconds |
Started | Jun 27 06:52:47 PM PDT 24 |
Finished | Jun 27 06:54:10 PM PDT 24 |
Peak memory | 327580 kb |
Host | smart-2877963f-874d-4354-8e01-a3c14db69a3f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671454665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.1671454665 |
Directory | /workspace/32.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_access_during_key_req.1703498228 |
Short name | T897 |
Test name | |
Test status | |
Simulation time | 55070277117 ps |
CPU time | 1197.41 seconds |
Started | Jun 27 06:53:01 PM PDT 24 |
Finished | Jun 27 07:13:01 PM PDT 24 |
Peak memory | 378744 kb |
Host | smart-6623d902-4c88-4501-a43a-3930bfe55b64 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703498228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 33.sram_ctrl_access_during_key_req.1703498228 |
Directory | /workspace/33.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_alert_test.484319418 |
Short name | T482 |
Test name | |
Test status | |
Simulation time | 12876801 ps |
CPU time | 0.66 seconds |
Started | Jun 27 06:53:11 PM PDT 24 |
Finished | Jun 27 06:53:13 PM PDT 24 |
Peak memory | 202600 kb |
Host | smart-5bb81ec4-52f1-4989-8c70-eee1783de580 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484319418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.484319418 |
Directory | /workspace/33.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_bijection.1610030466 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 67627410044 ps |
CPU time | 766.49 seconds |
Started | Jun 27 06:53:00 PM PDT 24 |
Finished | Jun 27 07:05:48 PM PDT 24 |
Peak memory | 202988 kb |
Host | smart-f038eec7-017a-4980-a8b6-25cd1479e0cd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610030466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection .1610030466 |
Directory | /workspace/33.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_executable.735736143 |
Short name | T671 |
Test name | |
Test status | |
Simulation time | 13545036680 ps |
CPU time | 973.13 seconds |
Started | Jun 27 06:53:01 PM PDT 24 |
Finished | Jun 27 07:09:16 PM PDT 24 |
Peak memory | 376684 kb |
Host | smart-01ab1f2e-cd4d-40f2-97e4-9244e417c702 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735736143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executabl e.735736143 |
Directory | /workspace/33.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_lc_escalation.4194974530 |
Short name | T858 |
Test name | |
Test status | |
Simulation time | 7449820678 ps |
CPU time | 13.44 seconds |
Started | Jun 27 06:53:00 PM PDT 24 |
Finished | Jun 27 06:53:15 PM PDT 24 |
Peak memory | 202764 kb |
Host | smart-94ae9026-92ef-4abe-9558-9fa1a3745775 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194974530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_es calation.4194974530 |
Directory | /workspace/33.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_max_throughput.2513675322 |
Short name | T803 |
Test name | |
Test status | |
Simulation time | 3083946380 ps |
CPU time | 109.61 seconds |
Started | Jun 27 06:53:00 PM PDT 24 |
Finished | Jun 27 06:54:51 PM PDT 24 |
Peak memory | 329632 kb |
Host | smart-29a843d6-8ec3-4536-b3c1-ee0f726c65a4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513675322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 33.sram_ctrl_max_throughput.2513675322 |
Directory | /workspace/33.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_mem_partial_access.2171733946 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 8988610288 ps |
CPU time | 82.42 seconds |
Started | Jun 27 06:53:12 PM PDT 24 |
Finished | Jun 27 06:54:36 PM PDT 24 |
Peak memory | 211100 kb |
Host | smart-2b8c4296-9a89-4f04-bde0-9f2e8133cc24 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171733946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_mem_partial_access.2171733946 |
Directory | /workspace/33.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_mem_walk.1267266858 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 14430891334 ps |
CPU time | 314.27 seconds |
Started | Jun 27 06:53:12 PM PDT 24 |
Finished | Jun 27 06:58:28 PM PDT 24 |
Peak memory | 210972 kb |
Host | smart-88228700-9136-477d-a585-dde2274c4013 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267266858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr l_mem_walk.1267266858 |
Directory | /workspace/33.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_multiple_keys.2953311092 |
Short name | T874 |
Test name | |
Test status | |
Simulation time | 16770873980 ps |
CPU time | 1166.52 seconds |
Started | Jun 27 06:53:01 PM PDT 24 |
Finished | Jun 27 07:12:29 PM PDT 24 |
Peak memory | 377420 kb |
Host | smart-f511c289-c577-4ee7-b9cc-96d0f005ffed |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953311092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi ple_keys.2953311092 |
Directory | /workspace/33.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_partial_access.320229584 |
Short name | T503 |
Test name | |
Test status | |
Simulation time | 4450895285 ps |
CPU time | 19.76 seconds |
Started | Jun 27 06:53:00 PM PDT 24 |
Finished | Jun 27 06:53:21 PM PDT 24 |
Peak memory | 202748 kb |
Host | smart-0651fb96-bcd0-491f-97cc-0e8bd477fa71 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320229584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.s ram_ctrl_partial_access.320229584 |
Directory | /workspace/33.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.2399666609 |
Short name | T927 |
Test name | |
Test status | |
Simulation time | 27422057404 ps |
CPU time | 309.69 seconds |
Started | Jun 27 06:53:02 PM PDT 24 |
Finished | Jun 27 06:58:13 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-2420e1fd-56de-448c-9194-81f243b3f25a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399666609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 33.sram_ctrl_partial_access_b2b.2399666609 |
Directory | /workspace/33.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_ram_cfg.880642674 |
Short name | T474 |
Test name | |
Test status | |
Simulation time | 1410497904 ps |
CPU time | 3.74 seconds |
Started | Jun 27 06:53:01 PM PDT 24 |
Finished | Jun 27 06:53:06 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-13db7997-ccb4-48aa-8b59-d4686e50adf8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880642674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.880642674 |
Directory | /workspace/33.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_regwen.4037540357 |
Short name | T533 |
Test name | |
Test status | |
Simulation time | 9835646355 ps |
CPU time | 397.5 seconds |
Started | Jun 27 06:53:00 PM PDT 24 |
Finished | Jun 27 06:59:39 PM PDT 24 |
Peak memory | 365464 kb |
Host | smart-dbf97431-e26c-472e-821a-7080e04645de |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037540357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.4037540357 |
Directory | /workspace/33.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_smoke.1404505443 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 16225481871 ps |
CPU time | 141.59 seconds |
Started | Jun 27 06:53:01 PM PDT 24 |
Finished | Jun 27 06:55:24 PM PDT 24 |
Peak memory | 357240 kb |
Host | smart-bf440ae9-fdf0-4a54-8c40-916600a0c76e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404505443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.1404505443 |
Directory | /workspace/33.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_all.3641753640 |
Short name | T527 |
Test name | |
Test status | |
Simulation time | 311569359303 ps |
CPU time | 5114.31 seconds |
Started | Jun 27 06:53:12 PM PDT 24 |
Finished | Jun 27 08:18:28 PM PDT 24 |
Peak memory | 381844 kb |
Host | smart-3ad66d4b-a4e7-4fcd-aeaa-d0ffbe9ae939 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641753640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 33.sram_ctrl_stress_all.3641753640 |
Directory | /workspace/33.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1076456374 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 1277396866 ps |
CPU time | 139.78 seconds |
Started | Jun 27 06:53:12 PM PDT 24 |
Finished | Jun 27 06:55:32 PM PDT 24 |
Peak memory | 365328 kb |
Host | smart-9735ac32-ac43-4bb3-a6d5-7e717d8b6987 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1076456374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.1076456374 |
Directory | /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_pipeline.3993839829 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 3651946189 ps |
CPU time | 295.95 seconds |
Started | Jun 27 06:53:00 PM PDT 24 |
Finished | Jun 27 06:57:56 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-6b3820a0-560a-45a6-b0bc-67069f70b2bc |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993839829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_stress_pipeline.3993839829 |
Directory | /workspace/33.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.271642894 |
Short name | T817 |
Test name | |
Test status | |
Simulation time | 724849436 ps |
CPU time | 11.66 seconds |
Started | Jun 27 06:53:00 PM PDT 24 |
Finished | Jun 27 06:53:13 PM PDT 24 |
Peak memory | 235524 kb |
Host | smart-ab3fc8a1-1a58-41e1-83f8-ab35fa03dc24 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271642894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 33.sram_ctrl_throughput_w_partial_write.271642894 |
Directory | /workspace/33.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_access_during_key_req.609614625 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 10517892119 ps |
CPU time | 1096.54 seconds |
Started | Jun 27 06:53:12 PM PDT 24 |
Finished | Jun 27 07:11:29 PM PDT 24 |
Peak memory | 379752 kb |
Host | smart-124736a6-03fc-4c4e-9beb-8ba82f1751cd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609614625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 34.sram_ctrl_access_during_key_req.609614625 |
Directory | /workspace/34.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_alert_test.1652292507 |
Short name | T755 |
Test name | |
Test status | |
Simulation time | 18205453 ps |
CPU time | 0.67 seconds |
Started | Jun 27 06:53:30 PM PDT 24 |
Finished | Jun 27 06:53:31 PM PDT 24 |
Peak memory | 202588 kb |
Host | smart-df86091a-b08a-434c-a4a1-9fae8fda000b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652292507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.1652292507 |
Directory | /workspace/34.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_bijection.361157911 |
Short name | T472 |
Test name | |
Test status | |
Simulation time | 29067875607 ps |
CPU time | 657.39 seconds |
Started | Jun 27 06:53:11 PM PDT 24 |
Finished | Jun 27 07:04:09 PM PDT 24 |
Peak memory | 203640 kb |
Host | smart-8ac45750-5b59-446d-834a-2fba76667ce5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361157911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection. 361157911 |
Directory | /workspace/34.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_executable.1145692357 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 61042544651 ps |
CPU time | 1036.54 seconds |
Started | Jun 27 06:53:14 PM PDT 24 |
Finished | Jun 27 07:10:32 PM PDT 24 |
Peak memory | 375656 kb |
Host | smart-d2a541ec-81f9-44e1-baee-009e6e556fd2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145692357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executab le.1145692357 |
Directory | /workspace/34.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_lc_escalation.1693630501 |
Short name | T932 |
Test name | |
Test status | |
Simulation time | 46541538325 ps |
CPU time | 59.29 seconds |
Started | Jun 27 06:53:13 PM PDT 24 |
Finished | Jun 27 06:54:13 PM PDT 24 |
Peak memory | 211112 kb |
Host | smart-d11b2815-a76d-4af7-a3b6-516b45a8de21 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693630501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_es calation.1693630501 |
Directory | /workspace/34.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_max_throughput.1033240871 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 1459976280 ps |
CPU time | 36.77 seconds |
Started | Jun 27 06:53:14 PM PDT 24 |
Finished | Jun 27 06:53:52 PM PDT 24 |
Peak memory | 306172 kb |
Host | smart-d5db32aa-ab8d-4411-8a2c-f87e0d4e79b7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033240871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 34.sram_ctrl_max_throughput.1033240871 |
Directory | /workspace/34.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_mem_partial_access.3187869337 |
Short name | T919 |
Test name | |
Test status | |
Simulation time | 22150819797 ps |
CPU time | 87.66 seconds |
Started | Jun 27 06:53:27 PM PDT 24 |
Finished | Jun 27 06:54:56 PM PDT 24 |
Peak memory | 211284 kb |
Host | smart-c2d33d8b-7cf0-41df-b326-b39ef653afa1 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187869337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_mem_partial_access.3187869337 |
Directory | /workspace/34.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_mem_walk.4015902289 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 28785480016 ps |
CPU time | 168.36 seconds |
Started | Jun 27 06:53:26 PM PDT 24 |
Finished | Jun 27 06:56:16 PM PDT 24 |
Peak memory | 211000 kb |
Host | smart-a9240b6c-4808-4882-9573-6fa4a275b4f3 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015902289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr l_mem_walk.4015902289 |
Directory | /workspace/34.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_multiple_keys.1528948786 |
Short name | T681 |
Test name | |
Test status | |
Simulation time | 7481603895 ps |
CPU time | 272.43 seconds |
Started | Jun 27 06:53:11 PM PDT 24 |
Finished | Jun 27 06:57:44 PM PDT 24 |
Peak memory | 353336 kb |
Host | smart-c0bb5811-2b34-4f3d-a238-b0bbc7e19afd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528948786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi ple_keys.1528948786 |
Directory | /workspace/34.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_partial_access.3973006883 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 993083733 ps |
CPU time | 186.99 seconds |
Started | Jun 27 06:53:13 PM PDT 24 |
Finished | Jun 27 06:56:21 PM PDT 24 |
Peak memory | 371432 kb |
Host | smart-a3df7161-efab-46cc-a977-6bf8d19ec6d4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973006883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34. sram_ctrl_partial_access.3973006883 |
Directory | /workspace/34.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.2957953677 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 54303837289 ps |
CPU time | 338.16 seconds |
Started | Jun 27 06:53:14 PM PDT 24 |
Finished | Jun 27 06:58:53 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-47e6f8ec-9f67-44dc-9e6d-994d1d2fb306 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957953677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 34.sram_ctrl_partial_access_b2b.2957953677 |
Directory | /workspace/34.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_ram_cfg.2157143349 |
Short name | T929 |
Test name | |
Test status | |
Simulation time | 348187134 ps |
CPU time | 3.13 seconds |
Started | Jun 27 06:53:13 PM PDT 24 |
Finished | Jun 27 06:53:17 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-3917307c-d090-42a2-afa0-2d2bb108345e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157143349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.2157143349 |
Directory | /workspace/34.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_regwen.1410890247 |
Short name | T566 |
Test name | |
Test status | |
Simulation time | 12550597337 ps |
CPU time | 1434 seconds |
Started | Jun 27 06:53:13 PM PDT 24 |
Finished | Jun 27 07:17:08 PM PDT 24 |
Peak memory | 379800 kb |
Host | smart-61ea3e3e-6e25-41e1-b740-c83e8da5b83a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410890247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.1410890247 |
Directory | /workspace/34.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_smoke.1014609458 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 2851975347 ps |
CPU time | 17.91 seconds |
Started | Jun 27 06:53:13 PM PDT 24 |
Finished | Jun 27 06:53:32 PM PDT 24 |
Peak memory | 202764 kb |
Host | smart-1bf2a15c-4b12-4aca-a7f6-4c32fabca5da |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014609458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.1014609458 |
Directory | /workspace/34.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_all.2315908574 |
Short name | T791 |
Test name | |
Test status | |
Simulation time | 221188794835 ps |
CPU time | 5512.36 seconds |
Started | Jun 27 06:53:30 PM PDT 24 |
Finished | Jun 27 08:25:23 PM PDT 24 |
Peak memory | 382864 kb |
Host | smart-7dbe7132-d4e9-4386-93af-5a73e6979b3b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315908574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 34.sram_ctrl_stress_all.2315908574 |
Directory | /workspace/34.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2642511688 |
Short name | T877 |
Test name | |
Test status | |
Simulation time | 300580607 ps |
CPU time | 9.2 seconds |
Started | Jun 27 06:53:27 PM PDT 24 |
Finished | Jun 27 06:53:37 PM PDT 24 |
Peak memory | 211120 kb |
Host | smart-cbe33af1-6173-4d9a-b7ae-d7992aef8154 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2642511688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.2642511688 |
Directory | /workspace/34.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_pipeline.1549278567 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 4847588484 ps |
CPU time | 294.57 seconds |
Started | Jun 27 06:53:10 PM PDT 24 |
Finished | Jun 27 06:58:05 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-1dccb1d7-8a46-4b57-a6c9-408c3713d4a4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549278567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_stress_pipeline.1549278567 |
Directory | /workspace/34.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.1017944165 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 713994819 ps |
CPU time | 28.47 seconds |
Started | Jun 27 06:53:13 PM PDT 24 |
Finished | Jun 27 06:53:43 PM PDT 24 |
Peak memory | 258676 kb |
Host | smart-bf74e669-aa56-4556-a68a-7af1b821ff10 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017944165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.1017944165 |
Directory | /workspace/34.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_access_during_key_req.4161039871 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 24914477861 ps |
CPU time | 946.65 seconds |
Started | Jun 27 06:53:26 PM PDT 24 |
Finished | Jun 27 07:09:14 PM PDT 24 |
Peak memory | 376676 kb |
Host | smart-1ea85911-7534-4c91-944b-a01f8022daa2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161039871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 35.sram_ctrl_access_during_key_req.4161039871 |
Directory | /workspace/35.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_alert_test.2228915714 |
Short name | T545 |
Test name | |
Test status | |
Simulation time | 16690710 ps |
CPU time | 0.72 seconds |
Started | Jun 27 06:53:40 PM PDT 24 |
Finished | Jun 27 06:53:42 PM PDT 24 |
Peak memory | 202748 kb |
Host | smart-81b75d86-bfa7-4ef7-b3c8-557eef422a20 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228915714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.2228915714 |
Directory | /workspace/35.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_bijection.1820306987 |
Short name | T729 |
Test name | |
Test status | |
Simulation time | 29032290173 ps |
CPU time | 2040.94 seconds |
Started | Jun 27 06:53:27 PM PDT 24 |
Finished | Jun 27 07:27:29 PM PDT 24 |
Peak memory | 203620 kb |
Host | smart-ff2eb8dd-08d6-46c7-a9d8-36ab8b0f2972 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820306987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection .1820306987 |
Directory | /workspace/35.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_executable.2604595620 |
Short name | T739 |
Test name | |
Test status | |
Simulation time | 8539271180 ps |
CPU time | 1388.39 seconds |
Started | Jun 27 06:53:26 PM PDT 24 |
Finished | Jun 27 07:16:36 PM PDT 24 |
Peak memory | 379824 kb |
Host | smart-c7c4a8a5-337e-4d3c-a98e-f4524e1fb108 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604595620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab le.2604595620 |
Directory | /workspace/35.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_lc_escalation.1954790603 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 28728201726 ps |
CPU time | 49.68 seconds |
Started | Jun 27 06:53:28 PM PDT 24 |
Finished | Jun 27 06:54:19 PM PDT 24 |
Peak memory | 211112 kb |
Host | smart-840b297c-a6a1-4359-b188-54d0b6700b21 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954790603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es calation.1954790603 |
Directory | /workspace/35.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_max_throughput.329342652 |
Short name | T640 |
Test name | |
Test status | |
Simulation time | 779018903 ps |
CPU time | 90.18 seconds |
Started | Jun 27 06:53:27 PM PDT 24 |
Finished | Jun 27 06:54:58 PM PDT 24 |
Peak memory | 334660 kb |
Host | smart-5bdf7c35-2342-4a17-b05c-04407eb8764c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329342652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 35.sram_ctrl_max_throughput.329342652 |
Directory | /workspace/35.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_mem_partial_access.2079268660 |
Short name | T746 |
Test name | |
Test status | |
Simulation time | 2949066096 ps |
CPU time | 88.04 seconds |
Started | Jun 27 06:53:40 PM PDT 24 |
Finished | Jun 27 06:55:09 PM PDT 24 |
Peak memory | 211012 kb |
Host | smart-35941977-92ef-433f-b501-fe7612c19ba2 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079268660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_mem_partial_access.2079268660 |
Directory | /workspace/35.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_mem_walk.2424234758 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 57634164430 ps |
CPU time | 314.84 seconds |
Started | Jun 27 06:53:40 PM PDT 24 |
Finished | Jun 27 06:58:56 PM PDT 24 |
Peak memory | 210980 kb |
Host | smart-a39337e2-6b88-4591-9263-2788a733d139 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424234758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctr l_mem_walk.2424234758 |
Directory | /workspace/35.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_multiple_keys.1537347130 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 46287402545 ps |
CPU time | 1041.47 seconds |
Started | Jun 27 06:53:26 PM PDT 24 |
Finished | Jun 27 07:10:49 PM PDT 24 |
Peak memory | 379788 kb |
Host | smart-f1e2813b-f533-4e82-b24f-68140469d5c6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537347130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multi ple_keys.1537347130 |
Directory | /workspace/35.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_partial_access.3592538345 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 3078265899 ps |
CPU time | 8.04 seconds |
Started | Jun 27 06:53:28 PM PDT 24 |
Finished | Jun 27 06:53:37 PM PDT 24 |
Peak memory | 205876 kb |
Host | smart-6d4ec447-52ff-4d7c-be9c-45a143116d84 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592538345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35. sram_ctrl_partial_access.3592538345 |
Directory | /workspace/35.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.349974664 |
Short name | T630 |
Test name | |
Test status | |
Simulation time | 11941695434 ps |
CPU time | 266.16 seconds |
Started | Jun 27 06:53:26 PM PDT 24 |
Finished | Jun 27 06:57:53 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-98a04d62-9e0b-4d91-8d22-89dae1152739 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349974664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 35.sram_ctrl_partial_access_b2b.349974664 |
Directory | /workspace/35.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_ram_cfg.3805804981 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 2788903018 ps |
CPU time | 3.89 seconds |
Started | Jun 27 06:53:40 PM PDT 24 |
Finished | Jun 27 06:53:45 PM PDT 24 |
Peak memory | 202948 kb |
Host | smart-13578a6f-b1dd-4c66-b574-e3997773ad26 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805804981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.3805804981 |
Directory | /workspace/35.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_regwen.1840332455 |
Short name | T635 |
Test name | |
Test status | |
Simulation time | 56032651695 ps |
CPU time | 602.12 seconds |
Started | Jun 27 06:53:27 PM PDT 24 |
Finished | Jun 27 07:03:30 PM PDT 24 |
Peak memory | 369540 kb |
Host | smart-6083caf6-5bd1-4da6-ad95-1e9e059703cf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840332455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.1840332455 |
Directory | /workspace/35.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_smoke.4095709561 |
Short name | T783 |
Test name | |
Test status | |
Simulation time | 845820331 ps |
CPU time | 5.51 seconds |
Started | Jun 27 06:53:26 PM PDT 24 |
Finished | Jun 27 06:53:32 PM PDT 24 |
Peak memory | 202740 kb |
Host | smart-22f94cc8-f06e-4f9f-8b58-a013a93d6d39 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095709561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.4095709561 |
Directory | /workspace/35.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_all.3786514548 |
Short name | T581 |
Test name | |
Test status | |
Simulation time | 54808286982 ps |
CPU time | 4263.51 seconds |
Started | Jun 27 06:53:39 PM PDT 24 |
Finished | Jun 27 08:04:44 PM PDT 24 |
Peak memory | 382928 kb |
Host | smart-2b273d46-ca18-4de5-a13e-8b70b819175e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786514548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 35.sram_ctrl_stress_all.3786514548 |
Directory | /workspace/35.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_pipeline.3712185878 |
Short name | T859 |
Test name | |
Test status | |
Simulation time | 5021773242 ps |
CPU time | 291.46 seconds |
Started | Jun 27 06:53:29 PM PDT 24 |
Finished | Jun 27 06:58:21 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-5f76ec5c-68e5-4100-94ce-ccc482df47d5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712185878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_stress_pipeline.3712185878 |
Directory | /workspace/35.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.35551024 |
Short name | T492 |
Test name | |
Test status | |
Simulation time | 760414258 ps |
CPU time | 46.2 seconds |
Started | Jun 27 06:53:26 PM PDT 24 |
Finished | Jun 27 06:54:14 PM PDT 24 |
Peak memory | 289688 kb |
Host | smart-b81542d3-5fae-4eef-bd76-82293b5eac91 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35551024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 35.sram_ctrl_throughput_w_partial_write.35551024 |
Directory | /workspace/35.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_access_during_key_req.1949668856 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 30949605092 ps |
CPU time | 709.12 seconds |
Started | Jun 27 06:53:40 PM PDT 24 |
Finished | Jun 27 07:05:30 PM PDT 24 |
Peak memory | 378736 kb |
Host | smart-9b30d48a-54a2-4db4-ac3d-d78ad6e50980 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949668856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 36.sram_ctrl_access_during_key_req.1949668856 |
Directory | /workspace/36.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_alert_test.1278870890 |
Short name | T723 |
Test name | |
Test status | |
Simulation time | 24474657 ps |
CPU time | 0.66 seconds |
Started | Jun 27 06:53:52 PM PDT 24 |
Finished | Jun 27 06:53:55 PM PDT 24 |
Peak memory | 202588 kb |
Host | smart-2053bf9c-fd33-4815-a372-e51c8575bc3c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278870890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.1278870890 |
Directory | /workspace/36.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_bijection.1282480455 |
Short name | T668 |
Test name | |
Test status | |
Simulation time | 111452715012 ps |
CPU time | 2030.3 seconds |
Started | Jun 27 06:53:38 PM PDT 24 |
Finished | Jun 27 07:27:29 PM PDT 24 |
Peak memory | 203792 kb |
Host | smart-a2245824-75cd-4f0d-8094-b8740517d264 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282480455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection .1282480455 |
Directory | /workspace/36.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_executable.660604072 |
Short name | T835 |
Test name | |
Test status | |
Simulation time | 54919111917 ps |
CPU time | 863.35 seconds |
Started | Jun 27 06:53:51 PM PDT 24 |
Finished | Jun 27 07:08:16 PM PDT 24 |
Peak memory | 378736 kb |
Host | smart-c80ea3e0-8d18-4539-823f-f6ff33d6ff63 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660604072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executabl e.660604072 |
Directory | /workspace/36.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_lc_escalation.738225391 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 24806137819 ps |
CPU time | 36.35 seconds |
Started | Jun 27 06:53:40 PM PDT 24 |
Finished | Jun 27 06:54:17 PM PDT 24 |
Peak memory | 211124 kb |
Host | smart-481a067d-e0ef-4426-8244-b5d19526c9af |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738225391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_esc alation.738225391 |
Directory | /workspace/36.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_max_throughput.3052528791 |
Short name | T790 |
Test name | |
Test status | |
Simulation time | 1468301229 ps |
CPU time | 36.99 seconds |
Started | Jun 27 06:53:40 PM PDT 24 |
Finished | Jun 27 06:54:18 PM PDT 24 |
Peak memory | 284744 kb |
Host | smart-af552eac-c869-4ff6-8cac-7a613e157e80 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052528791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 36.sram_ctrl_max_throughput.3052528791 |
Directory | /workspace/36.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_mem_partial_access.3971250900 |
Short name | T604 |
Test name | |
Test status | |
Simulation time | 2782519661 ps |
CPU time | 83.49 seconds |
Started | Jun 27 06:53:52 PM PDT 24 |
Finished | Jun 27 06:55:18 PM PDT 24 |
Peak memory | 211032 kb |
Host | smart-60d4cfd9-406d-4f16-af07-c206f0f0f0b6 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971250900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_mem_partial_access.3971250900 |
Directory | /workspace/36.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_mem_walk.4180575447 |
Short name | T715 |
Test name | |
Test status | |
Simulation time | 27718837480 ps |
CPU time | 173.25 seconds |
Started | Jun 27 06:53:52 PM PDT 24 |
Finished | Jun 27 06:56:46 PM PDT 24 |
Peak memory | 203628 kb |
Host | smart-e692d622-8d39-4b3f-8bab-5db8a86bf39c |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180575447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr l_mem_walk.4180575447 |
Directory | /workspace/36.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_multiple_keys.1412330370 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 20140304822 ps |
CPU time | 757.52 seconds |
Started | Jun 27 06:53:39 PM PDT 24 |
Finished | Jun 27 07:06:18 PM PDT 24 |
Peak memory | 377696 kb |
Host | smart-ec2326f4-7da4-4930-a107-bb3f30a914b1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412330370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi ple_keys.1412330370 |
Directory | /workspace/36.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_partial_access.348663424 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 1828070858 ps |
CPU time | 28.08 seconds |
Started | Jun 27 06:53:41 PM PDT 24 |
Finished | Jun 27 06:54:10 PM PDT 24 |
Peak memory | 202716 kb |
Host | smart-ae5d27bc-5c0b-458b-9e31-46f251164b6f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348663424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.s ram_ctrl_partial_access.348663424 |
Directory | /workspace/36.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.925342758 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 150725658211 ps |
CPU time | 511.25 seconds |
Started | Jun 27 06:53:38 PM PDT 24 |
Finished | Jun 27 07:02:09 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-9dbfee83-4ff8-4457-9591-7d3b12b52f0d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925342758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 36.sram_ctrl_partial_access_b2b.925342758 |
Directory | /workspace/36.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_ram_cfg.233181910 |
Short name | T740 |
Test name | |
Test status | |
Simulation time | 900843928 ps |
CPU time | 3.31 seconds |
Started | Jun 27 06:53:50 PM PDT 24 |
Finished | Jun 27 06:53:54 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-093c4a5e-5265-4463-9da0-49f9b872a9b5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233181910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.233181910 |
Directory | /workspace/36.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_regwen.279641080 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 22211854435 ps |
CPU time | 495.41 seconds |
Started | Jun 27 06:53:52 PM PDT 24 |
Finished | Jun 27 07:02:10 PM PDT 24 |
Peak memory | 377736 kb |
Host | smart-12b9044e-1484-441a-9472-c72e4d6b91b8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279641080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.279641080 |
Directory | /workspace/36.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_smoke.1350059720 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 6223788329 ps |
CPU time | 7.19 seconds |
Started | Jun 27 06:53:40 PM PDT 24 |
Finished | Jun 27 06:53:48 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-20976f18-c332-4316-a03c-91d74f5b61bc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350059720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.1350059720 |
Directory | /workspace/36.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_all.2795395086 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 114414394601 ps |
CPU time | 4184.64 seconds |
Started | Jun 27 06:53:52 PM PDT 24 |
Finished | Jun 27 08:03:37 PM PDT 24 |
Peak memory | 382788 kb |
Host | smart-69f54e05-c767-484f-acf7-3595db8fe0df |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795395086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 36.sram_ctrl_stress_all.2795395086 |
Directory | /workspace/36.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.2716754966 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 264634091 ps |
CPU time | 7.73 seconds |
Started | Jun 27 06:53:52 PM PDT 24 |
Finished | Jun 27 06:54:02 PM PDT 24 |
Peak memory | 211060 kb |
Host | smart-f74b400b-1d09-4979-b405-d5fa67f8b433 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2716754966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.2716754966 |
Directory | /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_pipeline.1146951046 |
Short name | T829 |
Test name | |
Test status | |
Simulation time | 7948156819 ps |
CPU time | 343.22 seconds |
Started | Jun 27 06:53:41 PM PDT 24 |
Finished | Jun 27 06:59:25 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-71e4659a-bb1d-4cea-bc1c-f5047cb19eec |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146951046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_stress_pipeline.1146951046 |
Directory | /workspace/36.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.3371875689 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 14172026754 ps |
CPU time | 24.69 seconds |
Started | Jun 27 06:53:42 PM PDT 24 |
Finished | Jun 27 06:54:07 PM PDT 24 |
Peak memory | 268216 kb |
Host | smart-b8341be0-47be-48e4-9e46-248a12d6f696 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371875689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.3371875689 |
Directory | /workspace/36.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_access_during_key_req.1728146796 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 10787274927 ps |
CPU time | 867.09 seconds |
Started | Jun 27 06:54:08 PM PDT 24 |
Finished | Jun 27 07:08:36 PM PDT 24 |
Peak memory | 375652 kb |
Host | smart-e9315ee0-8672-494c-9da8-59c6297ec229 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728146796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 37.sram_ctrl_access_during_key_req.1728146796 |
Directory | /workspace/37.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_alert_test.3934045275 |
Short name | T857 |
Test name | |
Test status | |
Simulation time | 15843270 ps |
CPU time | 0.68 seconds |
Started | Jun 27 06:54:08 PM PDT 24 |
Finished | Jun 27 06:54:10 PM PDT 24 |
Peak memory | 202552 kb |
Host | smart-39b6c126-af25-488d-8713-59323f090df5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934045275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.3934045275 |
Directory | /workspace/37.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_bijection.14650701 |
Short name | T523 |
Test name | |
Test status | |
Simulation time | 132424955454 ps |
CPU time | 2167.28 seconds |
Started | Jun 27 06:53:52 PM PDT 24 |
Finished | Jun 27 07:30:02 PM PDT 24 |
Peak memory | 203780 kb |
Host | smart-e4136be7-8861-4aa5-b305-96d01a033e3f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14650701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection.14650701 |
Directory | /workspace/37.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_executable.478885975 |
Short name | T525 |
Test name | |
Test status | |
Simulation time | 25343200041 ps |
CPU time | 624.07 seconds |
Started | Jun 27 06:54:10 PM PDT 24 |
Finished | Jun 27 07:04:35 PM PDT 24 |
Peak memory | 375740 kb |
Host | smart-2262f413-7ffd-4b24-9197-d371a4d09e03 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478885975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executabl e.478885975 |
Directory | /workspace/37.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_lc_escalation.1425916684 |
Short name | T491 |
Test name | |
Test status | |
Simulation time | 83943477012 ps |
CPU time | 98.36 seconds |
Started | Jun 27 06:54:09 PM PDT 24 |
Finished | Jun 27 06:55:49 PM PDT 24 |
Peak memory | 211088 kb |
Host | smart-3075e9bb-e8f0-4d0f-96ba-3aab6c845c1a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425916684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_es calation.1425916684 |
Directory | /workspace/37.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_max_throughput.3645834509 |
Short name | T763 |
Test name | |
Test status | |
Simulation time | 1584030781 ps |
CPU time | 144.11 seconds |
Started | Jun 27 06:54:09 PM PDT 24 |
Finished | Jun 27 06:56:35 PM PDT 24 |
Peak memory | 363216 kb |
Host | smart-7b884b4e-c9d2-4aa6-9cd3-af2e25a1af5d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645834509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 37.sram_ctrl_max_throughput.3645834509 |
Directory | /workspace/37.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_mem_partial_access.971283805 |
Short name | T772 |
Test name | |
Test status | |
Simulation time | 6554097198 ps |
CPU time | 136.13 seconds |
Started | Jun 27 06:54:11 PM PDT 24 |
Finished | Jun 27 06:56:28 PM PDT 24 |
Peak memory | 211084 kb |
Host | smart-99de8975-34c2-4701-bbe6-900c703e70a4 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971283805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37 .sram_ctrl_mem_partial_access.971283805 |
Directory | /workspace/37.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_mem_walk.1732858857 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 344454472768 ps |
CPU time | 489.17 seconds |
Started | Jun 27 06:54:08 PM PDT 24 |
Finished | Jun 27 07:02:19 PM PDT 24 |
Peak memory | 211016 kb |
Host | smart-6e250f80-81ea-4cee-af90-7d95b05d1b23 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732858857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr l_mem_walk.1732858857 |
Directory | /workspace/37.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_multiple_keys.615184595 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 38026170064 ps |
CPU time | 739.73 seconds |
Started | Jun 27 06:53:52 PM PDT 24 |
Finished | Jun 27 07:06:14 PM PDT 24 |
Peak memory | 376692 kb |
Host | smart-97f1361c-d9f2-4717-b064-973c058e21be |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615184595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multip le_keys.615184595 |
Directory | /workspace/37.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_partial_access.3298510975 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 1341530186 ps |
CPU time | 139.84 seconds |
Started | Jun 27 06:54:08 PM PDT 24 |
Finished | Jun 27 06:56:29 PM PDT 24 |
Peak memory | 367300 kb |
Host | smart-61184e0e-aa1d-4e08-b575-092cc5dc1a27 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298510975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37. sram_ctrl_partial_access.3298510975 |
Directory | /workspace/37.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.2712923777 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 25460013403 ps |
CPU time | 327.67 seconds |
Started | Jun 27 06:54:12 PM PDT 24 |
Finished | Jun 27 06:59:41 PM PDT 24 |
Peak memory | 202508 kb |
Host | smart-0f06d66e-8d5e-4f37-8bb8-4a4e285395d9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712923777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 37.sram_ctrl_partial_access_b2b.2712923777 |
Directory | /workspace/37.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_ram_cfg.3245787750 |
Short name | T627 |
Test name | |
Test status | |
Simulation time | 2576842737 ps |
CPU time | 3.52 seconds |
Started | Jun 27 06:54:08 PM PDT 24 |
Finished | Jun 27 06:54:13 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-b3c2b0bb-61fc-454e-9654-ab49a0b4fb83 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245787750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.3245787750 |
Directory | /workspace/37.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_regwen.3497570622 |
Short name | T852 |
Test name | |
Test status | |
Simulation time | 3983988844 ps |
CPU time | 121.39 seconds |
Started | Jun 27 06:54:09 PM PDT 24 |
Finished | Jun 27 06:56:12 PM PDT 24 |
Peak memory | 298460 kb |
Host | smart-deebffb7-35cc-4195-80d8-b4551c66ed7a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497570622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.3497570622 |
Directory | /workspace/37.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_smoke.1227111928 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 3254903629 ps |
CPU time | 8.24 seconds |
Started | Jun 27 06:53:52 PM PDT 24 |
Finished | Jun 27 06:54:02 PM PDT 24 |
Peak memory | 209136 kb |
Host | smart-b03f944a-ea48-4500-8041-34b4b6222be3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227111928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.1227111928 |
Directory | /workspace/37.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.4138866685 |
Short name | T536 |
Test name | |
Test status | |
Simulation time | 897407352 ps |
CPU time | 24.13 seconds |
Started | Jun 27 06:54:10 PM PDT 24 |
Finished | Jun 27 06:54:35 PM PDT 24 |
Peak memory | 211108 kb |
Host | smart-d1c4da82-ab79-45a5-82c3-44d99cc2b5e4 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4138866685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.4138866685 |
Directory | /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_pipeline.1437409228 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 14098614078 ps |
CPU time | 283.36 seconds |
Started | Jun 27 06:54:09 PM PDT 24 |
Finished | Jun 27 06:58:54 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-41061f46-95ff-4b18-a95e-9ad4d1361557 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437409228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_stress_pipeline.1437409228 |
Directory | /workspace/37.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.1261400803 |
Short name | T641 |
Test name | |
Test status | |
Simulation time | 1787612873 ps |
CPU time | 72.19 seconds |
Started | Jun 27 06:54:09 PM PDT 24 |
Finished | Jun 27 06:55:23 PM PDT 24 |
Peak memory | 320260 kb |
Host | smart-6627feba-a1cc-4e5e-824c-68d21afc3721 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261400803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.1261400803 |
Directory | /workspace/37.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_access_during_key_req.2617643045 |
Short name | T577 |
Test name | |
Test status | |
Simulation time | 10635727234 ps |
CPU time | 324.34 seconds |
Started | Jun 27 06:54:14 PM PDT 24 |
Finished | Jun 27 06:59:39 PM PDT 24 |
Peak memory | 374560 kb |
Host | smart-c412a327-ecc6-4dba-8854-45a9621290b9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617643045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 38.sram_ctrl_access_during_key_req.2617643045 |
Directory | /workspace/38.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_alert_test.2165731299 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 37775234 ps |
CPU time | 0.67 seconds |
Started | Jun 27 06:54:26 PM PDT 24 |
Finished | Jun 27 06:54:28 PM PDT 24 |
Peak memory | 202616 kb |
Host | smart-3edea183-5666-4360-8b17-80fb7cd3df25 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165731299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.2165731299 |
Directory | /workspace/38.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_bijection.2067714159 |
Short name | T820 |
Test name | |
Test status | |
Simulation time | 52613583349 ps |
CPU time | 1582.28 seconds |
Started | Jun 27 06:54:16 PM PDT 24 |
Finished | Jun 27 07:20:40 PM PDT 24 |
Peak memory | 203620 kb |
Host | smart-12c12694-ea64-4e88-a7d7-b79c30f689d5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067714159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection .2067714159 |
Directory | /workspace/38.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_executable.789809792 |
Short name | T587 |
Test name | |
Test status | |
Simulation time | 113411304386 ps |
CPU time | 1966.59 seconds |
Started | Jun 27 06:54:14 PM PDT 24 |
Finished | Jun 27 07:27:02 PM PDT 24 |
Peak memory | 380852 kb |
Host | smart-708efffa-1be8-4fbc-911d-a72b6dd8d56f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789809792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executabl e.789809792 |
Directory | /workspace/38.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_lc_escalation.1336924142 |
Short name | T553 |
Test name | |
Test status | |
Simulation time | 14959697084 ps |
CPU time | 91.64 seconds |
Started | Jun 27 06:54:14 PM PDT 24 |
Finished | Jun 27 06:55:47 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-75c23e16-73c3-488b-9a76-565e4c81e0c6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336924142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es calation.1336924142 |
Directory | /workspace/38.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_max_throughput.284830954 |
Short name | T638 |
Test name | |
Test status | |
Simulation time | 1499566627 ps |
CPU time | 46.08 seconds |
Started | Jun 27 06:54:16 PM PDT 24 |
Finished | Jun 27 06:55:03 PM PDT 24 |
Peak memory | 288836 kb |
Host | smart-a22321e4-4a29-4704-bcbf-ca710ef1c612 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284830954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 38.sram_ctrl_max_throughput.284830954 |
Directory | /workspace/38.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_mem_partial_access.3312327122 |
Short name | T934 |
Test name | |
Test status | |
Simulation time | 1402281761 ps |
CPU time | 75.2 seconds |
Started | Jun 27 06:54:27 PM PDT 24 |
Finished | Jun 27 06:55:43 PM PDT 24 |
Peak memory | 211132 kb |
Host | smart-e0fb3478-3326-4c2f-9b95-3580f1f794ad |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312327122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_mem_partial_access.3312327122 |
Directory | /workspace/38.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_mem_walk.1801938958 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 31429442212 ps |
CPU time | 173.11 seconds |
Started | Jun 27 06:54:27 PM PDT 24 |
Finished | Jun 27 06:57:22 PM PDT 24 |
Peak memory | 210940 kb |
Host | smart-eb3acb43-d023-4c38-86fb-59c596234027 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801938958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr l_mem_walk.1801938958 |
Directory | /workspace/38.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_multiple_keys.3409123497 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 22638104838 ps |
CPU time | 591.15 seconds |
Started | Jun 27 06:54:14 PM PDT 24 |
Finished | Jun 27 07:04:06 PM PDT 24 |
Peak memory | 338916 kb |
Host | smart-26a9b488-effb-4f8e-91d7-b3ac613e447d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409123497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multi ple_keys.3409123497 |
Directory | /workspace/38.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_partial_access.842039612 |
Short name | T555 |
Test name | |
Test status | |
Simulation time | 496408985 ps |
CPU time | 10.83 seconds |
Started | Jun 27 06:54:17 PM PDT 24 |
Finished | Jun 27 06:54:29 PM PDT 24 |
Peak memory | 202740 kb |
Host | smart-ef1a5b9e-ee2e-4680-af62-58d2f6a26f20 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842039612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.s ram_ctrl_partial_access.842039612 |
Directory | /workspace/38.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.1376785009 |
Short name | T662 |
Test name | |
Test status | |
Simulation time | 24961368002 ps |
CPU time | 268.36 seconds |
Started | Jun 27 06:54:16 PM PDT 24 |
Finished | Jun 27 06:58:46 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-2503d9e4-567c-4520-8e0a-b90aecf32b6b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376785009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 38.sram_ctrl_partial_access_b2b.1376785009 |
Directory | /workspace/38.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_ram_cfg.3132153345 |
Short name | T560 |
Test name | |
Test status | |
Simulation time | 351456726 ps |
CPU time | 3.46 seconds |
Started | Jun 27 06:54:26 PM PDT 24 |
Finished | Jun 27 06:54:31 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-da9fd976-c63b-4573-ab68-c406db743f5c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132153345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.3132153345 |
Directory | /workspace/38.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_regwen.1174749634 |
Short name | T825 |
Test name | |
Test status | |
Simulation time | 12377487799 ps |
CPU time | 1231.81 seconds |
Started | Jun 27 06:54:14 PM PDT 24 |
Finished | Jun 27 07:14:47 PM PDT 24 |
Peak memory | 378696 kb |
Host | smart-204cbfcb-c117-485d-a40b-21736e1a7f1d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174749634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.1174749634 |
Directory | /workspace/38.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_smoke.2591075926 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 382572271 ps |
CPU time | 19.03 seconds |
Started | Jun 27 06:54:12 PM PDT 24 |
Finished | Jun 27 06:54:32 PM PDT 24 |
Peak memory | 263156 kb |
Host | smart-ab715352-f2f6-4e23-b1b7-5f92b43b0c67 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591075926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.2591075926 |
Directory | /workspace/38.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_all.4011802258 |
Short name | T670 |
Test name | |
Test status | |
Simulation time | 109282860435 ps |
CPU time | 1187.98 seconds |
Started | Jun 27 06:54:27 PM PDT 24 |
Finished | Jun 27 07:14:16 PM PDT 24 |
Peak memory | 380876 kb |
Host | smart-06e9aa01-7a03-4456-9bed-59d88edb00ec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011802258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 38.sram_ctrl_stress_all.4011802258 |
Directory | /workspace/38.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3261803029 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 1526422494 ps |
CPU time | 19.85 seconds |
Started | Jun 27 06:54:27 PM PDT 24 |
Finished | Jun 27 06:54:48 PM PDT 24 |
Peak memory | 211064 kb |
Host | smart-ee5bd7b3-0e0a-497a-b05d-5be0e74ba1c7 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3261803029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.3261803029 |
Directory | /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_pipeline.1828039321 |
Short name | T547 |
Test name | |
Test status | |
Simulation time | 5565374528 ps |
CPU time | 335.4 seconds |
Started | Jun 27 06:54:14 PM PDT 24 |
Finished | Jun 27 06:59:51 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-5bf3f162-1ba7-4687-8c84-e3f4fe7f228f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828039321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_stress_pipeline.1828039321 |
Directory | /workspace/38.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.758840493 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 678393644 ps |
CPU time | 6.47 seconds |
Started | Jun 27 06:54:14 PM PDT 24 |
Finished | Jun 27 06:54:22 PM PDT 24 |
Peak memory | 210940 kb |
Host | smart-45865b45-603b-4aa0-ab35-ff26884e1ec1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758840493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 38.sram_ctrl_throughput_w_partial_write.758840493 |
Directory | /workspace/38.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_access_during_key_req.4001984098 |
Short name | T720 |
Test name | |
Test status | |
Simulation time | 9595205339 ps |
CPU time | 920.98 seconds |
Started | Jun 27 06:54:26 PM PDT 24 |
Finished | Jun 27 07:09:48 PM PDT 24 |
Peak memory | 376672 kb |
Host | smart-5f426b87-a9a6-457c-8d29-30a919162638 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001984098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 39.sram_ctrl_access_during_key_req.4001984098 |
Directory | /workspace/39.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_alert_test.2672454725 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 13293700 ps |
CPU time | 0.67 seconds |
Started | Jun 27 06:54:46 PM PDT 24 |
Finished | Jun 27 06:54:47 PM PDT 24 |
Peak memory | 202380 kb |
Host | smart-5664c5dc-6091-4ac1-9a0a-71e60f18b755 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672454725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.2672454725 |
Directory | /workspace/39.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_bijection.2851729723 |
Short name | T521 |
Test name | |
Test status | |
Simulation time | 405133325448 ps |
CPU time | 2380.91 seconds |
Started | Jun 27 06:54:26 PM PDT 24 |
Finished | Jun 27 07:34:09 PM PDT 24 |
Peak memory | 203116 kb |
Host | smart-6798ac89-282a-42a1-a1ca-eda3f4ffff20 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851729723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection .2851729723 |
Directory | /workspace/39.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_executable.3479671261 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 36543601206 ps |
CPU time | 259.89 seconds |
Started | Jun 27 06:54:27 PM PDT 24 |
Finished | Jun 27 06:58:48 PM PDT 24 |
Peak memory | 369216 kb |
Host | smart-71c1dfcc-7ec4-478a-b1df-c94140983345 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479671261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executab le.3479671261 |
Directory | /workspace/39.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_lc_escalation.3654011895 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 44300317310 ps |
CPU time | 49.74 seconds |
Started | Jun 27 06:54:27 PM PDT 24 |
Finished | Jun 27 06:55:18 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-aed32d0c-38c5-4821-ac47-64fe94d4f0f8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654011895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es calation.3654011895 |
Directory | /workspace/39.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_max_throughput.898771029 |
Short name | T700 |
Test name | |
Test status | |
Simulation time | 3192441540 ps |
CPU time | 57.71 seconds |
Started | Jun 27 06:54:27 PM PDT 24 |
Finished | Jun 27 06:55:26 PM PDT 24 |
Peak memory | 315964 kb |
Host | smart-a95e8bfe-dffd-4870-b0fe-d6695f1a6274 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898771029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 39.sram_ctrl_max_throughput.898771029 |
Directory | /workspace/39.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_mem_partial_access.877181474 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 32964370518 ps |
CPU time | 89.57 seconds |
Started | Jun 27 06:54:44 PM PDT 24 |
Finished | Jun 27 06:56:15 PM PDT 24 |
Peak memory | 213004 kb |
Host | smart-92598750-29a2-4d7b-912e-16ee4ab2fa80 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877181474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39 .sram_ctrl_mem_partial_access.877181474 |
Directory | /workspace/39.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_mem_walk.1728865970 |
Short name | T457 |
Test name | |
Test status | |
Simulation time | 14445928380 ps |
CPU time | 178.47 seconds |
Started | Jun 27 06:54:43 PM PDT 24 |
Finished | Jun 27 06:57:43 PM PDT 24 |
Peak memory | 210972 kb |
Host | smart-16f8b4d8-02f3-47b5-a0b7-3daf8ad2a28b |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728865970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr l_mem_walk.1728865970 |
Directory | /workspace/39.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_multiple_keys.3308624710 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 8432915480 ps |
CPU time | 688.3 seconds |
Started | Jun 27 06:54:27 PM PDT 24 |
Finished | Jun 27 07:05:56 PM PDT 24 |
Peak memory | 369484 kb |
Host | smart-6e4d4e6c-2f67-4c37-a756-0e8ee8c4c2f1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308624710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi ple_keys.3308624710 |
Directory | /workspace/39.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_partial_access.710866600 |
Short name | T810 |
Test name | |
Test status | |
Simulation time | 4157625554 ps |
CPU time | 17.86 seconds |
Started | Jun 27 06:54:26 PM PDT 24 |
Finished | Jun 27 06:54:46 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-a5778fa0-99c9-477e-a919-f304695ebeb4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710866600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.s ram_ctrl_partial_access.710866600 |
Directory | /workspace/39.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.2073931418 |
Short name | T727 |
Test name | |
Test status | |
Simulation time | 61411724084 ps |
CPU time | 409.8 seconds |
Started | Jun 27 06:54:25 PM PDT 24 |
Finished | Jun 27 07:01:16 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-1f516ba7-505f-458c-979d-d6713b9120f5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073931418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 39.sram_ctrl_partial_access_b2b.2073931418 |
Directory | /workspace/39.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_ram_cfg.888975569 |
Short name | T748 |
Test name | |
Test status | |
Simulation time | 707657655 ps |
CPU time | 3.47 seconds |
Started | Jun 27 06:54:28 PM PDT 24 |
Finished | Jun 27 06:54:32 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-1f1d7274-1720-436d-a6c1-1a3c59a6b8fd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888975569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.888975569 |
Directory | /workspace/39.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_regwen.2402530295 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 2770173876 ps |
CPU time | 124.48 seconds |
Started | Jun 27 06:54:27 PM PDT 24 |
Finished | Jun 27 06:56:33 PM PDT 24 |
Peak memory | 307260 kb |
Host | smart-5fa5fb90-8846-4711-941a-318166ed5d1a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402530295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.2402530295 |
Directory | /workspace/39.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_smoke.4141885151 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 1198042068 ps |
CPU time | 101.34 seconds |
Started | Jun 27 06:54:25 PM PDT 24 |
Finished | Jun 27 06:56:07 PM PDT 24 |
Peak memory | 331552 kb |
Host | smart-e496c70b-8879-49f5-b0b8-21f9460eaabd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141885151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.4141885151 |
Directory | /workspace/39.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_all.2626923458 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 285253090242 ps |
CPU time | 9548.51 seconds |
Started | Jun 27 06:54:43 PM PDT 24 |
Finished | Jun 27 09:33:54 PM PDT 24 |
Peak memory | 380812 kb |
Host | smart-d1e4ec50-7d0c-48ab-8c49-ab09b2cd1901 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626923458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 39.sram_ctrl_stress_all.2626923458 |
Directory | /workspace/39.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1757804374 |
Short name | T520 |
Test name | |
Test status | |
Simulation time | 1350266618 ps |
CPU time | 20.3 seconds |
Started | Jun 27 06:54:43 PM PDT 24 |
Finished | Jun 27 06:55:04 PM PDT 24 |
Peak memory | 211064 kb |
Host | smart-45512a78-26aa-4788-9434-51b96d8e5c7f |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1757804374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.1757804374 |
Directory | /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_pipeline.728245122 |
Short name | T650 |
Test name | |
Test status | |
Simulation time | 9440533461 ps |
CPU time | 286.69 seconds |
Started | Jun 27 06:54:25 PM PDT 24 |
Finished | Jun 27 06:59:12 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-e7f51c23-c1bc-4607-91bc-42e8ad5a5994 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728245122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39 .sram_ctrl_stress_pipeline.728245122 |
Directory | /workspace/39.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.1278367794 |
Short name | T675 |
Test name | |
Test status | |
Simulation time | 1487139383 ps |
CPU time | 36.92 seconds |
Started | Jun 27 06:54:27 PM PDT 24 |
Finished | Jun 27 06:55:06 PM PDT 24 |
Peak memory | 290468 kb |
Host | smart-f98feeed-d6b8-4725-9fe5-30796c69646c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278367794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.1278367794 |
Directory | /workspace/39.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_access_during_key_req.4099159626 |
Short name | T821 |
Test name | |
Test status | |
Simulation time | 18278809999 ps |
CPU time | 1495.25 seconds |
Started | Jun 27 06:49:24 PM PDT 24 |
Finished | Jun 27 07:14:21 PM PDT 24 |
Peak memory | 378956 kb |
Host | smart-2666dddd-2672-447d-bd92-f4172a726baa |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099159626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_access_during_key_req.4099159626 |
Directory | /workspace/4.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_alert_test.2469575363 |
Short name | T557 |
Test name | |
Test status | |
Simulation time | 23495213 ps |
CPU time | 0.69 seconds |
Started | Jun 27 06:49:25 PM PDT 24 |
Finished | Jun 27 06:49:27 PM PDT 24 |
Peak memory | 202572 kb |
Host | smart-420ff1bb-f55f-42c0-99ce-837e61bbee94 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469575363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.2469575363 |
Directory | /workspace/4.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_bijection.1761388335 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 121556168757 ps |
CPU time | 2186.62 seconds |
Started | Jun 27 06:49:29 PM PDT 24 |
Finished | Jun 27 07:26:00 PM PDT 24 |
Peak memory | 203752 kb |
Host | smart-695fdc7f-3fee-44e0-bd77-dcc2909aff1c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761388335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection. 1761388335 |
Directory | /workspace/4.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_executable.2310466705 |
Short name | T476 |
Test name | |
Test status | |
Simulation time | 16307187909 ps |
CPU time | 560.33 seconds |
Started | Jun 27 06:49:26 PM PDT 24 |
Finished | Jun 27 06:58:50 PM PDT 24 |
Peak memory | 350096 kb |
Host | smart-c2c85b39-d938-445e-b5d5-a6d54c2b8df9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310466705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executabl e.2310466705 |
Directory | /workspace/4.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_lc_escalation.2083530384 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 2267583478 ps |
CPU time | 15.26 seconds |
Started | Jun 27 06:49:26 PM PDT 24 |
Finished | Jun 27 06:49:46 PM PDT 24 |
Peak memory | 211064 kb |
Host | smart-f40f4a0c-b1d6-498f-8161-b23640995dae |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083530384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esc alation.2083530384 |
Directory | /workspace/4.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_max_throughput.3340790300 |
Short name | T579 |
Test name | |
Test status | |
Simulation time | 2719854134 ps |
CPU time | 115.45 seconds |
Started | Jun 27 06:49:27 PM PDT 24 |
Finished | Jun 27 06:51:27 PM PDT 24 |
Peak memory | 365496 kb |
Host | smart-d92f73f3-c8d1-4d6f-92b0-0c42f2f7ba57 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340790300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 4.sram_ctrl_max_throughput.3340790300 |
Directory | /workspace/4.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_mem_partial_access.2648736431 |
Short name | T609 |
Test name | |
Test status | |
Simulation time | 11615146241 ps |
CPU time | 180.73 seconds |
Started | Jun 27 06:49:24 PM PDT 24 |
Finished | Jun 27 06:52:26 PM PDT 24 |
Peak memory | 211088 kb |
Host | smart-afcf0c16-1c19-4509-8066-dd027e11c561 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648736431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_mem_partial_access.2648736431 |
Directory | /workspace/4.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_mem_walk.3989191721 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 18544280120 ps |
CPU time | 341.42 seconds |
Started | Jun 27 06:49:26 PM PDT 24 |
Finished | Jun 27 06:55:12 PM PDT 24 |
Peak memory | 211068 kb |
Host | smart-f57c5aca-f4f6-43df-bd4b-17527ba6add2 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989191721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl _mem_walk.3989191721 |
Directory | /workspace/4.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_multiple_keys.1213239018 |
Short name | T815 |
Test name | |
Test status | |
Simulation time | 7259090428 ps |
CPU time | 1068.51 seconds |
Started | Jun 27 06:49:24 PM PDT 24 |
Finished | Jun 27 07:07:14 PM PDT 24 |
Peak memory | 380740 kb |
Host | smart-715672c0-be14-40ae-894c-ed0593abf763 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213239018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip le_keys.1213239018 |
Directory | /workspace/4.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_partial_access.637802388 |
Short name | T636 |
Test name | |
Test status | |
Simulation time | 3263477064 ps |
CPU time | 19.88 seconds |
Started | Jun 27 06:49:29 PM PDT 24 |
Finished | Jun 27 06:49:53 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-15a84554-12cb-40ef-9500-011a5dec2c3f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637802388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sr am_ctrl_partial_access.637802388 |
Directory | /workspace/4.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.3627936016 |
Short name | T837 |
Test name | |
Test status | |
Simulation time | 207660531732 ps |
CPU time | 406.79 seconds |
Started | Jun 27 06:49:26 PM PDT 24 |
Finished | Jun 27 06:56:17 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-687e2916-3d6f-496c-aec8-f0c8201abd23 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627936016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 4.sram_ctrl_partial_access_b2b.3627936016 |
Directory | /workspace/4.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_ram_cfg.477876496 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 347549870 ps |
CPU time | 3.28 seconds |
Started | Jun 27 06:49:28 PM PDT 24 |
Finished | Jun 27 06:49:36 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-5142f819-e77d-4c14-a0e5-724c7e9b1d4d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477876496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.477876496 |
Directory | /workspace/4.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_regwen.968632830 |
Short name | T597 |
Test name | |
Test status | |
Simulation time | 16583789365 ps |
CPU time | 1566.06 seconds |
Started | Jun 27 06:49:26 PM PDT 24 |
Finished | Jun 27 07:15:35 PM PDT 24 |
Peak memory | 378748 kb |
Host | smart-19935d0e-b8ba-46b8-bd86-b63359479366 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968632830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.968632830 |
Directory | /workspace/4.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_sec_cm.2824270836 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 1904613268 ps |
CPU time | 3.61 seconds |
Started | Jun 27 06:49:23 PM PDT 24 |
Finished | Jun 27 06:49:28 PM PDT 24 |
Peak memory | 222408 kb |
Host | smart-7120da28-a8c4-46f6-aabd-d4f0d7cec517 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824270836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.2824270836 |
Directory | /workspace/4.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_smoke.1621170947 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 2633064172 ps |
CPU time | 23.19 seconds |
Started | Jun 27 06:49:26 PM PDT 24 |
Finished | Jun 27 06:49:53 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-888c2583-ee99-4523-9aef-702c251b27ef |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621170947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.1621170947 |
Directory | /workspace/4.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_all.2756608800 |
Short name | T701 |
Test name | |
Test status | |
Simulation time | 20513724377 ps |
CPU time | 2883.65 seconds |
Started | Jun 27 06:49:23 PM PDT 24 |
Finished | Jun 27 07:37:29 PM PDT 24 |
Peak memory | 384844 kb |
Host | smart-f3d554dd-ce26-43a7-b858-b7b2d28f04e2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756608800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 4.sram_ctrl_stress_all.2756608800 |
Directory | /workspace/4.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_pipeline.1092441998 |
Short name | T931 |
Test name | |
Test status | |
Simulation time | 4178368987 ps |
CPU time | 290.01 seconds |
Started | Jun 27 06:49:27 PM PDT 24 |
Finished | Jun 27 06:54:22 PM PDT 24 |
Peak memory | 203060 kb |
Host | smart-d6ac3094-5bb0-4bcf-9d65-142e4ed48afd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092441998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_stress_pipeline.1092441998 |
Directory | /workspace/4.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.2154326280 |
Short name | T590 |
Test name | |
Test status | |
Simulation time | 8603518168 ps |
CPU time | 128.64 seconds |
Started | Jun 27 06:49:27 PM PDT 24 |
Finished | Jun 27 06:51:40 PM PDT 24 |
Peak memory | 364480 kb |
Host | smart-aec0ee6f-b787-47c9-ad9a-7ec541b6b746 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154326280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.2154326280 |
Directory | /workspace/4.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_access_during_key_req.2570383888 |
Short name | T867 |
Test name | |
Test status | |
Simulation time | 11055910634 ps |
CPU time | 513.2 seconds |
Started | Jun 27 06:54:44 PM PDT 24 |
Finished | Jun 27 07:03:19 PM PDT 24 |
Peak memory | 346040 kb |
Host | smart-b291f754-9598-493a-9703-7b7e0024e5f1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570383888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 40.sram_ctrl_access_during_key_req.2570383888 |
Directory | /workspace/40.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_alert_test.1381813241 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 23612815 ps |
CPU time | 0.69 seconds |
Started | Jun 27 06:54:55 PM PDT 24 |
Finished | Jun 27 06:54:59 PM PDT 24 |
Peak memory | 202400 kb |
Host | smart-a0df9c03-0eaf-4eb6-9574-f38c27885ae3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381813241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.1381813241 |
Directory | /workspace/40.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_bijection.1523484040 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 26427915383 ps |
CPU time | 1742.84 seconds |
Started | Jun 27 06:54:43 PM PDT 24 |
Finished | Jun 27 07:23:48 PM PDT 24 |
Peak memory | 203500 kb |
Host | smart-680293db-471f-4e5f-b98d-53cad855026d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523484040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection .1523484040 |
Directory | /workspace/40.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_executable.110999896 |
Short name | T807 |
Test name | |
Test status | |
Simulation time | 14752940890 ps |
CPU time | 984.3 seconds |
Started | Jun 27 06:54:44 PM PDT 24 |
Finished | Jun 27 07:11:10 PM PDT 24 |
Peak memory | 379720 kb |
Host | smart-10d5af7d-778a-49ce-8719-f1e4ceb87ff2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110999896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executabl e.110999896 |
Directory | /workspace/40.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_lc_escalation.1562580033 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 9131939512 ps |
CPU time | 30.86 seconds |
Started | Jun 27 06:54:46 PM PDT 24 |
Finished | Jun 27 06:55:18 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-a31708eb-ff94-4e9a-8ecd-f770576611f0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562580033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_es calation.1562580033 |
Directory | /workspace/40.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_max_throughput.1587671662 |
Short name | T691 |
Test name | |
Test status | |
Simulation time | 746818244 ps |
CPU time | 49.05 seconds |
Started | Jun 27 06:54:43 PM PDT 24 |
Finished | Jun 27 06:55:34 PM PDT 24 |
Peak memory | 293560 kb |
Host | smart-d0c2a160-a2a7-4225-b7f0-d5dad28f53d8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587671662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 40.sram_ctrl_max_throughput.1587671662 |
Directory | /workspace/40.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_mem_partial_access.67649040 |
Short name | T561 |
Test name | |
Test status | |
Simulation time | 6252222233 ps |
CPU time | 169 seconds |
Started | Jun 27 06:54:44 PM PDT 24 |
Finished | Jun 27 06:57:35 PM PDT 24 |
Peak memory | 211116 kb |
Host | smart-b1460480-e037-4e60-856d-feb39671ffbf |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67649040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40. sram_ctrl_mem_partial_access.67649040 |
Directory | /workspace/40.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_mem_walk.3832113539 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 10715177830 ps |
CPU time | 292.96 seconds |
Started | Jun 27 06:54:43 PM PDT 24 |
Finished | Jun 27 06:59:37 PM PDT 24 |
Peak memory | 211804 kb |
Host | smart-72891cb7-bf91-4cf0-b497-59f57d783577 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832113539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr l_mem_walk.3832113539 |
Directory | /workspace/40.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_multiple_keys.2235778216 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 6281243532 ps |
CPU time | 58.26 seconds |
Started | Jun 27 06:54:45 PM PDT 24 |
Finished | Jun 27 06:55:44 PM PDT 24 |
Peak memory | 252852 kb |
Host | smart-0656d917-f07c-450f-8672-89cc99bac4f5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235778216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi ple_keys.2235778216 |
Directory | /workspace/40.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_partial_access.3534585515 |
Short name | T699 |
Test name | |
Test status | |
Simulation time | 4202764055 ps |
CPU time | 16.68 seconds |
Started | Jun 27 06:54:43 PM PDT 24 |
Finished | Jun 27 06:55:01 PM PDT 24 |
Peak memory | 203044 kb |
Host | smart-a4054f76-3f8c-4498-b9d9-ec2efd2e0baf |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534585515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40. sram_ctrl_partial_access.3534585515 |
Directory | /workspace/40.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.3671986480 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 7744679886 ps |
CPU time | 190.58 seconds |
Started | Jun 27 06:54:44 PM PDT 24 |
Finished | Jun 27 06:57:56 PM PDT 24 |
Peak memory | 202852 kb |
Host | smart-8ec0925b-10c5-4c37-9120-b623c19537c4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671986480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 40.sram_ctrl_partial_access_b2b.3671986480 |
Directory | /workspace/40.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_ram_cfg.2196541644 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 1259923875 ps |
CPU time | 3.68 seconds |
Started | Jun 27 06:54:43 PM PDT 24 |
Finished | Jun 27 06:54:48 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-22a01f08-8382-4958-9a79-730626c1cf22 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196541644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.2196541644 |
Directory | /workspace/40.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_regwen.3778333500 |
Short name | T467 |
Test name | |
Test status | |
Simulation time | 11820045463 ps |
CPU time | 536.86 seconds |
Started | Jun 27 06:54:42 PM PDT 24 |
Finished | Jun 27 07:03:39 PM PDT 24 |
Peak memory | 368512 kb |
Host | smart-256d1498-2658-4484-9f91-1292cbbca283 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778333500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.3778333500 |
Directory | /workspace/40.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_smoke.250520490 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 2660052489 ps |
CPU time | 10.08 seconds |
Started | Jun 27 06:54:44 PM PDT 24 |
Finished | Jun 27 06:54:56 PM PDT 24 |
Peak memory | 217484 kb |
Host | smart-c4ed3ac3-2d0c-4b77-b41d-8be9abe4ebf4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250520490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.250520490 |
Directory | /workspace/40.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_all.3467679960 |
Short name | T459 |
Test name | |
Test status | |
Simulation time | 58913574268 ps |
CPU time | 4416.47 seconds |
Started | Jun 27 06:54:57 PM PDT 24 |
Finished | Jun 27 08:08:36 PM PDT 24 |
Peak memory | 379832 kb |
Host | smart-947aa9c6-053f-42b1-b7ee-19339c28f197 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467679960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 40.sram_ctrl_stress_all.3467679960 |
Directory | /workspace/40.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2583781537 |
Short name | T758 |
Test name | |
Test status | |
Simulation time | 412869170 ps |
CPU time | 8.12 seconds |
Started | Jun 27 06:54:43 PM PDT 24 |
Finished | Jun 27 06:54:52 PM PDT 24 |
Peak memory | 211024 kb |
Host | smart-3bf62367-a80b-4694-8c26-40f46049d650 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2583781537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.2583781537 |
Directory | /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_pipeline.1576576443 |
Short name | T463 |
Test name | |
Test status | |
Simulation time | 4133908947 ps |
CPU time | 285.83 seconds |
Started | Jun 27 06:54:42 PM PDT 24 |
Finished | Jun 27 06:59:29 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-15354c4c-030b-4490-9c11-5de975e7dd21 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576576443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_stress_pipeline.1576576443 |
Directory | /workspace/40.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.4172924986 |
Short name | T920 |
Test name | |
Test status | |
Simulation time | 2963972858 ps |
CPU time | 53.33 seconds |
Started | Jun 27 06:54:44 PM PDT 24 |
Finished | Jun 27 06:55:39 PM PDT 24 |
Peak memory | 305264 kb |
Host | smart-2c1339fb-eb84-4b82-87a7-8d138bf34c5d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172924986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.4172924986 |
Directory | /workspace/40.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_access_during_key_req.832746185 |
Short name | T637 |
Test name | |
Test status | |
Simulation time | 27731686653 ps |
CPU time | 385.13 seconds |
Started | Jun 27 06:54:55 PM PDT 24 |
Finished | Jun 27 07:01:23 PM PDT 24 |
Peak memory | 365404 kb |
Host | smart-9a7bcf0c-9fbd-4ef9-ab37-f03c5b85f718 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832746185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 41.sram_ctrl_access_during_key_req.832746185 |
Directory | /workspace/41.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_alert_test.2896499704 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 35961714 ps |
CPU time | 0.69 seconds |
Started | Jun 27 06:54:55 PM PDT 24 |
Finished | Jun 27 06:54:58 PM PDT 24 |
Peak memory | 202400 kb |
Host | smart-2dfd40f8-08c1-40ed-a5bd-71bc57ee4f74 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896499704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.2896499704 |
Directory | /workspace/41.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_bijection.3629666079 |
Short name | T824 |
Test name | |
Test status | |
Simulation time | 101282517592 ps |
CPU time | 2311.3 seconds |
Started | Jun 27 06:54:55 PM PDT 24 |
Finished | Jun 27 07:33:29 PM PDT 24 |
Peak memory | 203640 kb |
Host | smart-736c21c6-771c-400d-9b6d-7082de786e80 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629666079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection .3629666079 |
Directory | /workspace/41.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_executable.2707566365 |
Short name | T542 |
Test name | |
Test status | |
Simulation time | 18444287350 ps |
CPU time | 834.93 seconds |
Started | Jun 27 06:54:55 PM PDT 24 |
Finished | Jun 27 07:08:53 PM PDT 24 |
Peak memory | 357300 kb |
Host | smart-7790e7e3-b680-4a05-ad71-0384c07c3073 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707566365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executab le.2707566365 |
Directory | /workspace/41.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_lc_escalation.3953351584 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 9671142220 ps |
CPU time | 58.77 seconds |
Started | Jun 27 06:54:54 PM PDT 24 |
Finished | Jun 27 06:55:54 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-d8e56676-2618-4d47-bc82-93db50811bcc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953351584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es calation.3953351584 |
Directory | /workspace/41.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_max_throughput.3170550909 |
Short name | T875 |
Test name | |
Test status | |
Simulation time | 1295190345 ps |
CPU time | 6.58 seconds |
Started | Jun 27 06:54:54 PM PDT 24 |
Finished | Jun 27 06:55:02 PM PDT 24 |
Peak memory | 212060 kb |
Host | smart-9be77e27-82eb-4dfa-91f1-b9633e317074 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170550909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 41.sram_ctrl_max_throughput.3170550909 |
Directory | /workspace/41.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_mem_partial_access.2950977026 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 3862524785 ps |
CPU time | 63.47 seconds |
Started | Jun 27 06:54:58 PM PDT 24 |
Finished | Jun 27 06:56:03 PM PDT 24 |
Peak memory | 211116 kb |
Host | smart-c7e18c6f-6901-4395-8707-f88da625a36c |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950977026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_mem_partial_access.2950977026 |
Directory | /workspace/41.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_mem_walk.2934134454 |
Short name | T732 |
Test name | |
Test status | |
Simulation time | 20999466274 ps |
CPU time | 307.76 seconds |
Started | Jun 27 06:54:54 PM PDT 24 |
Finished | Jun 27 07:00:03 PM PDT 24 |
Peak memory | 211028 kb |
Host | smart-36596c1d-c14e-418c-a2e4-71481466e437 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934134454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr l_mem_walk.2934134454 |
Directory | /workspace/41.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_multiple_keys.794279823 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 70748376575 ps |
CPU time | 1129.92 seconds |
Started | Jun 27 06:54:54 PM PDT 24 |
Finished | Jun 27 07:13:46 PM PDT 24 |
Peak memory | 380756 kb |
Host | smart-2b318d12-344a-4007-8e7c-a19ac329103e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794279823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multip le_keys.794279823 |
Directory | /workspace/41.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_partial_access.2595724231 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 794464595 ps |
CPU time | 51.93 seconds |
Started | Jun 27 06:54:55 PM PDT 24 |
Finished | Jun 27 06:55:50 PM PDT 24 |
Peak memory | 305168 kb |
Host | smart-26e041e9-1e24-4d98-8062-ef1847b7717b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595724231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41. sram_ctrl_partial_access.2595724231 |
Directory | /workspace/41.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.3131615282 |
Short name | T706 |
Test name | |
Test status | |
Simulation time | 128801579116 ps |
CPU time | 532.95 seconds |
Started | Jun 27 06:54:55 PM PDT 24 |
Finished | Jun 27 07:03:50 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-4993a873-0e39-46fc-81c3-4ba97a89ff80 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131615282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 41.sram_ctrl_partial_access_b2b.3131615282 |
Directory | /workspace/41.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_ram_cfg.2614995809 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 355765289 ps |
CPU time | 3.37 seconds |
Started | Jun 27 06:54:58 PM PDT 24 |
Finished | Jun 27 06:55:02 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-7c469967-32ac-440a-8c4f-4d1fb392ba34 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614995809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.2614995809 |
Directory | /workspace/41.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_regwen.3287038182 |
Short name | T911 |
Test name | |
Test status | |
Simulation time | 9137257366 ps |
CPU time | 659.54 seconds |
Started | Jun 27 06:54:57 PM PDT 24 |
Finished | Jun 27 07:05:59 PM PDT 24 |
Peak memory | 380392 kb |
Host | smart-06f24e8e-e473-4e26-abdd-bb8dd8aa2e5c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287038182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.3287038182 |
Directory | /workspace/41.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_smoke.1645921266 |
Short name | T643 |
Test name | |
Test status | |
Simulation time | 1770529552 ps |
CPU time | 5.87 seconds |
Started | Jun 27 06:54:55 PM PDT 24 |
Finished | Jun 27 06:55:03 PM PDT 24 |
Peak memory | 202772 kb |
Host | smart-daa7eacf-bc7a-4c06-b396-12ad3a0bcd22 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645921266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.1645921266 |
Directory | /workspace/41.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_all.31272746 |
Short name | T812 |
Test name | |
Test status | |
Simulation time | 124145856914 ps |
CPU time | 1824.77 seconds |
Started | Jun 27 06:54:58 PM PDT 24 |
Finished | Jun 27 07:25:24 PM PDT 24 |
Peak memory | 380808 kb |
Host | smart-616b1368-f13b-4a26-8c63-71b68182fda2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31272746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test + UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 41.sram_ctrl_stress_all.31272746 |
Directory | /workspace/41.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1976723354 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 16097040346 ps |
CPU time | 303.99 seconds |
Started | Jun 27 06:54:54 PM PDT 24 |
Finished | Jun 27 07:00:01 PM PDT 24 |
Peak memory | 374732 kb |
Host | smart-d5c8914e-ce02-4a7a-8f06-7d3f8a0b57bd |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1976723354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.1976723354 |
Directory | /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_pipeline.2724438388 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 4276363693 ps |
CPU time | 234.67 seconds |
Started | Jun 27 06:54:53 PM PDT 24 |
Finished | Jun 27 06:58:50 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-6ed43804-ea53-4463-9141-9af6bccb68cb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724438388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_stress_pipeline.2724438388 |
Directory | /workspace/41.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.3260760533 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 1589113944 ps |
CPU time | 120.08 seconds |
Started | Jun 27 06:54:53 PM PDT 24 |
Finished | Jun 27 06:56:55 PM PDT 24 |
Peak memory | 339748 kb |
Host | smart-91e0a3ed-9212-4998-ba0c-34aa69daba13 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260760533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.3260760533 |
Directory | /workspace/41.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_access_during_key_req.2530417137 |
Short name | T677 |
Test name | |
Test status | |
Simulation time | 36940755530 ps |
CPU time | 797.64 seconds |
Started | Jun 27 06:55:07 PM PDT 24 |
Finished | Jun 27 07:08:25 PM PDT 24 |
Peak memory | 379432 kb |
Host | smart-1599f072-a6ee-45d5-b699-1201db748943 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530417137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 42.sram_ctrl_access_during_key_req.2530417137 |
Directory | /workspace/42.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_alert_test.2900728644 |
Short name | T620 |
Test name | |
Test status | |
Simulation time | 36080631 ps |
CPU time | 0.66 seconds |
Started | Jun 27 06:55:08 PM PDT 24 |
Finished | Jun 27 06:55:10 PM PDT 24 |
Peak memory | 202368 kb |
Host | smart-92882f50-d992-4c43-b335-005a205f1a7f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900728644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.2900728644 |
Directory | /workspace/42.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_bijection.878262644 |
Short name | T656 |
Test name | |
Test status | |
Simulation time | 103689008186 ps |
CPU time | 1216.09 seconds |
Started | Jun 27 06:54:55 PM PDT 24 |
Finished | Jun 27 07:15:14 PM PDT 24 |
Peak memory | 203500 kb |
Host | smart-0a78b672-e22b-4157-86f6-0aa18ee0f0f1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878262644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection. 878262644 |
Directory | /workspace/42.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_executable.1581482248 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 5276368334 ps |
CPU time | 424.66 seconds |
Started | Jun 27 06:55:06 PM PDT 24 |
Finished | Jun 27 07:02:12 PM PDT 24 |
Peak memory | 370532 kb |
Host | smart-eabdcb9e-75c5-42aa-997a-0706a41aa47d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581482248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executab le.1581482248 |
Directory | /workspace/42.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_lc_escalation.3938688030 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 15870040438 ps |
CPU time | 48.01 seconds |
Started | Jun 27 06:55:07 PM PDT 24 |
Finished | Jun 27 06:55:56 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-37bc5c2c-8e52-45c8-8a4a-8c3847462b20 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938688030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_es calation.3938688030 |
Directory | /workspace/42.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_max_throughput.2664412863 |
Short name | T750 |
Test name | |
Test status | |
Simulation time | 712342020 ps |
CPU time | 6.87 seconds |
Started | Jun 27 06:55:07 PM PDT 24 |
Finished | Jun 27 06:55:15 PM PDT 24 |
Peak memory | 214988 kb |
Host | smart-c9f7405f-a886-4374-a734-0f339572ade0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664412863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 42.sram_ctrl_max_throughput.2664412863 |
Directory | /workspace/42.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_mem_partial_access.1915340178 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 6069219162 ps |
CPU time | 76.82 seconds |
Started | Jun 27 06:55:06 PM PDT 24 |
Finished | Jun 27 06:56:23 PM PDT 24 |
Peak memory | 211072 kb |
Host | smart-5f8a2014-89c7-43b0-9e4f-b84ceaa5caff |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915340178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_mem_partial_access.1915340178 |
Directory | /workspace/42.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_mem_walk.3622510391 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 10516286453 ps |
CPU time | 150.88 seconds |
Started | Jun 27 06:55:06 PM PDT 24 |
Finished | Jun 27 06:57:38 PM PDT 24 |
Peak memory | 211036 kb |
Host | smart-9de9e776-370d-408a-8257-ba0222c0532f |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622510391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr l_mem_walk.3622510391 |
Directory | /workspace/42.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_multiple_keys.105615914 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 18331317737 ps |
CPU time | 712.92 seconds |
Started | Jun 27 06:54:55 PM PDT 24 |
Finished | Jun 27 07:06:50 PM PDT 24 |
Peak memory | 378716 kb |
Host | smart-a042bdf9-05e5-4a7c-b472-8ff53926bb80 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105615914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multip le_keys.105615914 |
Directory | /workspace/42.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_partial_access.1666878829 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 1990932749 ps |
CPU time | 182.8 seconds |
Started | Jun 27 06:55:08 PM PDT 24 |
Finished | Jun 27 06:58:12 PM PDT 24 |
Peak memory | 370324 kb |
Host | smart-66b9f4ab-0c61-4640-aef9-20a6fe14143c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666878829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42. sram_ctrl_partial_access.1666878829 |
Directory | /workspace/42.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.963935309 |
Short name | T888 |
Test name | |
Test status | |
Simulation time | 8891363584 ps |
CPU time | 243.37 seconds |
Started | Jun 27 06:55:06 PM PDT 24 |
Finished | Jun 27 06:59:10 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-ac557bea-0f7b-4999-9dd0-b2d236303ab1 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963935309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 42.sram_ctrl_partial_access_b2b.963935309 |
Directory | /workspace/42.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_ram_cfg.2665841273 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 872526367 ps |
CPU time | 3.31 seconds |
Started | Jun 27 06:55:09 PM PDT 24 |
Finished | Jun 27 06:55:14 PM PDT 24 |
Peak memory | 203068 kb |
Host | smart-bd44b5f4-6fce-4319-9a0a-584f6c9cf9a1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665841273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.2665841273 |
Directory | /workspace/42.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_regwen.32883308 |
Short name | T465 |
Test name | |
Test status | |
Simulation time | 5057204719 ps |
CPU time | 1378.73 seconds |
Started | Jun 27 06:55:06 PM PDT 24 |
Finished | Jun 27 07:18:06 PM PDT 24 |
Peak memory | 376712 kb |
Host | smart-adb2fbee-b396-40fe-ad8e-8df5ca30c093 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32883308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.32883308 |
Directory | /workspace/42.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_smoke.3532262482 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 3081745200 ps |
CPU time | 40.93 seconds |
Started | Jun 27 06:54:56 PM PDT 24 |
Finished | Jun 27 06:55:40 PM PDT 24 |
Peak memory | 295880 kb |
Host | smart-f875bc5f-0a07-4c0c-9b26-a9c062cd8e4b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532262482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.3532262482 |
Directory | /workspace/42.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_all.1871378975 |
Short name | T685 |
Test name | |
Test status | |
Simulation time | 64779682213 ps |
CPU time | 2622.22 seconds |
Started | Jun 27 06:55:07 PM PDT 24 |
Finished | Jun 27 07:38:50 PM PDT 24 |
Peak memory | 370536 kb |
Host | smart-24fbe25d-650b-44e0-9fe9-c27f8974e05a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871378975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 42.sram_ctrl_stress_all.1871378975 |
Directory | /workspace/42.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3175757966 |
Short name | T754 |
Test name | |
Test status | |
Simulation time | 1524387951 ps |
CPU time | 12.71 seconds |
Started | Jun 27 06:55:09 PM PDT 24 |
Finished | Jun 27 06:55:23 PM PDT 24 |
Peak memory | 211268 kb |
Host | smart-d1c988ff-aef1-44da-adf5-febd5bb56f8d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3175757966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.3175757966 |
Directory | /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_pipeline.1382061444 |
Short name | T682 |
Test name | |
Test status | |
Simulation time | 31455510730 ps |
CPU time | 217.02 seconds |
Started | Jun 27 06:54:57 PM PDT 24 |
Finished | Jun 27 06:58:36 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-a643ce44-8272-490c-ba1f-017c1d83ac63 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382061444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_stress_pipeline.1382061444 |
Directory | /workspace/42.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1292715413 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 1505565907 ps |
CPU time | 76.29 seconds |
Started | Jun 27 06:55:06 PM PDT 24 |
Finished | Jun 27 06:56:23 PM PDT 24 |
Peak memory | 323360 kb |
Host | smart-a051cd76-c4b7-44c4-a6cb-5dbdd74c930f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292715413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.1292715413 |
Directory | /workspace/42.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_access_during_key_req.420078725 |
Short name | T936 |
Test name | |
Test status | |
Simulation time | 14094452928 ps |
CPU time | 608.86 seconds |
Started | Jun 27 06:55:19 PM PDT 24 |
Finished | Jun 27 07:05:30 PM PDT 24 |
Peak memory | 379708 kb |
Host | smart-15f3037a-c76b-4b37-8270-51687d7a41b3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420078725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 43.sram_ctrl_access_during_key_req.420078725 |
Directory | /workspace/43.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_alert_test.1686161602 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 42001696 ps |
CPU time | 0.69 seconds |
Started | Jun 27 06:55:32 PM PDT 24 |
Finished | Jun 27 06:55:34 PM PDT 24 |
Peak memory | 202384 kb |
Host | smart-90556c3c-9e95-41ba-8d56-f179a5b36c93 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686161602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.1686161602 |
Directory | /workspace/43.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_bijection.1815965575 |
Short name | T795 |
Test name | |
Test status | |
Simulation time | 18105567579 ps |
CPU time | 1212.11 seconds |
Started | Jun 27 06:55:19 PM PDT 24 |
Finished | Jun 27 07:15:33 PM PDT 24 |
Peak memory | 203108 kb |
Host | smart-65852a12-0fc6-43df-9bf1-b447c34ef58a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815965575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection .1815965575 |
Directory | /workspace/43.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_executable.1755783930 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 101093818320 ps |
CPU time | 818.63 seconds |
Started | Jun 27 06:55:30 PM PDT 24 |
Finished | Jun 27 07:09:09 PM PDT 24 |
Peak memory | 378752 kb |
Host | smart-8ad8f882-cbf7-400b-8f30-2da91e99695b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755783930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executab le.1755783930 |
Directory | /workspace/43.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_lc_escalation.917885796 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 8951246372 ps |
CPU time | 60 seconds |
Started | Jun 27 06:55:25 PM PDT 24 |
Finished | Jun 27 06:56:26 PM PDT 24 |
Peak memory | 215376 kb |
Host | smart-90d82e3b-e58d-40f1-8599-0b63d9a95494 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917885796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_esc alation.917885796 |
Directory | /workspace/43.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_max_throughput.1793509811 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 742461924 ps |
CPU time | 38.39 seconds |
Started | Jun 27 06:55:18 PM PDT 24 |
Finished | Jun 27 06:55:57 PM PDT 24 |
Peak memory | 279916 kb |
Host | smart-df16d664-37c2-4293-bff1-a2a7381703bf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793509811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 43.sram_ctrl_max_throughput.1793509811 |
Directory | /workspace/43.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_mem_partial_access.2829158057 |
Short name | T781 |
Test name | |
Test status | |
Simulation time | 17549018457 ps |
CPU time | 166.12 seconds |
Started | Jun 27 06:55:26 PM PDT 24 |
Finished | Jun 27 06:58:13 PM PDT 24 |
Peak memory | 211032 kb |
Host | smart-5935c6c8-cb7f-4ef6-b44e-e9f968f23e24 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829158057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_mem_partial_access.2829158057 |
Directory | /workspace/43.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_mem_walk.1669693878 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 10722516354 ps |
CPU time | 297.49 seconds |
Started | Jun 27 06:55:25 PM PDT 24 |
Finished | Jun 27 07:00:23 PM PDT 24 |
Peak memory | 212100 kb |
Host | smart-e66ad5ec-44ae-4336-adcf-cd553db40b1e |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669693878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr l_mem_walk.1669693878 |
Directory | /workspace/43.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_multiple_keys.2339404839 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 33265748689 ps |
CPU time | 1258.7 seconds |
Started | Jun 27 06:55:07 PM PDT 24 |
Finished | Jun 27 07:16:07 PM PDT 24 |
Peak memory | 378780 kb |
Host | smart-bfc260d2-a085-41c1-9735-893151aef541 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339404839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multi ple_keys.2339404839 |
Directory | /workspace/43.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_partial_access.93469520 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 1341336454 ps |
CPU time | 19.55 seconds |
Started | Jun 27 06:55:19 PM PDT 24 |
Finished | Jun 27 06:55:40 PM PDT 24 |
Peak memory | 202780 kb |
Host | smart-d091c9a5-05c0-456e-afab-164baddcadec |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93469520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sr am_ctrl_partial_access.93469520 |
Directory | /workspace/43.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3044587039 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 7279612763 ps |
CPU time | 347.09 seconds |
Started | Jun 27 06:55:18 PM PDT 24 |
Finished | Jun 27 07:01:06 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-f0399096-352e-4283-92ec-3b71cbcafec5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044587039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 43.sram_ctrl_partial_access_b2b.3044587039 |
Directory | /workspace/43.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_ram_cfg.3884667974 |
Short name | T470 |
Test name | |
Test status | |
Simulation time | 1057746410 ps |
CPU time | 3.26 seconds |
Started | Jun 27 06:55:25 PM PDT 24 |
Finished | Jun 27 06:55:29 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-11955cf4-aa34-4ff5-a350-4b141cc943e9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884667974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.3884667974 |
Directory | /workspace/43.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_regwen.3074532446 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 1133515110 ps |
CPU time | 380.47 seconds |
Started | Jun 27 06:55:19 PM PDT 24 |
Finished | Jun 27 07:01:40 PM PDT 24 |
Peak memory | 375684 kb |
Host | smart-105f852f-4096-4a7f-91a8-da0c97457edc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074532446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.3074532446 |
Directory | /workspace/43.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_smoke.3122854294 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 1530006907 ps |
CPU time | 31.12 seconds |
Started | Jun 27 06:55:08 PM PDT 24 |
Finished | Jun 27 06:55:40 PM PDT 24 |
Peak memory | 271736 kb |
Host | smart-b9802f0b-abaa-4c47-b18a-5e06821dc5de |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122854294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.3122854294 |
Directory | /workspace/43.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_all.1519775728 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 79257233836 ps |
CPU time | 2541.16 seconds |
Started | Jun 27 06:55:25 PM PDT 24 |
Finished | Jun 27 07:37:48 PM PDT 24 |
Peak memory | 379992 kb |
Host | smart-68e7fca8-6b44-48b7-936b-efd011d2bb3e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519775728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 43.sram_ctrl_stress_all.1519775728 |
Directory | /workspace/43.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2747536171 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 11508673926 ps |
CPU time | 29.43 seconds |
Started | Jun 27 06:55:25 PM PDT 24 |
Finished | Jun 27 06:55:55 PM PDT 24 |
Peak memory | 211464 kb |
Host | smart-0a7eb6f9-1e4f-4f95-9535-67bdb5192cb3 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2747536171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.2747536171 |
Directory | /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_pipeline.3689849165 |
Short name | T697 |
Test name | |
Test status | |
Simulation time | 18466209238 ps |
CPU time | 210.45 seconds |
Started | Jun 27 06:55:26 PM PDT 24 |
Finished | Jun 27 06:58:57 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-e22d6ca7-9b6e-4490-883d-355c5e48779e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689849165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_stress_pipeline.3689849165 |
Directory | /workspace/43.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.745021716 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 1414201491 ps |
CPU time | 6.33 seconds |
Started | Jun 27 06:55:32 PM PDT 24 |
Finished | Jun 27 06:55:39 PM PDT 24 |
Peak memory | 202668 kb |
Host | smart-e31845f5-2676-41c2-89be-fb0e28c831e4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745021716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 43.sram_ctrl_throughput_w_partial_write.745021716 |
Directory | /workspace/43.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_access_during_key_req.4233969075 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 152976059840 ps |
CPU time | 914.07 seconds |
Started | Jun 27 06:55:32 PM PDT 24 |
Finished | Jun 27 07:10:48 PM PDT 24 |
Peak memory | 371320 kb |
Host | smart-5c8a1cb4-12be-47a6-a197-1d4e1279f838 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233969075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 44.sram_ctrl_access_during_key_req.4233969075 |
Directory | /workspace/44.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_alert_test.3389420723 |
Short name | T765 |
Test name | |
Test status | |
Simulation time | 14428450 ps |
CPU time | 0.68 seconds |
Started | Jun 27 06:55:57 PM PDT 24 |
Finished | Jun 27 06:56:01 PM PDT 24 |
Peak memory | 202112 kb |
Host | smart-15fd5e8b-4693-40fc-af11-37b60477a108 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389420723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.3389420723 |
Directory | /workspace/44.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_bijection.2493482287 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 105222105088 ps |
CPU time | 1707.9 seconds |
Started | Jun 27 06:55:36 PM PDT 24 |
Finished | Jun 27 07:24:05 PM PDT 24 |
Peak memory | 203344 kb |
Host | smart-49fa840e-4eaa-4ecf-bdfd-8c1ea7d4dfc3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493482287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection .2493482287 |
Directory | /workspace/44.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_executable.3370340094 |
Short name | T744 |
Test name | |
Test status | |
Simulation time | 19711209565 ps |
CPU time | 1179.67 seconds |
Started | Jun 27 06:55:33 PM PDT 24 |
Finished | Jun 27 07:15:14 PM PDT 24 |
Peak memory | 379772 kb |
Host | smart-1e9de285-cccc-4a66-8e43-9c469994c970 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370340094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executab le.3370340094 |
Directory | /workspace/44.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_lc_escalation.3643838923 |
Short name | T497 |
Test name | |
Test status | |
Simulation time | 60575731652 ps |
CPU time | 100.57 seconds |
Started | Jun 27 06:55:34 PM PDT 24 |
Finished | Jun 27 06:57:16 PM PDT 24 |
Peak memory | 216192 kb |
Host | smart-25485c80-a326-4e22-8573-8fdeaaba9a78 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643838923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es calation.3643838923 |
Directory | /workspace/44.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_max_throughput.4207246959 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 3077071974 ps |
CPU time | 26.72 seconds |
Started | Jun 27 06:55:31 PM PDT 24 |
Finished | Jun 27 06:55:59 PM PDT 24 |
Peak memory | 277936 kb |
Host | smart-7d340f9a-dad9-4906-9c75-e81078ff29c1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207246959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 44.sram_ctrl_max_throughput.4207246959 |
Directory | /workspace/44.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_mem_partial_access.2138317701 |
Short name | T657 |
Test name | |
Test status | |
Simulation time | 1580795914 ps |
CPU time | 116.6 seconds |
Started | Jun 27 06:55:47 PM PDT 24 |
Finished | Jun 27 06:57:45 PM PDT 24 |
Peak memory | 211016 kb |
Host | smart-cde86d92-e976-4a6e-af40-990ffb329bae |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138317701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_mem_partial_access.2138317701 |
Directory | /workspace/44.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_mem_walk.3194049990 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 14452834928 ps |
CPU time | 154.34 seconds |
Started | Jun 27 06:55:32 PM PDT 24 |
Finished | Jun 27 06:58:07 PM PDT 24 |
Peak memory | 210972 kb |
Host | smart-4cadba53-5d45-40b9-a3bd-9d9e59191824 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194049990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr l_mem_walk.3194049990 |
Directory | /workspace/44.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_multiple_keys.3968541533 |
Short name | T651 |
Test name | |
Test status | |
Simulation time | 18701100089 ps |
CPU time | 1239.07 seconds |
Started | Jun 27 06:55:37 PM PDT 24 |
Finished | Jun 27 07:16:17 PM PDT 24 |
Peak memory | 379744 kb |
Host | smart-3fa40800-d223-4fbb-95fd-4ae3136bc65d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968541533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi ple_keys.3968541533 |
Directory | /workspace/44.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_partial_access.678467952 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 6661833878 ps |
CPU time | 23.58 seconds |
Started | Jun 27 06:55:31 PM PDT 24 |
Finished | Jun 27 06:55:55 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-5232004b-75eb-46d8-b2da-24b46a846f33 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678467952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.s ram_ctrl_partial_access.678467952 |
Directory | /workspace/44.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3800595093 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 5855567255 ps |
CPU time | 291.51 seconds |
Started | Jun 27 06:55:32 PM PDT 24 |
Finished | Jun 27 07:00:24 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-a8609eed-c085-4b29-a1b5-f28142797361 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800595093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 44.sram_ctrl_partial_access_b2b.3800595093 |
Directory | /workspace/44.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_ram_cfg.2627589274 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 355469742 ps |
CPU time | 3.29 seconds |
Started | Jun 27 06:55:36 PM PDT 24 |
Finished | Jun 27 06:55:41 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-8e4db047-7e3e-43a5-bc3b-7555d498e1ad |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627589274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.2627589274 |
Directory | /workspace/44.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_regwen.4126616974 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 16700059005 ps |
CPU time | 242.6 seconds |
Started | Jun 27 06:55:36 PM PDT 24 |
Finished | Jun 27 06:59:39 PM PDT 24 |
Peak memory | 334560 kb |
Host | smart-a7c75257-ad90-4d34-949a-06b5480d54c1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126616974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.4126616974 |
Directory | /workspace/44.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_smoke.4288074178 |
Short name | T761 |
Test name | |
Test status | |
Simulation time | 9360523477 ps |
CPU time | 72.42 seconds |
Started | Jun 27 06:55:35 PM PDT 24 |
Finished | Jun 27 06:56:49 PM PDT 24 |
Peak memory | 310952 kb |
Host | smart-d7fdb206-ab8c-4766-ad7e-8cfd685b68a3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288074178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.4288074178 |
Directory | /workspace/44.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_all.2945655247 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 40779491146 ps |
CPU time | 1481.58 seconds |
Started | Jun 27 06:55:46 PM PDT 24 |
Finished | Jun 27 07:20:29 PM PDT 24 |
Peak memory | 381796 kb |
Host | smart-7af97f6a-1707-4c4f-bb47-bb7e1adb9016 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945655247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 44.sram_ctrl_stress_all.2945655247 |
Directory | /workspace/44.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3870874621 |
Short name | T788 |
Test name | |
Test status | |
Simulation time | 1944360356 ps |
CPU time | 81.46 seconds |
Started | Jun 27 06:55:57 PM PDT 24 |
Finished | Jun 27 06:57:22 PM PDT 24 |
Peak memory | 211104 kb |
Host | smart-087f66c8-e667-4443-9738-7c62f0475887 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3870874621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.3870874621 |
Directory | /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_pipeline.3446804044 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 4736165820 ps |
CPU time | 336.17 seconds |
Started | Jun 27 06:55:31 PM PDT 24 |
Finished | Jun 27 07:01:08 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-fa10e7c9-e07c-4146-80ad-7a194be0f798 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446804044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_stress_pipeline.3446804044 |
Directory | /workspace/44.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1754264085 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 3129761330 ps |
CPU time | 180.48 seconds |
Started | Jun 27 06:55:36 PM PDT 24 |
Finished | Jun 27 06:58:37 PM PDT 24 |
Peak memory | 372592 kb |
Host | smart-b059bf90-145d-4962-8ed2-e947d8985f6b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754264085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.1754264085 |
Directory | /workspace/44.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_access_during_key_req.1930240735 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 38903761863 ps |
CPU time | 565.24 seconds |
Started | Jun 27 06:55:57 PM PDT 24 |
Finished | Jun 27 07:05:26 PM PDT 24 |
Peak memory | 379504 kb |
Host | smart-abbb397e-b6b5-4a98-b7d8-e1afeadc1812 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930240735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 45.sram_ctrl_access_during_key_req.1930240735 |
Directory | /workspace/45.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_alert_test.481973253 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 41959829 ps |
CPU time | 0.68 seconds |
Started | Jun 27 06:55:44 PM PDT 24 |
Finished | Jun 27 06:55:46 PM PDT 24 |
Peak memory | 202420 kb |
Host | smart-7566b8d8-5774-415f-a272-fb6ff994e41a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481973253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.481973253 |
Directory | /workspace/45.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_bijection.3597317901 |
Short name | T648 |
Test name | |
Test status | |
Simulation time | 12148391115 ps |
CPU time | 897.53 seconds |
Started | Jun 27 06:55:46 PM PDT 24 |
Finished | Jun 27 07:10:44 PM PDT 24 |
Peak memory | 203076 kb |
Host | smart-b8398c6c-f422-4950-9c85-517c3bb6234c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597317901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection .3597317901 |
Directory | /workspace/45.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_executable.2606680306 |
Short name | T610 |
Test name | |
Test status | |
Simulation time | 60213642334 ps |
CPU time | 1125.25 seconds |
Started | Jun 27 06:55:54 PM PDT 24 |
Finished | Jun 27 07:14:42 PM PDT 24 |
Peak memory | 379076 kb |
Host | smart-ba9878b5-09ef-44f7-9c87-e3384221c13e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606680306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab le.2606680306 |
Directory | /workspace/45.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_lc_escalation.2163752990 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 8800703593 ps |
CPU time | 58.05 seconds |
Started | Jun 27 06:55:47 PM PDT 24 |
Finished | Jun 27 06:56:47 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-269f0842-a596-4ba8-8272-1f4bc5dd7cbd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163752990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_es calation.2163752990 |
Directory | /workspace/45.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_max_throughput.2700793296 |
Short name | T890 |
Test name | |
Test status | |
Simulation time | 1408158105 ps |
CPU time | 19.89 seconds |
Started | Jun 27 06:55:57 PM PDT 24 |
Finished | Jun 27 06:56:20 PM PDT 24 |
Peak memory | 260648 kb |
Host | smart-5d119492-8db0-43f6-a693-be9ec105c164 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700793296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 45.sram_ctrl_max_throughput.2700793296 |
Directory | /workspace/45.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_mem_partial_access.1494601516 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 2613774864 ps |
CPU time | 135 seconds |
Started | Jun 27 06:55:46 PM PDT 24 |
Finished | Jun 27 06:58:03 PM PDT 24 |
Peak memory | 211004 kb |
Host | smart-841eb520-f80b-4e7d-9d8b-68c2d9299073 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494601516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_mem_partial_access.1494601516 |
Directory | /workspace/45.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_mem_walk.2569221035 |
Short name | T621 |
Test name | |
Test status | |
Simulation time | 2718252311 ps |
CPU time | 152.73 seconds |
Started | Jun 27 06:55:46 PM PDT 24 |
Finished | Jun 27 06:58:20 PM PDT 24 |
Peak memory | 210952 kb |
Host | smart-80b0f8df-61d2-4550-81b7-86178c7d7c76 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569221035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctr l_mem_walk.2569221035 |
Directory | /workspace/45.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_multiple_keys.317693860 |
Short name | T502 |
Test name | |
Test status | |
Simulation time | 103757662708 ps |
CPU time | 1476.23 seconds |
Started | Jun 27 06:55:46 PM PDT 24 |
Finished | Jun 27 07:20:24 PM PDT 24 |
Peak memory | 376680 kb |
Host | smart-c7c1c692-a33e-4c07-b99b-23f5c4ee60c5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317693860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multip le_keys.317693860 |
Directory | /workspace/45.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_partial_access.782968789 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 19796843101 ps |
CPU time | 30.89 seconds |
Started | Jun 27 06:55:46 PM PDT 24 |
Finished | Jun 27 06:56:18 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-8bba55e8-0aab-47cb-86b7-14eb67c985ef |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782968789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.s ram_ctrl_partial_access.782968789 |
Directory | /workspace/45.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3945570926 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 8613726296 ps |
CPU time | 272.63 seconds |
Started | Jun 27 06:55:57 PM PDT 24 |
Finished | Jun 27 07:00:33 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-c31ca490-72ab-41c7-8d67-e4e644315ef4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945570926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 45.sram_ctrl_partial_access_b2b.3945570926 |
Directory | /workspace/45.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_ram_cfg.871405207 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 1402636413 ps |
CPU time | 3.36 seconds |
Started | Jun 27 06:55:46 PM PDT 24 |
Finished | Jun 27 06:55:51 PM PDT 24 |
Peak memory | 202852 kb |
Host | smart-2210b15b-c2f0-471b-a20f-4885eb2198fc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871405207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.871405207 |
Directory | /workspace/45.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_regwen.1098068636 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 35602429488 ps |
CPU time | 477.53 seconds |
Started | Jun 27 06:55:45 PM PDT 24 |
Finished | Jun 27 07:03:43 PM PDT 24 |
Peak memory | 369720 kb |
Host | smart-735bbdc9-040d-4767-ba2b-f13022b6d706 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098068636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.1098068636 |
Directory | /workspace/45.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_smoke.1488553618 |
Short name | T884 |
Test name | |
Test status | |
Simulation time | 2704208943 ps |
CPU time | 21.15 seconds |
Started | Jun 27 06:55:47 PM PDT 24 |
Finished | Jun 27 06:56:09 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-8f8a7ef8-e8f8-4f0f-b923-b06e5d46dd14 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488553618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.1488553618 |
Directory | /workspace/45.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_all.3734952692 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 167366513133 ps |
CPU time | 3545.88 seconds |
Started | Jun 27 06:55:44 PM PDT 24 |
Finished | Jun 27 07:54:51 PM PDT 24 |
Peak memory | 380420 kb |
Host | smart-96e59a45-663f-46e4-8568-372fbf07669a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734952692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 45.sram_ctrl_stress_all.3734952692 |
Directory | /workspace/45.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.744160939 |
Short name | T680 |
Test name | |
Test status | |
Simulation time | 688256609 ps |
CPU time | 25.87 seconds |
Started | Jun 27 06:55:46 PM PDT 24 |
Finished | Jun 27 06:56:13 PM PDT 24 |
Peak memory | 211060 kb |
Host | smart-88a3a1be-93a4-4185-9c38-23bc1dba7ec4 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=744160939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.744160939 |
Directory | /workspace/45.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_pipeline.1872707443 |
Short name | T500 |
Test name | |
Test status | |
Simulation time | 16030142276 ps |
CPU time | 282.03 seconds |
Started | Jun 27 06:55:57 PM PDT 24 |
Finished | Jun 27 07:00:42 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-b06c8add-0d12-480d-a9d5-4a41e187913d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872707443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_stress_pipeline.1872707443 |
Directory | /workspace/45.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2457782956 |
Short name | T853 |
Test name | |
Test status | |
Simulation time | 706956303 ps |
CPU time | 6.64 seconds |
Started | Jun 27 06:55:46 PM PDT 24 |
Finished | Jun 27 06:55:54 PM PDT 24 |
Peak memory | 210900 kb |
Host | smart-9ef88ee2-c642-478a-8063-7583a35d900f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457782956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.2457782956 |
Directory | /workspace/45.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_access_during_key_req.3763068203 |
Short name | T745 |
Test name | |
Test status | |
Simulation time | 56592651580 ps |
CPU time | 924.09 seconds |
Started | Jun 27 06:55:56 PM PDT 24 |
Finished | Jun 27 07:11:24 PM PDT 24 |
Peak memory | 366504 kb |
Host | smart-d99bb993-dc03-4cfd-b1bc-894b26303dda |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763068203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 46.sram_ctrl_access_during_key_req.3763068203 |
Directory | /workspace/46.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_alert_test.1304749434 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 16241897 ps |
CPU time | 0.71 seconds |
Started | Jun 27 06:55:56 PM PDT 24 |
Finished | Jun 27 06:55:59 PM PDT 24 |
Peak memory | 202752 kb |
Host | smart-15648775-90bc-4368-a571-7d3f7857bcbd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304749434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.1304749434 |
Directory | /workspace/46.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_bijection.1789111794 |
Short name | T679 |
Test name | |
Test status | |
Simulation time | 9521937846 ps |
CPU time | 678.75 seconds |
Started | Jun 27 06:55:55 PM PDT 24 |
Finished | Jun 27 07:07:16 PM PDT 24 |
Peak memory | 203476 kb |
Host | smart-b0ef4710-d377-4200-bd8d-57625e2ec3e9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789111794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection .1789111794 |
Directory | /workspace/46.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_executable.2168786431 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 15078853666 ps |
CPU time | 784.15 seconds |
Started | Jun 27 06:55:55 PM PDT 24 |
Finished | Jun 27 07:09:01 PM PDT 24 |
Peak memory | 369656 kb |
Host | smart-7e530017-cca0-4687-a9e0-6187b1c01e32 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168786431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab le.2168786431 |
Directory | /workspace/46.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_lc_escalation.3937162872 |
Short name | T601 |
Test name | |
Test status | |
Simulation time | 100811444138 ps |
CPU time | 83.2 seconds |
Started | Jun 27 06:55:55 PM PDT 24 |
Finished | Jun 27 06:57:22 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-ba5d47b1-4dc9-45dd-aa31-f6947a5b56f5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937162872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es calation.3937162872 |
Directory | /workspace/46.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_max_throughput.10480034 |
Short name | T528 |
Test name | |
Test status | |
Simulation time | 787783056 ps |
CPU time | 36.73 seconds |
Started | Jun 27 06:55:56 PM PDT 24 |
Finished | Jun 27 06:56:36 PM PDT 24 |
Peak memory | 295700 kb |
Host | smart-0511440d-809f-4aef-bb12-a9edddba254b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10480034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 46.sram_ctrl_max_throughput.10480034 |
Directory | /workspace/46.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_mem_partial_access.1480746017 |
Short name | T684 |
Test name | |
Test status | |
Simulation time | 2513504144 ps |
CPU time | 157.35 seconds |
Started | Jun 27 06:55:54 PM PDT 24 |
Finished | Jun 27 06:58:34 PM PDT 24 |
Peak memory | 211056 kb |
Host | smart-e7159904-3be9-40d4-8b7a-e3bb2f956d33 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480746017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_mem_partial_access.1480746017 |
Directory | /workspace/46.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_mem_walk.870573835 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 14130518064 ps |
CPU time | 167.42 seconds |
Started | Jun 27 06:55:56 PM PDT 24 |
Finished | Jun 27 06:58:47 PM PDT 24 |
Peak memory | 211016 kb |
Host | smart-ec1eb05f-0a96-4b03-bfac-dc096cc01337 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870573835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl _mem_walk.870573835 |
Directory | /workspace/46.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_multiple_keys.132677056 |
Short name | T676 |
Test name | |
Test status | |
Simulation time | 10002733414 ps |
CPU time | 271.5 seconds |
Started | Jun 27 06:55:56 PM PDT 24 |
Finished | Jun 27 07:00:30 PM PDT 24 |
Peak memory | 375648 kb |
Host | smart-b0aaaed5-ac23-4fcd-a7bf-7f3af6039b28 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132677056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multip le_keys.132677056 |
Directory | /workspace/46.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_partial_access.561572579 |
Short name | T865 |
Test name | |
Test status | |
Simulation time | 4912249147 ps |
CPU time | 18.13 seconds |
Started | Jun 27 06:55:57 PM PDT 24 |
Finished | Jun 27 06:56:18 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-83ca9efe-63e6-4523-8199-bb25c62b1606 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561572579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.s ram_ctrl_partial_access.561572579 |
Directory | /workspace/46.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.426976973 |
Short name | T696 |
Test name | |
Test status | |
Simulation time | 18137391833 ps |
CPU time | 335.78 seconds |
Started | Jun 27 06:55:56 PM PDT 24 |
Finished | Jun 27 07:01:35 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-641ce322-321c-4fef-ac90-883b14c471af |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426976973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 46.sram_ctrl_partial_access_b2b.426976973 |
Directory | /workspace/46.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_ram_cfg.2745332829 |
Short name | T576 |
Test name | |
Test status | |
Simulation time | 705336893 ps |
CPU time | 3.2 seconds |
Started | Jun 27 06:55:55 PM PDT 24 |
Finished | Jun 27 06:56:01 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-02feaf23-05c6-4f3c-8f12-e733c5d349e5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745332829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.2745332829 |
Directory | /workspace/46.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_regwen.1493479389 |
Short name | T832 |
Test name | |
Test status | |
Simulation time | 16038477619 ps |
CPU time | 1249.83 seconds |
Started | Jun 27 06:55:56 PM PDT 24 |
Finished | Jun 27 07:16:50 PM PDT 24 |
Peak memory | 375736 kb |
Host | smart-8381e285-88b1-42c5-b4aa-59221e433aa6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493479389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.1493479389 |
Directory | /workspace/46.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_smoke.2000602877 |
Short name | T793 |
Test name | |
Test status | |
Simulation time | 488160793 ps |
CPU time | 5.77 seconds |
Started | Jun 27 06:55:56 PM PDT 24 |
Finished | Jun 27 06:56:05 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-e74927bd-0dfd-487a-80db-ca2ab75043d3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000602877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.2000602877 |
Directory | /workspace/46.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_all.1461118725 |
Short name | T589 |
Test name | |
Test status | |
Simulation time | 410197470276 ps |
CPU time | 7117.83 seconds |
Started | Jun 27 06:55:57 PM PDT 24 |
Finished | Jun 27 08:54:39 PM PDT 24 |
Peak memory | 380868 kb |
Host | smart-9365dd9d-3033-43ca-a113-aff9fe912c19 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461118725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 46.sram_ctrl_stress_all.1461118725 |
Directory | /workspace/46.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3295129285 |
Short name | T917 |
Test name | |
Test status | |
Simulation time | 7603277920 ps |
CPU time | 33.88 seconds |
Started | Jun 27 06:55:56 PM PDT 24 |
Finished | Jun 27 06:56:33 PM PDT 24 |
Peak memory | 218480 kb |
Host | smart-4c8261e7-f15b-44cf-ac21-d173c5c277fc |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3295129285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.3295129285 |
Directory | /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_pipeline.141709504 |
Short name | T559 |
Test name | |
Test status | |
Simulation time | 3909867965 ps |
CPU time | 211.91 seconds |
Started | Jun 27 06:55:57 PM PDT 24 |
Finished | Jun 27 06:59:32 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-ec253861-aa8c-463a-a557-381807c64d5d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141709504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46 .sram_ctrl_stress_pipeline.141709504 |
Directory | /workspace/46.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2411474367 |
Short name | T622 |
Test name | |
Test status | |
Simulation time | 1007390496 ps |
CPU time | 15.78 seconds |
Started | Jun 27 06:55:56 PM PDT 24 |
Finished | Jun 27 06:56:15 PM PDT 24 |
Peak memory | 251596 kb |
Host | smart-131137eb-5f8b-4d3e-bc65-8fca1b2908ef |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411474367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.2411474367 |
Directory | /workspace/46.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_access_during_key_req.4134712050 |
Short name | T614 |
Test name | |
Test status | |
Simulation time | 13099764945 ps |
CPU time | 901.7 seconds |
Started | Jun 27 06:56:10 PM PDT 24 |
Finished | Jun 27 07:11:13 PM PDT 24 |
Peak memory | 375588 kb |
Host | smart-88be148f-9f1c-45ff-97ac-2f4e0be74bca |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134712050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 47.sram_ctrl_access_during_key_req.4134712050 |
Directory | /workspace/47.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_alert_test.2277520062 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 24020702 ps |
CPU time | 0.71 seconds |
Started | Jun 27 06:56:07 PM PDT 24 |
Finished | Jun 27 06:56:09 PM PDT 24 |
Peak memory | 202752 kb |
Host | smart-4e22f63c-4c36-4b52-b4e4-4f74158efe10 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277520062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.2277520062 |
Directory | /workspace/47.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_bijection.3209302456 |
Short name | T665 |
Test name | |
Test status | |
Simulation time | 62288364574 ps |
CPU time | 2177.89 seconds |
Started | Jun 27 06:56:09 PM PDT 24 |
Finished | Jun 27 07:32:29 PM PDT 24 |
Peak memory | 203616 kb |
Host | smart-5cd4d277-ed47-4115-93b7-32cfd568294c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209302456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection .3209302456 |
Directory | /workspace/47.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_executable.2926544213 |
Short name | T487 |
Test name | |
Test status | |
Simulation time | 13753319036 ps |
CPU time | 992.94 seconds |
Started | Jun 27 06:56:09 PM PDT 24 |
Finished | Jun 27 07:12:44 PM PDT 24 |
Peak memory | 376684 kb |
Host | smart-f45fcb8d-12b4-4bd2-8a4b-2a034070ce3b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926544213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executab le.2926544213 |
Directory | /workspace/47.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_lc_escalation.4234185080 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 6045913947 ps |
CPU time | 37.5 seconds |
Started | Jun 27 06:56:08 PM PDT 24 |
Finished | Jun 27 06:56:46 PM PDT 24 |
Peak memory | 211088 kb |
Host | smart-d62b654b-d159-442d-9115-b01f5963164c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234185080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_es calation.4234185080 |
Directory | /workspace/47.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_max_throughput.4004234709 |
Short name | T455 |
Test name | |
Test status | |
Simulation time | 1522597317 ps |
CPU time | 53.97 seconds |
Started | Jun 27 06:56:09 PM PDT 24 |
Finished | Jun 27 06:57:04 PM PDT 24 |
Peak memory | 300772 kb |
Host | smart-6b1e3ac7-063a-4365-8c9e-1b09fefeb991 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004234709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 47.sram_ctrl_max_throughput.4004234709 |
Directory | /workspace/47.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_mem_partial_access.3796164804 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 991010512 ps |
CPU time | 69.29 seconds |
Started | Jun 27 06:56:12 PM PDT 24 |
Finished | Jun 27 06:57:23 PM PDT 24 |
Peak memory | 210968 kb |
Host | smart-6061f286-3b0e-4304-9fbb-14a34b4d542a |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796164804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_mem_partial_access.3796164804 |
Directory | /workspace/47.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_mem_walk.2154742758 |
Short name | T762 |
Test name | |
Test status | |
Simulation time | 34638471686 ps |
CPU time | 174.2 seconds |
Started | Jun 27 06:56:08 PM PDT 24 |
Finished | Jun 27 06:59:03 PM PDT 24 |
Peak memory | 211000 kb |
Host | smart-701f2a32-ee05-4d4e-bc16-719e21e109a9 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154742758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr l_mem_walk.2154742758 |
Directory | /workspace/47.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_multiple_keys.2021458794 |
Short name | T530 |
Test name | |
Test status | |
Simulation time | 92710253970 ps |
CPU time | 806.89 seconds |
Started | Jun 27 06:56:12 PM PDT 24 |
Finished | Jun 27 07:09:40 PM PDT 24 |
Peak memory | 379796 kb |
Host | smart-ea725729-601c-4a77-8e7f-06a509808370 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021458794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi ple_keys.2021458794 |
Directory | /workspace/47.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_partial_access.2224110944 |
Short name | T515 |
Test name | |
Test status | |
Simulation time | 1569665823 ps |
CPU time | 46.52 seconds |
Started | Jun 27 06:56:12 PM PDT 24 |
Finished | Jun 27 06:57:00 PM PDT 24 |
Peak memory | 287688 kb |
Host | smart-c59c531e-f023-4c4b-9e47-95bd4786e7f2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224110944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47. sram_ctrl_partial_access.2224110944 |
Directory | /workspace/47.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3147309713 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 5130426112 ps |
CPU time | 260.67 seconds |
Started | Jun 27 06:56:08 PM PDT 24 |
Finished | Jun 27 07:00:30 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-c3377695-b78a-42c5-92a4-fe16e2baf74a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147309713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 47.sram_ctrl_partial_access_b2b.3147309713 |
Directory | /workspace/47.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_ram_cfg.2255587600 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 712698431 ps |
CPU time | 3.47 seconds |
Started | Jun 27 06:56:08 PM PDT 24 |
Finished | Jun 27 06:56:12 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-09071388-ef09-4916-8c01-d3657b3258ae |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255587600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.2255587600 |
Directory | /workspace/47.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_regwen.2539831409 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 69642511745 ps |
CPU time | 1151.7 seconds |
Started | Jun 27 06:56:09 PM PDT 24 |
Finished | Jun 27 07:15:23 PM PDT 24 |
Peak memory | 378732 kb |
Host | smart-8b8086ff-77b2-43c1-b5dd-0b08394e844a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539831409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.2539831409 |
Directory | /workspace/47.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_smoke.1795469209 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 1560285222 ps |
CPU time | 13.86 seconds |
Started | Jun 27 06:56:09 PM PDT 24 |
Finished | Jun 27 06:56:24 PM PDT 24 |
Peak memory | 202744 kb |
Host | smart-79d21fc5-a99e-4c08-b3a6-36378905eece |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795469209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.1795469209 |
Directory | /workspace/47.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_all.2126202191 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 129336748109 ps |
CPU time | 4196.93 seconds |
Started | Jun 27 06:56:12 PM PDT 24 |
Finished | Jun 27 08:06:10 PM PDT 24 |
Peak memory | 381112 kb |
Host | smart-600b70c1-b338-4926-87a0-6dc6b3461198 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126202191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 47.sram_ctrl_stress_all.2126202191 |
Directory | /workspace/47.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.991168173 |
Short name | T654 |
Test name | |
Test status | |
Simulation time | 614985449 ps |
CPU time | 27.08 seconds |
Started | Jun 27 06:56:08 PM PDT 24 |
Finished | Jun 27 06:56:36 PM PDT 24 |
Peak memory | 211144 kb |
Host | smart-ce733af8-bba6-424a-ab28-c7a473aab48b |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=991168173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.991168173 |
Directory | /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_pipeline.2870962068 |
Short name | T838 |
Test name | |
Test status | |
Simulation time | 5284777498 ps |
CPU time | 370.53 seconds |
Started | Jun 27 06:56:09 PM PDT 24 |
Finished | Jun 27 07:02:22 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-0b367694-b957-4ae6-803d-8786d65d6ee9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870962068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_stress_pipeline.2870962068 |
Directory | /workspace/47.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3796688588 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 790271210 ps |
CPU time | 87.23 seconds |
Started | Jun 27 06:56:10 PM PDT 24 |
Finished | Jun 27 06:57:39 PM PDT 24 |
Peak memory | 349496 kb |
Host | smart-fe5fea73-8e72-4dad-bd00-39c7f9db874b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796688588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.3796688588 |
Directory | /workspace/47.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_access_during_key_req.1287252071 |
Short name | T818 |
Test name | |
Test status | |
Simulation time | 13175878759 ps |
CPU time | 703.04 seconds |
Started | Jun 27 06:56:24 PM PDT 24 |
Finished | Jun 27 07:08:09 PM PDT 24 |
Peak memory | 356156 kb |
Host | smart-6c0af440-c757-45cb-b37c-57f4818339cc |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287252071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 48.sram_ctrl_access_during_key_req.1287252071 |
Directory | /workspace/48.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_alert_test.3341583879 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 12730945 ps |
CPU time | 0.65 seconds |
Started | Jun 27 06:56:22 PM PDT 24 |
Finished | Jun 27 06:56:25 PM PDT 24 |
Peak memory | 202616 kb |
Host | smart-28b654fb-f820-4c51-8038-b11f2e291826 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341583879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.3341583879 |
Directory | /workspace/48.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_bijection.3191408362 |
Short name | T766 |
Test name | |
Test status | |
Simulation time | 331528524161 ps |
CPU time | 2017.46 seconds |
Started | Jun 27 06:56:09 PM PDT 24 |
Finished | Jun 27 07:29:49 PM PDT 24 |
Peak memory | 203412 kb |
Host | smart-213cf273-8f48-4f9c-aab7-a09fba8bc087 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191408362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection .3191408362 |
Directory | /workspace/48.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_executable.773777020 |
Short name | T607 |
Test name | |
Test status | |
Simulation time | 22887079186 ps |
CPU time | 1042.66 seconds |
Started | Jun 27 06:56:22 PM PDT 24 |
Finished | Jun 27 07:13:46 PM PDT 24 |
Peak memory | 377560 kb |
Host | smart-978d5eff-5dab-4e58-bf46-68cf6d34b964 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773777020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executabl e.773777020 |
Directory | /workspace/48.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_lc_escalation.439190156 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 12378453210 ps |
CPU time | 77.14 seconds |
Started | Jun 27 06:56:24 PM PDT 24 |
Finished | Jun 27 06:57:43 PM PDT 24 |
Peak memory | 211036 kb |
Host | smart-79d56a5d-14ea-44e5-ba27-e959fa3b1520 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439190156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_esc alation.439190156 |
Directory | /workspace/48.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_max_throughput.2756393257 |
Short name | T628 |
Test name | |
Test status | |
Simulation time | 1299459626 ps |
CPU time | 137.55 seconds |
Started | Jun 27 06:56:22 PM PDT 24 |
Finished | Jun 27 06:58:41 PM PDT 24 |
Peak memory | 370348 kb |
Host | smart-93ad0243-08eb-4755-89a6-f02b536b0452 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756393257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 48.sram_ctrl_max_throughput.2756393257 |
Directory | /workspace/48.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_mem_partial_access.3973439246 |
Short name | T733 |
Test name | |
Test status | |
Simulation time | 19152056251 ps |
CPU time | 68.03 seconds |
Started | Jun 27 06:56:22 PM PDT 24 |
Finished | Jun 27 06:57:32 PM PDT 24 |
Peak memory | 211408 kb |
Host | smart-29702533-efcf-4d9e-a1db-27ad15294b98 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973439246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_mem_partial_access.3973439246 |
Directory | /workspace/48.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_mem_walk.1896961226 |
Short name | T552 |
Test name | |
Test status | |
Simulation time | 3951807891 ps |
CPU time | 126.79 seconds |
Started | Jun 27 06:56:22 PM PDT 24 |
Finished | Jun 27 06:58:31 PM PDT 24 |
Peak memory | 211756 kb |
Host | smart-8159e5a9-0829-4cce-bfe5-f878822ac96f |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896961226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr l_mem_walk.1896961226 |
Directory | /workspace/48.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_multiple_keys.631414534 |
Short name | T511 |
Test name | |
Test status | |
Simulation time | 29163242235 ps |
CPU time | 1314.99 seconds |
Started | Jun 27 06:56:09 PM PDT 24 |
Finished | Jun 27 07:18:06 PM PDT 24 |
Peak memory | 376888 kb |
Host | smart-c77b027c-03cf-4649-b723-fe0bb7a83872 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631414534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multip le_keys.631414534 |
Directory | /workspace/48.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_partial_access.2812025955 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 2553554172 ps |
CPU time | 8.84 seconds |
Started | Jun 27 06:56:12 PM PDT 24 |
Finished | Jun 27 06:56:22 PM PDT 24 |
Peak memory | 214848 kb |
Host | smart-fa70eb3b-84f6-4ce7-a893-8992c5a04a21 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812025955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48. sram_ctrl_partial_access.2812025955 |
Directory | /workspace/48.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.301559136 |
Short name | T924 |
Test name | |
Test status | |
Simulation time | 13300797633 ps |
CPU time | 315.04 seconds |
Started | Jun 27 06:56:22 PM PDT 24 |
Finished | Jun 27 07:01:39 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-2a2ce110-5a4e-4350-9d11-0c3c6da2ecdd |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301559136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 48.sram_ctrl_partial_access_b2b.301559136 |
Directory | /workspace/48.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_ram_cfg.2467905259 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 359249390 ps |
CPU time | 3.21 seconds |
Started | Jun 27 06:56:24 PM PDT 24 |
Finished | Jun 27 06:56:28 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-a4e719cd-ee4f-4e49-80cd-5e98b5b3d7ca |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467905259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.2467905259 |
Directory | /workspace/48.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_regwen.3857588346 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 9209864773 ps |
CPU time | 235.34 seconds |
Started | Jun 27 06:56:25 PM PDT 24 |
Finished | Jun 27 07:00:22 PM PDT 24 |
Peak memory | 368272 kb |
Host | smart-7147dbd0-9acc-42ec-aad3-3d782c71add8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857588346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.3857588346 |
Directory | /workspace/48.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_smoke.3290548601 |
Short name | T489 |
Test name | |
Test status | |
Simulation time | 3506518503 ps |
CPU time | 145.22 seconds |
Started | Jun 27 06:56:09 PM PDT 24 |
Finished | Jun 27 06:58:36 PM PDT 24 |
Peak memory | 367460 kb |
Host | smart-237b6fe9-a191-4f9e-896c-bb4c52d6350e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290548601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.3290548601 |
Directory | /workspace/48.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_all.2336761201 |
Short name | T711 |
Test name | |
Test status | |
Simulation time | 302310152684 ps |
CPU time | 4819.47 seconds |
Started | Jun 27 06:56:24 PM PDT 24 |
Finished | Jun 27 08:16:45 PM PDT 24 |
Peak memory | 381812 kb |
Host | smart-401feceb-fea4-44eb-86df-e3d671f76d6b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336761201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 48.sram_ctrl_stress_all.2336761201 |
Directory | /workspace/48.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1388586329 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 6005584500 ps |
CPU time | 48.64 seconds |
Started | Jun 27 06:56:22 PM PDT 24 |
Finished | Jun 27 06:57:13 PM PDT 24 |
Peak memory | 213108 kb |
Host | smart-a415ef7c-c43e-4eb4-ab29-028ee59042e5 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1388586329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.1388586329 |
Directory | /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_pipeline.952218318 |
Short name | T539 |
Test name | |
Test status | |
Simulation time | 21755118473 ps |
CPU time | 354.05 seconds |
Started | Jun 27 06:56:12 PM PDT 24 |
Finished | Jun 27 07:02:07 PM PDT 24 |
Peak memory | 203044 kb |
Host | smart-8efc9f86-29b2-4ef5-8f55-5e5d697385e9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952218318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48 .sram_ctrl_stress_pipeline.952218318 |
Directory | /workspace/48.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3923501169 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 785344339 ps |
CPU time | 136.6 seconds |
Started | Jun 27 06:56:24 PM PDT 24 |
Finished | Jun 27 06:58:42 PM PDT 24 |
Peak memory | 370372 kb |
Host | smart-dd9bf91b-386b-43ac-bd08-2154dd320414 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923501169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.3923501169 |
Directory | /workspace/48.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_access_during_key_req.1258768684 |
Short name | T844 |
Test name | |
Test status | |
Simulation time | 26520463312 ps |
CPU time | 346.5 seconds |
Started | Jun 27 06:56:40 PM PDT 24 |
Finished | Jun 27 07:02:27 PM PDT 24 |
Peak memory | 350100 kb |
Host | smart-28d23503-d37c-4e69-9df3-931d50504c1c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258768684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 49.sram_ctrl_access_during_key_req.1258768684 |
Directory | /workspace/49.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_alert_test.4262543769 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 27632076 ps |
CPU time | 0.67 seconds |
Started | Jun 27 06:56:41 PM PDT 24 |
Finished | Jun 27 06:56:43 PM PDT 24 |
Peak memory | 202412 kb |
Host | smart-67d8eeb9-88aa-4374-8fc3-bc6d5104d009 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262543769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.4262543769 |
Directory | /workspace/49.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_bijection.410056079 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 170658361835 ps |
CPU time | 748.39 seconds |
Started | Jun 27 06:56:24 PM PDT 24 |
Finished | Jun 27 07:08:54 PM PDT 24 |
Peak memory | 202976 kb |
Host | smart-362d7603-87c1-4e65-bad5-8c54856a5bc9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410056079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection. 410056079 |
Directory | /workspace/49.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_executable.3368669231 |
Short name | T771 |
Test name | |
Test status | |
Simulation time | 18900440309 ps |
CPU time | 1075.25 seconds |
Started | Jun 27 06:56:40 PM PDT 24 |
Finished | Jun 27 07:14:36 PM PDT 24 |
Peak memory | 372600 kb |
Host | smart-0271954a-f1e9-4dde-aa54-f8635e09f13c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368669231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executab le.3368669231 |
Directory | /workspace/49.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_lc_escalation.214656208 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 44595559374 ps |
CPU time | 61.3 seconds |
Started | Jun 27 06:56:41 PM PDT 24 |
Finished | Jun 27 06:57:44 PM PDT 24 |
Peak memory | 203056 kb |
Host | smart-641f43fe-d76f-4eeb-9d40-0768ba0404fd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214656208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_esc alation.214656208 |
Directory | /workspace/49.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_max_throughput.3383466493 |
Short name | T826 |
Test name | |
Test status | |
Simulation time | 702925963 ps |
CPU time | 17.18 seconds |
Started | Jun 27 06:56:42 PM PDT 24 |
Finished | Jun 27 06:57:00 PM PDT 24 |
Peak memory | 251836 kb |
Host | smart-8a6c3768-89ce-4557-b2a5-c3f60f8b5d2f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383466493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 49.sram_ctrl_max_throughput.3383466493 |
Directory | /workspace/49.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_mem_partial_access.1553340113 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 5007649414 ps |
CPU time | 85.18 seconds |
Started | Jun 27 06:56:41 PM PDT 24 |
Finished | Jun 27 06:58:07 PM PDT 24 |
Peak memory | 211080 kb |
Host | smart-b0ec0c85-201b-4222-be70-a7695309e431 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553340113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_mem_partial_access.1553340113 |
Directory | /workspace/49.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_mem_walk.3032424200 |
Short name | T836 |
Test name | |
Test status | |
Simulation time | 60252528713 ps |
CPU time | 324.1 seconds |
Started | Jun 27 06:56:42 PM PDT 24 |
Finished | Jun 27 07:02:07 PM PDT 24 |
Peak memory | 210988 kb |
Host | smart-b08f1f9b-24a3-4b4c-8b7d-473c84b35dfd |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032424200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr l_mem_walk.3032424200 |
Directory | /workspace/49.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_multiple_keys.1880155479 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 98826251592 ps |
CPU time | 876.61 seconds |
Started | Jun 27 06:56:21 PM PDT 24 |
Finished | Jun 27 07:10:59 PM PDT 24 |
Peak memory | 378780 kb |
Host | smart-8f4fb6bc-db33-465d-b86e-453bc4765cfe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880155479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multi ple_keys.1880155479 |
Directory | /workspace/49.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_partial_access.3424498713 |
Short name | T664 |
Test name | |
Test status | |
Simulation time | 2641100408 ps |
CPU time | 7.17 seconds |
Started | Jun 27 06:56:24 PM PDT 24 |
Finished | Jun 27 06:56:33 PM PDT 24 |
Peak memory | 202692 kb |
Host | smart-10e589fe-cc85-4887-a6c3-f6186c0251a7 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424498713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49. sram_ctrl_partial_access.3424498713 |
Directory | /workspace/49.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1800935770 |
Short name | T568 |
Test name | |
Test status | |
Simulation time | 20142029085 ps |
CPU time | 483.97 seconds |
Started | Jun 27 06:56:25 PM PDT 24 |
Finished | Jun 27 07:04:30 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-01a55c6d-6567-4bb4-b780-2c5596f9e5c4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800935770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 49.sram_ctrl_partial_access_b2b.1800935770 |
Directory | /workspace/49.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_ram_cfg.410996824 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 358091060 ps |
CPU time | 3.57 seconds |
Started | Jun 27 06:56:40 PM PDT 24 |
Finished | Jun 27 06:56:44 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-875ddceb-6f2f-4c30-8d02-c8cd6f026a00 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410996824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.410996824 |
Directory | /workspace/49.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_regwen.1033855173 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 10018342285 ps |
CPU time | 673.88 seconds |
Started | Jun 27 06:56:43 PM PDT 24 |
Finished | Jun 27 07:07:58 PM PDT 24 |
Peak memory | 376696 kb |
Host | smart-945bfd8c-9d56-4ac8-94d7-7f8bd0b7f951 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033855173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.1033855173 |
Directory | /workspace/49.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_smoke.3500719826 |
Short name | T644 |
Test name | |
Test status | |
Simulation time | 355039198 ps |
CPU time | 6.34 seconds |
Started | Jun 27 06:56:22 PM PDT 24 |
Finished | Jun 27 06:56:30 PM PDT 24 |
Peak memory | 218972 kb |
Host | smart-ac329431-5dbc-4e3d-97fd-02782006124f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500719826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.3500719826 |
Directory | /workspace/49.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1404206811 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 517303033 ps |
CPU time | 17.05 seconds |
Started | Jun 27 06:56:43 PM PDT 24 |
Finished | Jun 27 06:57:01 PM PDT 24 |
Peak memory | 211072 kb |
Host | smart-5544cf24-8490-4c07-9fd5-7b5384b799ee |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1404206811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.1404206811 |
Directory | /workspace/49.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_pipeline.2266278165 |
Short name | T846 |
Test name | |
Test status | |
Simulation time | 34373577318 ps |
CPU time | 325.36 seconds |
Started | Jun 27 06:56:22 PM PDT 24 |
Finished | Jun 27 07:01:49 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-13b23481-c68d-42c6-a5b5-824bdf6c66c4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266278165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_stress_pipeline.2266278165 |
Directory | /workspace/49.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.164304853 |
Short name | T712 |
Test name | |
Test status | |
Simulation time | 3230858386 ps |
CPU time | 63.97 seconds |
Started | Jun 27 06:56:41 PM PDT 24 |
Finished | Jun 27 06:57:46 PM PDT 24 |
Peak memory | 310380 kb |
Host | smart-5c82e461-5870-4a6e-adea-1198aa58ae19 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164304853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 49.sram_ctrl_throughput_w_partial_write.164304853 |
Directory | /workspace/49.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_access_during_key_req.1768047210 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 4597350828 ps |
CPU time | 31.44 seconds |
Started | Jun 27 06:49:26 PM PDT 24 |
Finished | Jun 27 06:50:01 PM PDT 24 |
Peak memory | 255836 kb |
Host | smart-3a4a4eb2-2357-44d3-a4c0-ab0e81f877f2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768047210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_access_during_key_req.1768047210 |
Directory | /workspace/5.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_alert_test.3310259378 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 23119936 ps |
CPU time | 0.74 seconds |
Started | Jun 27 06:49:27 PM PDT 24 |
Finished | Jun 27 06:49:32 PM PDT 24 |
Peak memory | 202368 kb |
Host | smart-53d3268a-0fbd-411c-9665-5e69a6fa24f9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310259378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.3310259378 |
Directory | /workspace/5.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_bijection.3170018520 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 10826910763 ps |
CPU time | 731.51 seconds |
Started | Jun 27 06:49:26 PM PDT 24 |
Finished | Jun 27 07:01:41 PM PDT 24 |
Peak memory | 202976 kb |
Host | smart-9dad412b-927d-4bab-85e7-59155a2fbab4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170018520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection. 3170018520 |
Directory | /workspace/5.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_executable.2738166403 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 22353747746 ps |
CPU time | 1001.9 seconds |
Started | Jun 27 06:49:24 PM PDT 24 |
Finished | Jun 27 07:06:08 PM PDT 24 |
Peak memory | 363400 kb |
Host | smart-a6aaa08c-10e7-4659-a059-fbc35f203988 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738166403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl e.2738166403 |
Directory | /workspace/5.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_lc_escalation.3087469127 |
Short name | T599 |
Test name | |
Test status | |
Simulation time | 23505542685 ps |
CPU time | 35.31 seconds |
Started | Jun 27 06:49:27 PM PDT 24 |
Finished | Jun 27 06:50:07 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-a728479d-21d5-4e74-a0a3-f9d9c49dbbce |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087469127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esc alation.3087469127 |
Directory | /workspace/5.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_max_throughput.1960402253 |
Short name | T938 |
Test name | |
Test status | |
Simulation time | 2792235341 ps |
CPU time | 6.14 seconds |
Started | Jun 27 06:49:28 PM PDT 24 |
Finished | Jun 27 06:49:38 PM PDT 24 |
Peak memory | 202736 kb |
Host | smart-b0ea73d4-875c-42f2-bcf7-ae1ffb14c9b1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960402253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 5.sram_ctrl_max_throughput.1960402253 |
Directory | /workspace/5.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_mem_partial_access.3646169855 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 15782411339 ps |
CPU time | 81.49 seconds |
Started | Jun 27 06:49:27 PM PDT 24 |
Finished | Jun 27 06:50:53 PM PDT 24 |
Peak memory | 219344 kb |
Host | smart-5f49c833-9b78-46af-b1bd-2dd1290114de |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646169855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_mem_partial_access.3646169855 |
Directory | /workspace/5.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_mem_walk.3187731463 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 8999811801 ps |
CPU time | 189.95 seconds |
Started | Jun 27 06:49:24 PM PDT 24 |
Finished | Jun 27 06:52:36 PM PDT 24 |
Peak memory | 211016 kb |
Host | smart-6dfc4f35-98be-40e0-9def-a334b988f174 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187731463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl _mem_walk.3187731463 |
Directory | /workspace/5.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_multiple_keys.774022331 |
Short name | T894 |
Test name | |
Test status | |
Simulation time | 18734550640 ps |
CPU time | 1500.7 seconds |
Started | Jun 27 06:49:24 PM PDT 24 |
Finished | Jun 27 07:14:27 PM PDT 24 |
Peak memory | 379744 kb |
Host | smart-aafd5d45-4c20-4e6f-ac86-ce8638f6e304 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774022331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multipl e_keys.774022331 |
Directory | /workspace/5.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_partial_access.2473371394 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 1834887362 ps |
CPU time | 22.09 seconds |
Started | Jun 27 06:49:28 PM PDT 24 |
Finished | Jun 27 06:49:55 PM PDT 24 |
Peak memory | 202740 kb |
Host | smart-aaaec66b-e65a-4ee5-a4ca-c57c329b4294 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473371394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s ram_ctrl_partial_access.2473371394 |
Directory | /workspace/5.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2081095952 |
Short name | T600 |
Test name | |
Test status | |
Simulation time | 6549491731 ps |
CPU time | 366.67 seconds |
Started | Jun 27 06:49:24 PM PDT 24 |
Finished | Jun 27 06:55:33 PM PDT 24 |
Peak memory | 202852 kb |
Host | smart-b21f69ac-0aa5-459e-9664-6a4c2b524708 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081095952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 5.sram_ctrl_partial_access_b2b.2081095952 |
Directory | /workspace/5.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_ram_cfg.2449177599 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 710820901 ps |
CPU time | 3.61 seconds |
Started | Jun 27 06:49:27 PM PDT 24 |
Finished | Jun 27 06:49:35 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-0cf581f5-0215-4d64-800f-3255641291a4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449177599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.2449177599 |
Directory | /workspace/5.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_regwen.631328087 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 105297158002 ps |
CPU time | 912.05 seconds |
Started | Jun 27 06:49:23 PM PDT 24 |
Finished | Jun 27 07:04:38 PM PDT 24 |
Peak memory | 372612 kb |
Host | smart-587ae349-9843-40e8-ada8-d532144c29b2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631328087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.631328087 |
Directory | /workspace/5.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_smoke.514633374 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 758339976 ps |
CPU time | 10.98 seconds |
Started | Jun 27 06:49:26 PM PDT 24 |
Finished | Jun 27 06:49:41 PM PDT 24 |
Peak memory | 202752 kb |
Host | smart-ce7ab203-6c95-423e-bc97-ec62217acf39 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514633374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.514633374 |
Directory | /workspace/5.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_all.1649600218 |
Short name | T688 |
Test name | |
Test status | |
Simulation time | 176231875446 ps |
CPU time | 2092.99 seconds |
Started | Jun 27 06:49:24 PM PDT 24 |
Finished | Jun 27 07:24:19 PM PDT 24 |
Peak memory | 378744 kb |
Host | smart-42f24951-3472-4baf-b947-4900254b357c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649600218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 5.sram_ctrl_stress_all.1649600218 |
Directory | /workspace/5.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3326561585 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 276281224 ps |
CPU time | 11.13 seconds |
Started | Jun 27 06:49:28 PM PDT 24 |
Finished | Jun 27 06:49:44 PM PDT 24 |
Peak memory | 211120 kb |
Host | smart-9344d83d-b728-4270-9691-7c763f1a5bd7 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3326561585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.3326561585 |
Directory | /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_pipeline.993380655 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 13784199763 ps |
CPU time | 161.22 seconds |
Started | Jun 27 06:49:26 PM PDT 24 |
Finished | Jun 27 06:52:10 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-2b8b9519-4599-4814-86c0-7f2337c40c33 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993380655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5. sram_ctrl_stress_pipeline.993380655 |
Directory | /workspace/5.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2737923785 |
Short name | T883 |
Test name | |
Test status | |
Simulation time | 1605829252 ps |
CPU time | 176.64 seconds |
Started | Jun 27 06:49:23 PM PDT 24 |
Finished | Jun 27 06:52:21 PM PDT 24 |
Peak memory | 372540 kb |
Host | smart-2663a21a-8c50-47a2-982a-4e5712a75b01 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737923785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.2737923785 |
Directory | /workspace/5.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_access_during_key_req.1414704530 |
Short name | T468 |
Test name | |
Test status | |
Simulation time | 33023264563 ps |
CPU time | 926.3 seconds |
Started | Jun 27 06:49:26 PM PDT 24 |
Finished | Jun 27 07:04:55 PM PDT 24 |
Peak memory | 375016 kb |
Host | smart-ea92963e-3130-4dd5-95bc-e683ac9d89a6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414704530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_access_during_key_req.1414704530 |
Directory | /workspace/6.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_alert_test.714676629 |
Short name | T518 |
Test name | |
Test status | |
Simulation time | 16599027 ps |
CPU time | 0.68 seconds |
Started | Jun 27 06:49:26 PM PDT 24 |
Finished | Jun 27 06:49:30 PM PDT 24 |
Peak memory | 202408 kb |
Host | smart-3e2cac47-606c-493a-8ef3-98561d586cf9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714676629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.714676629 |
Directory | /workspace/6.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_bijection.2179042930 |
Short name | T805 |
Test name | |
Test status | |
Simulation time | 374378886778 ps |
CPU time | 1609.75 seconds |
Started | Jun 27 06:49:26 PM PDT 24 |
Finished | Jun 27 07:16:20 PM PDT 24 |
Peak memory | 203012 kb |
Host | smart-f4a3aa40-fce1-4003-92d4-54daf66a05b3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179042930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection. 2179042930 |
Directory | /workspace/6.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_executable.338066852 |
Short name | T532 |
Test name | |
Test status | |
Simulation time | 12374584991 ps |
CPU time | 496.42 seconds |
Started | Jun 27 06:49:28 PM PDT 24 |
Finished | Jun 27 06:57:49 PM PDT 24 |
Peak memory | 370056 kb |
Host | smart-da504682-c93e-48a1-b72c-9f0f9963828d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338066852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable .338066852 |
Directory | /workspace/6.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_lc_escalation.378931773 |
Short name | T849 |
Test name | |
Test status | |
Simulation time | 17420909752 ps |
CPU time | 63.7 seconds |
Started | Jun 27 06:49:28 PM PDT 24 |
Finished | Jun 27 06:50:36 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-e76a23d0-1a2a-4e5e-be87-2fa0d339c308 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378931773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esca lation.378931773 |
Directory | /workspace/6.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_max_throughput.231263472 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 2854834722 ps |
CPU time | 44.57 seconds |
Started | Jun 27 06:49:23 PM PDT 24 |
Finished | Jun 27 06:50:10 PM PDT 24 |
Peak memory | 280452 kb |
Host | smart-96ec94e7-e0ab-4072-8c6c-ba29b2f7dbde |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231263472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 6.sram_ctrl_max_throughput.231263472 |
Directory | /workspace/6.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_mem_partial_access.3895559643 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 5555468647 ps |
CPU time | 82.35 seconds |
Started | Jun 27 06:49:25 PM PDT 24 |
Finished | Jun 27 06:50:50 PM PDT 24 |
Peak memory | 211064 kb |
Host | smart-541d4981-a809-44d2-9ef7-9ae66d674525 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895559643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .sram_ctrl_mem_partial_access.3895559643 |
Directory | /workspace/6.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_mem_walk.797172138 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 25674229589 ps |
CPU time | 164.11 seconds |
Started | Jun 27 06:49:28 PM PDT 24 |
Finished | Jun 27 06:52:17 PM PDT 24 |
Peak memory | 211024 kb |
Host | smart-5c4c86c6-134a-45e6-8af6-8ab5025e47d5 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797172138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ mem_walk.797172138 |
Directory | /workspace/6.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_multiple_keys.3131613472 |
Short name | T693 |
Test name | |
Test status | |
Simulation time | 13614594625 ps |
CPU time | 353.03 seconds |
Started | Jun 27 06:49:26 PM PDT 24 |
Finished | Jun 27 06:55:23 PM PDT 24 |
Peak memory | 343772 kb |
Host | smart-e7b0a71c-090c-4c1f-a7a0-114544f7caac |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131613472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip le_keys.3131613472 |
Directory | /workspace/6.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_partial_access.1043789619 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 607478383 ps |
CPU time | 19.29 seconds |
Started | Jun 27 06:49:27 PM PDT 24 |
Finished | Jun 27 06:49:51 PM PDT 24 |
Peak memory | 202764 kb |
Host | smart-4cbd2fc0-c716-4ec8-9178-7a5fa37ee6f4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043789619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s ram_ctrl_partial_access.1043789619 |
Directory | /workspace/6.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.283607418 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 11079508544 ps |
CPU time | 162.44 seconds |
Started | Jun 27 06:49:26 PM PDT 24 |
Finished | Jun 27 06:52:11 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-bcd9a830-522a-406d-b72b-6349cd5f54bb |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283607418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 6.sram_ctrl_partial_access_b2b.283607418 |
Directory | /workspace/6.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_ram_cfg.4048999751 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 344336294 ps |
CPU time | 3.4 seconds |
Started | Jun 27 06:49:24 PM PDT 24 |
Finished | Jun 27 06:49:29 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-7a3a486d-5f66-412e-a610-3139a2509798 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048999751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.4048999751 |
Directory | /workspace/6.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_regwen.792933239 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 8054487065 ps |
CPU time | 759.41 seconds |
Started | Jun 27 06:49:29 PM PDT 24 |
Finished | Jun 27 07:02:13 PM PDT 24 |
Peak memory | 374716 kb |
Host | smart-fa9e2fae-361c-4911-a67f-afd14212d3b4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792933239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.792933239 |
Directory | /workspace/6.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_smoke.220841408 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 1539356851 ps |
CPU time | 18.53 seconds |
Started | Jun 27 06:49:26 PM PDT 24 |
Finished | Jun 27 06:49:47 PM PDT 24 |
Peak memory | 202680 kb |
Host | smart-a6976e55-1693-4828-b50f-32423a822c41 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220841408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.220841408 |
Directory | /workspace/6.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_all.2163176947 |
Short name | T514 |
Test name | |
Test status | |
Simulation time | 86770898003 ps |
CPU time | 2437.72 seconds |
Started | Jun 27 06:49:27 PM PDT 24 |
Finished | Jun 27 07:30:09 PM PDT 24 |
Peak memory | 390028 kb |
Host | smart-79e368c4-ad4d-4507-a193-d24a08f7d650 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163176947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 6.sram_ctrl_stress_all.2163176947 |
Directory | /workspace/6.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1030894559 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 2319644120 ps |
CPU time | 21.96 seconds |
Started | Jun 27 06:49:25 PM PDT 24 |
Finished | Jun 27 06:49:49 PM PDT 24 |
Peak memory | 211224 kb |
Host | smart-f6b6e21e-05e7-4b16-b83d-ff2ab5783447 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1030894559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.1030894559 |
Directory | /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_pipeline.2757612067 |
Short name | T583 |
Test name | |
Test status | |
Simulation time | 18537482225 ps |
CPU time | 298.09 seconds |
Started | Jun 27 06:49:29 PM PDT 24 |
Finished | Jun 27 06:54:31 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-c2964f19-502f-4327-bf31-dccbe698a93b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757612067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .sram_ctrl_stress_pipeline.2757612067 |
Directory | /workspace/6.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3379459375 |
Short name | T709 |
Test name | |
Test status | |
Simulation time | 799457940 ps |
CPU time | 86.47 seconds |
Started | Jun 27 06:49:24 PM PDT 24 |
Finished | Jun 27 06:50:52 PM PDT 24 |
Peak memory | 339728 kb |
Host | smart-151aad9b-0ed5-4dc8-9fb1-6ff690708cb0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379459375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.3379459375 |
Directory | /workspace/6.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_access_during_key_req.2893539918 |
Short name | T823 |
Test name | |
Test status | |
Simulation time | 60669262452 ps |
CPU time | 848.87 seconds |
Started | Jun 27 06:49:26 PM PDT 24 |
Finished | Jun 27 07:03:38 PM PDT 24 |
Peak memory | 348076 kb |
Host | smart-870cb258-28c7-4ff1-9cf3-b1f3ce101d45 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893539918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_access_during_key_req.2893539918 |
Directory | /workspace/7.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_alert_test.526808024 |
Short name | T564 |
Test name | |
Test status | |
Simulation time | 44308713 ps |
CPU time | 0.66 seconds |
Started | Jun 27 06:49:27 PM PDT 24 |
Finished | Jun 27 06:49:33 PM PDT 24 |
Peak memory | 202428 kb |
Host | smart-d658c275-d082-4ac1-ac3b-2e91db63b1a6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526808024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.526808024 |
Directory | /workspace/7.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_bijection.1753311361 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 77879144209 ps |
CPU time | 1292.7 seconds |
Started | Jun 27 06:49:20 PM PDT 24 |
Finished | Jun 27 07:10:55 PM PDT 24 |
Peak memory | 203504 kb |
Host | smart-cb7de9cd-c50e-4391-b0a4-dcaf6bd4754a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753311361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection. 1753311361 |
Directory | /workspace/7.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_executable.3267406134 |
Short name | T464 |
Test name | |
Test status | |
Simulation time | 13782273981 ps |
CPU time | 1037.69 seconds |
Started | Jun 27 06:49:29 PM PDT 24 |
Finished | Jun 27 07:06:51 PM PDT 24 |
Peak memory | 371796 kb |
Host | smart-54ef8f9d-d168-4c80-966c-3b4eab38d17c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267406134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executabl e.3267406134 |
Directory | /workspace/7.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_lc_escalation.810181839 |
Short name | T928 |
Test name | |
Test status | |
Simulation time | 8891191132 ps |
CPU time | 45.74 seconds |
Started | Jun 27 06:49:27 PM PDT 24 |
Finished | Jun 27 06:50:16 PM PDT 24 |
Peak memory | 211100 kb |
Host | smart-cc446ab6-973f-47fa-9644-246d88c4949d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810181839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esca lation.810181839 |
Directory | /workspace/7.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_max_throughput.2729919978 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 5326757452 ps |
CPU time | 14.73 seconds |
Started | Jun 27 06:49:26 PM PDT 24 |
Finished | Jun 27 06:49:45 PM PDT 24 |
Peak memory | 251876 kb |
Host | smart-495255ee-1515-4cf7-a0e6-114828e3c75a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729919978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 7.sram_ctrl_max_throughput.2729919978 |
Directory | /workspace/7.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_mem_partial_access.1292068156 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 1610458293 ps |
CPU time | 132.5 seconds |
Started | Jun 27 06:49:28 PM PDT 24 |
Finished | Jun 27 06:51:45 PM PDT 24 |
Peak memory | 210936 kb |
Host | smart-73826c28-c2ed-44ec-92b3-4356c906dd03 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292068156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_mem_partial_access.1292068156 |
Directory | /workspace/7.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_mem_walk.1456044014 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 106563629230 ps |
CPU time | 344.93 seconds |
Started | Jun 27 06:49:28 PM PDT 24 |
Finished | Jun 27 06:55:18 PM PDT 24 |
Peak memory | 211268 kb |
Host | smart-6b357f59-93d2-4fcb-83d7-ed3d19ffbd72 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456044014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl _mem_walk.1456044014 |
Directory | /workspace/7.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_multiple_keys.3896428049 |
Short name | T734 |
Test name | |
Test status | |
Simulation time | 13870402085 ps |
CPU time | 770.56 seconds |
Started | Jun 27 06:49:29 PM PDT 24 |
Finished | Jun 27 07:02:24 PM PDT 24 |
Peak memory | 379728 kb |
Host | smart-d53ef8db-6779-484c-8f1b-28f40f3f0d4d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896428049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip le_keys.3896428049 |
Directory | /workspace/7.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_partial_access.496089114 |
Short name | T722 |
Test name | |
Test status | |
Simulation time | 2260519593 ps |
CPU time | 8.18 seconds |
Started | Jun 27 06:49:25 PM PDT 24 |
Finished | Jun 27 06:49:36 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-633bc098-a49f-469e-b2ce-245252fc8ab8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496089114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sr am_ctrl_partial_access.496089114 |
Directory | /workspace/7.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.52824053 |
Short name | T531 |
Test name | |
Test status | |
Simulation time | 21259983903 ps |
CPU time | 308.46 seconds |
Started | Jun 27 06:49:26 PM PDT 24 |
Finished | Jun 27 06:54:37 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-54d0e848-bea9-4c0c-be5b-02bcd2ebdad5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52824053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_partial_access_b2b.52824053 |
Directory | /workspace/7.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_ram_cfg.102625562 |
Short name | T608 |
Test name | |
Test status | |
Simulation time | 1343331397 ps |
CPU time | 3.39 seconds |
Started | Jun 27 06:49:27 PM PDT 24 |
Finished | Jun 27 06:49:35 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-83d2094a-660d-492c-b4ae-26a254e32a06 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102625562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.102625562 |
Directory | /workspace/7.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_regwen.1057782733 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 59364373263 ps |
CPU time | 929.72 seconds |
Started | Jun 27 06:49:28 PM PDT 24 |
Finished | Jun 27 07:05:02 PM PDT 24 |
Peak memory | 375648 kb |
Host | smart-ccf7410d-f74f-4f2d-b70c-56dccb574560 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057782733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.1057782733 |
Directory | /workspace/7.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_smoke.4293041356 |
Short name | T871 |
Test name | |
Test status | |
Simulation time | 3081425996 ps |
CPU time | 8.86 seconds |
Started | Jun 27 06:49:26 PM PDT 24 |
Finished | Jun 27 06:49:39 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-fb355024-bd6d-41bf-8029-01a227f2a3d0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293041356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.4293041356 |
Directory | /workspace/7.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_all.1635163361 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 84482343834 ps |
CPU time | 165.56 seconds |
Started | Jun 27 06:49:26 PM PDT 24 |
Finished | Jun 27 06:52:16 PM PDT 24 |
Peak memory | 274384 kb |
Host | smart-cc085c60-1170-4ac5-9aad-46a6203a86a1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635163361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 7.sram_ctrl_stress_all.1635163361 |
Directory | /workspace/7.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3474323305 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 4070240117 ps |
CPU time | 33.98 seconds |
Started | Jun 27 06:49:28 PM PDT 24 |
Finished | Jun 27 06:50:07 PM PDT 24 |
Peak memory | 211604 kb |
Host | smart-df0a705d-b72f-4605-9a33-1e3933281602 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3474323305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.3474323305 |
Directory | /workspace/7.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_pipeline.1545441771 |
Short name | T797 |
Test name | |
Test status | |
Simulation time | 6743828441 ps |
CPU time | 176.23 seconds |
Started | Jun 27 06:49:27 PM PDT 24 |
Finished | Jun 27 06:52:27 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-04bd7c11-ba0e-4326-b599-a214a0306d68 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545441771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_stress_pipeline.1545441771 |
Directory | /workspace/7.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1231714082 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 1532721733 ps |
CPU time | 54.46 seconds |
Started | Jun 27 06:49:29 PM PDT 24 |
Finished | Jun 27 06:50:28 PM PDT 24 |
Peak memory | 301084 kb |
Host | smart-e5853c67-7449-42a0-9666-4d1aeecfed86 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231714082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.1231714082 |
Directory | /workspace/7.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_access_during_key_req.4031090237 |
Short name | T462 |
Test name | |
Test status | |
Simulation time | 24228801887 ps |
CPU time | 989.34 seconds |
Started | Jun 27 06:49:40 PM PDT 24 |
Finished | Jun 27 07:06:14 PM PDT 24 |
Peak memory | 378724 kb |
Host | smart-acc2da33-df52-449f-bb64-542edc545181 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031090237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_access_during_key_req.4031090237 |
Directory | /workspace/8.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_alert_test.891755694 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 27578804 ps |
CPU time | 0.73 seconds |
Started | Jun 27 06:49:39 PM PDT 24 |
Finished | Jun 27 06:49:44 PM PDT 24 |
Peak memory | 202400 kb |
Host | smart-347e339f-30ac-47be-b38b-fa66b42a2c3e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891755694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.891755694 |
Directory | /workspace/8.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_bijection.1765981822 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 28937454271 ps |
CPU time | 1021.17 seconds |
Started | Jun 27 06:49:27 PM PDT 24 |
Finished | Jun 27 07:06:33 PM PDT 24 |
Peak memory | 202992 kb |
Host | smart-971ffecf-d870-4844-ae87-a0214d6b18ac |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765981822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection. 1765981822 |
Directory | /workspace/8.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_executable.3856915372 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 163508743466 ps |
CPU time | 1226.63 seconds |
Started | Jun 27 06:49:44 PM PDT 24 |
Finished | Jun 27 07:10:15 PM PDT 24 |
Peak memory | 380800 kb |
Host | smart-96b6a413-82dd-44a8-bfbf-56f997efc7a4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856915372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executabl e.3856915372 |
Directory | /workspace/8.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_lc_escalation.3685152975 |
Short name | T915 |
Test name | |
Test status | |
Simulation time | 26995472662 ps |
CPU time | 48.01 seconds |
Started | Jun 27 06:49:39 PM PDT 24 |
Finished | Jun 27 06:50:31 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-94b96c6a-31de-40fe-8f62-4b3c9b07f97a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685152975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esc alation.3685152975 |
Directory | /workspace/8.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_max_throughput.2647266449 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 765166381 ps |
CPU time | 151.74 seconds |
Started | Jun 27 06:49:41 PM PDT 24 |
Finished | Jun 27 06:52:17 PM PDT 24 |
Peak memory | 367272 kb |
Host | smart-33615d4b-766a-42cf-ad4f-d8dff136a4d9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647266449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 8.sram_ctrl_max_throughput.2647266449 |
Directory | /workspace/8.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_mem_partial_access.2550755493 |
Short name | T752 |
Test name | |
Test status | |
Simulation time | 5251210849 ps |
CPU time | 184.24 seconds |
Started | Jun 27 06:49:39 PM PDT 24 |
Finished | Jun 27 06:52:47 PM PDT 24 |
Peak memory | 219200 kb |
Host | smart-cbad7041-8c14-4970-a890-977c76210432 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550755493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_mem_partial_access.2550755493 |
Directory | /workspace/8.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_mem_walk.1776338338 |
Short name | T554 |
Test name | |
Test status | |
Simulation time | 22837705337 ps |
CPU time | 339.33 seconds |
Started | Jun 27 06:49:43 PM PDT 24 |
Finished | Jun 27 06:55:28 PM PDT 24 |
Peak memory | 211220 kb |
Host | smart-efeb990c-e842-419e-af82-e4c0ddf6e170 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776338338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl _mem_walk.1776338338 |
Directory | /workspace/8.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_multiple_keys.1302024528 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 5075894252 ps |
CPU time | 706.74 seconds |
Started | Jun 27 06:49:27 PM PDT 24 |
Finished | Jun 27 07:01:18 PM PDT 24 |
Peak memory | 372900 kb |
Host | smart-935738f0-835c-4f37-81b3-7704fd22aedb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302024528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multip le_keys.1302024528 |
Directory | /workspace/8.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_partial_access.1263706076 |
Short name | T537 |
Test name | |
Test status | |
Simulation time | 3902457048 ps |
CPU time | 26.05 seconds |
Started | Jun 27 06:49:26 PM PDT 24 |
Finished | Jun 27 06:49:55 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-2766fcef-8479-4668-8040-f79204eae232 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263706076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s ram_ctrl_partial_access.1263706076 |
Directory | /workspace/8.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2057320547 |
Short name | T902 |
Test name | |
Test status | |
Simulation time | 7075506450 ps |
CPU time | 182.45 seconds |
Started | Jun 27 06:49:27 PM PDT 24 |
Finished | Jun 27 06:52:34 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-0aa811a8-9ff7-4255-92af-ef952980c537 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057320547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 8.sram_ctrl_partial_access_b2b.2057320547 |
Directory | /workspace/8.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_ram_cfg.1540828353 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 725495838 ps |
CPU time | 3.52 seconds |
Started | Jun 27 06:49:39 PM PDT 24 |
Finished | Jun 27 06:49:47 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-1750964d-9c19-4f82-968b-3d5625a91d93 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540828353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.1540828353 |
Directory | /workspace/8.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_regwen.2460003598 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 18749235606 ps |
CPU time | 1687.53 seconds |
Started | Jun 27 06:49:44 PM PDT 24 |
Finished | Jun 27 07:17:56 PM PDT 24 |
Peak memory | 378680 kb |
Host | smart-3ac14bd1-7332-4d37-8f42-898a7cb92e92 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460003598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.2460003598 |
Directory | /workspace/8.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_smoke.1353870746 |
Short name | T507 |
Test name | |
Test status | |
Simulation time | 16645250049 ps |
CPU time | 19.21 seconds |
Started | Jun 27 06:49:26 PM PDT 24 |
Finished | Jun 27 06:49:50 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-a2b17e6b-fcca-4b25-909d-c61c9a183ccf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353870746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.1353870746 |
Directory | /workspace/8.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_all.2770497830 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 92078425809 ps |
CPU time | 2561.35 seconds |
Started | Jun 27 06:49:39 PM PDT 24 |
Finished | Jun 27 07:32:24 PM PDT 24 |
Peak memory | 380752 kb |
Host | smart-660749bb-4efa-4cb3-bcea-d20925859cc4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770497830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 8.sram_ctrl_stress_all.2770497830 |
Directory | /workspace/8.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2489285238 |
Short name | T860 |
Test name | |
Test status | |
Simulation time | 8528796002 ps |
CPU time | 34.58 seconds |
Started | Jun 27 06:49:39 PM PDT 24 |
Finished | Jun 27 06:50:16 PM PDT 24 |
Peak memory | 211528 kb |
Host | smart-7d6630f5-f18e-47ee-8cec-d0319651caf5 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2489285238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.2489285238 |
Directory | /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_pipeline.3414667864 |
Short name | T580 |
Test name | |
Test status | |
Simulation time | 4313587681 ps |
CPU time | 330.78 seconds |
Started | Jun 27 06:49:26 PM PDT 24 |
Finished | Jun 27 06:55:01 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-fcceae1f-75aa-44bb-ad95-8cee48064939 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414667864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_stress_pipeline.3414667864 |
Directory | /workspace/8.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1072458908 |
Short name | T505 |
Test name | |
Test status | |
Simulation time | 3371342143 ps |
CPU time | 81.95 seconds |
Started | Jun 27 06:49:40 PM PDT 24 |
Finished | Jun 27 06:51:06 PM PDT 24 |
Peak memory | 310772 kb |
Host | smart-48554e5e-6d71-4d77-b1ef-072d9dab319d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072458908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.1072458908 |
Directory | /workspace/8.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_access_during_key_req.4054970046 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 12203111934 ps |
CPU time | 1121.86 seconds |
Started | Jun 27 06:49:42 PM PDT 24 |
Finished | Jun 27 07:08:28 PM PDT 24 |
Peak memory | 372708 kb |
Host | smart-ec7a59eb-3919-45a9-9d3d-8e7188411b1a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054970046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_access_during_key_req.4054970046 |
Directory | /workspace/9.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_alert_test.4262692274 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 33628653 ps |
CPU time | 0.7 seconds |
Started | Jun 27 06:49:37 PM PDT 24 |
Finished | Jun 27 06:49:40 PM PDT 24 |
Peak memory | 202564 kb |
Host | smart-f66f78c4-154e-4b4d-b9c8-d07eb7ab31e8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262692274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.4262692274 |
Directory | /workspace/9.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_bijection.4181359549 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 30771313929 ps |
CPU time | 1047.79 seconds |
Started | Jun 27 06:49:43 PM PDT 24 |
Finished | Jun 27 07:07:15 PM PDT 24 |
Peak memory | 203568 kb |
Host | smart-0407ad93-7e12-4f80-aac0-5d9f0bb7b2d9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181359549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection. 4181359549 |
Directory | /workspace/9.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_executable.2428610635 |
Short name | T892 |
Test name | |
Test status | |
Simulation time | 14703514072 ps |
CPU time | 1072.54 seconds |
Started | Jun 27 06:49:40 PM PDT 24 |
Finished | Jun 27 07:07:36 PM PDT 24 |
Peak memory | 379796 kb |
Host | smart-82bbd5b2-3a78-482e-b6a1-fd7c4f6dff96 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428610635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl e.2428610635 |
Directory | /workspace/9.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_lc_escalation.3214494048 |
Short name | T784 |
Test name | |
Test status | |
Simulation time | 17505472937 ps |
CPU time | 105.84 seconds |
Started | Jun 27 06:49:40 PM PDT 24 |
Finished | Jun 27 06:51:29 PM PDT 24 |
Peak memory | 211068 kb |
Host | smart-76ec5cd9-9523-401f-ae02-58ae3b359d21 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214494048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esc alation.3214494048 |
Directory | /workspace/9.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_max_throughput.1977449022 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 1329355510 ps |
CPU time | 6.2 seconds |
Started | Jun 27 06:49:38 PM PDT 24 |
Finished | Jun 27 06:49:46 PM PDT 24 |
Peak memory | 202676 kb |
Host | smart-a7c83883-d51c-49e3-ab3c-9d6124e5fcb9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977449022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 9.sram_ctrl_max_throughput.1977449022 |
Directory | /workspace/9.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_mem_partial_access.2133716302 |
Short name | T768 |
Test name | |
Test status | |
Simulation time | 7195659642 ps |
CPU time | 121.38 seconds |
Started | Jun 27 06:49:40 PM PDT 24 |
Finished | Jun 27 06:51:45 PM PDT 24 |
Peak memory | 211116 kb |
Host | smart-793de392-f1d6-4d31-97bb-d386e9e5f0e3 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133716302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_mem_partial_access.2133716302 |
Directory | /workspace/9.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_mem_walk.1837880110 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 55278457351 ps |
CPU time | 336.33 seconds |
Started | Jun 27 06:49:38 PM PDT 24 |
Finished | Jun 27 06:55:18 PM PDT 24 |
Peak memory | 211920 kb |
Host | smart-7090055b-422e-4edc-bd04-b7321ccc1a0a |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837880110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl _mem_walk.1837880110 |
Directory | /workspace/9.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_multiple_keys.1250448199 |
Short name | T483 |
Test name | |
Test status | |
Simulation time | 18252932696 ps |
CPU time | 785.03 seconds |
Started | Jun 27 06:49:37 PM PDT 24 |
Finished | Jun 27 07:02:44 PM PDT 24 |
Peak memory | 378796 kb |
Host | smart-0118694f-b68a-477b-9d14-92fb49ad3bf1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250448199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip le_keys.1250448199 |
Directory | /workspace/9.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_partial_access.780509116 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 2191397964 ps |
CPU time | 72.43 seconds |
Started | Jun 27 06:49:44 PM PDT 24 |
Finished | Jun 27 06:51:01 PM PDT 24 |
Peak memory | 318028 kb |
Host | smart-fd31b636-a124-4a89-ae09-68d076511fb9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780509116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sr am_ctrl_partial_access.780509116 |
Directory | /workspace/9.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.119837547 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 8197188429 ps |
CPU time | 233.57 seconds |
Started | Jun 27 06:49:44 PM PDT 24 |
Finished | Jun 27 06:53:43 PM PDT 24 |
Peak memory | 202768 kb |
Host | smart-f684001f-8b27-48f6-90da-6cd8a9dad24d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119837547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 9.sram_ctrl_partial_access_b2b.119837547 |
Directory | /workspace/9.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_ram_cfg.3338939862 |
Short name | T571 |
Test name | |
Test status | |
Simulation time | 351260045 ps |
CPU time | 3.36 seconds |
Started | Jun 27 06:49:44 PM PDT 24 |
Finished | Jun 27 06:49:52 PM PDT 24 |
Peak memory | 202600 kb |
Host | smart-d890d919-b4c1-4917-a647-6b8e555de695 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338939862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.3338939862 |
Directory | /workspace/9.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_regwen.245539400 |
Short name | T625 |
Test name | |
Test status | |
Simulation time | 17266115844 ps |
CPU time | 853.66 seconds |
Started | Jun 27 06:49:40 PM PDT 24 |
Finished | Jun 27 07:03:58 PM PDT 24 |
Peak memory | 375516 kb |
Host | smart-8442a53a-228b-4e87-a71c-379fe44c2c07 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245539400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.245539400 |
Directory | /workspace/9.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_smoke.3731676283 |
Short name | T749 |
Test name | |
Test status | |
Simulation time | 642937987 ps |
CPU time | 24.87 seconds |
Started | Jun 27 06:49:43 PM PDT 24 |
Finished | Jun 27 06:50:12 PM PDT 24 |
Peak memory | 267092 kb |
Host | smart-6a728acb-0e70-476a-8370-be0cba793954 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731676283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.3731676283 |
Directory | /workspace/9.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.6165526 |
Short name | T899 |
Test name | |
Test status | |
Simulation time | 1568743812 ps |
CPU time | 36.54 seconds |
Started | Jun 27 06:49:47 PM PDT 24 |
Finished | Jun 27 06:50:28 PM PDT 24 |
Peak memory | 211140 kb |
Host | smart-d7be69ec-f6dc-4038-90b9-c0e00d9d016e |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=6165526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.6165526 |
Directory | /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_pipeline.2808210964 |
Short name | T602 |
Test name | |
Test status | |
Simulation time | 10309263968 ps |
CPU time | 346.02 seconds |
Started | Jun 27 06:49:39 PM PDT 24 |
Finished | Jun 27 06:55:28 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-abb11e0a-ea41-485c-bd5c-cd6bec1d177a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808210964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_stress_pipeline.2808210964 |
Directory | /workspace/9.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2875307474 |
Short name | T898 |
Test name | |
Test status | |
Simulation time | 805679422 ps |
CPU time | 8.13 seconds |
Started | Jun 27 06:49:41 PM PDT 24 |
Finished | Jun 27 06:49:54 PM PDT 24 |
Peak memory | 219092 kb |
Host | smart-b0f90417-4733-498b-97c7-085c17792250 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875307474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.2875307474 |
Directory | /workspace/9.sram_ctrl_throughput_w_partial_write/latest |
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