Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16274379

1

T1

62092

T2

28180

T3

57856

full_word

151744695

1

T1

3241

T2

1569

T3

3024

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	168018744	1			T1	65333		T2	29749		T3	60880
auto[TlIntgErrCmd]	110	1			T55	6		T56	6		T57	4
auto[TlIntgErrData]	110	1			T55	1		T56	1		T57	9
auto[TlIntgErrBoth]	110	1			T55	3		T56	3		T57	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

80771901

1

T1

32342

T2

14873

T3

30177

auto[1]

87247173

1

T1

32991

T2

14876

T3

30703

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7945181	1			T1	32068		T2	14731		T3	29918
auto[TlIntgErrNone]	partial	auto[1]	8328896	1			T1	30024		T2	13449		T3	27938
auto[TlIntgErrNone]	full_word	auto[0]	72826571	1			T1	274		T2	142		T3	259
auto[TlIntgErrNone]	full_word	auto[1]	78918096	1			T1	2967		T2	1427		T3	2765
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T55	1		T56	4		T57	3
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T55	5		T56	2		T57	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T115	1		T118	1		T123	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T119	1		T124	1		T125	1
auto[TlIntgErrData]	partial	auto[0]	49	1			T57	4		T115	1		T120	2
auto[TlIntgErrData]	partial	auto[1]	46	1			T55	1		T56	1		T57	4
auto[TlIntgErrData]	full_word	auto[0]	8	1			T117	2		T126	1		T121	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T57	1		T127	1		T128	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T55	1		T56	3		T57	2
auto[TlIntgErrBoth]	partial	auto[1]	63	1			T55	2		T57	5		T115	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T118	1		T125	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T115	1		T120	1		T117	1