Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	924725	1			T1	1810		T5	4333		T6	35
auto[1]	11251247	1			T1	5166		T4	119617		T5	12096
auto[2]	714223	1			T1	1174		T5	3189		T6	37
auto[3]	10937360	1			T1	4670		T4	120479		T5	10961

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14999556	1			T1	8		T4	7611		T5	535
auto[1]	2242559	1			T1	156		T4	35860		T5	3160
auto[2]	2280332	1			T1	707		T4	35194		T5	4213
auto[3]	4305108	1			T1	11949		T4	161431		T5	22671

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10145264

1

T1

12819

T4

48

T11

2927

auto[1]

13682291

1

T1

1

T4

240048

T5

30579

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	436382	1			T6	28		T24	14		T8	47
auto[0]	auto[0]	auto[1]	44864	1			T1	12		T6	4		T8	6
auto[0]	auto[0]	auto[2]	44980	1			T1	15		T6	3		T24	2
auto[0]	auto[0]	auto[3]	54554	1			T1	1782		T98	1		T83	1800
auto[0]	auto[1]	auto[0]	3530223	1			T1	2		T11	1485		T13	402
auto[0]	auto[1]	auto[1]	377138	1			T1	41		T4	2		T13	32
auto[0]	auto[1]	auto[2]	386467	1			T1	267		T4	2		T13	36
auto[0]	auto[1]	auto[3]	384128	1			T1	4856		T4	22		T13	2
auto[0]	auto[2]	auto[0]	335993	1			T6	29		T63	2		T137	2585
auto[0]	auto[2]	auto[1]	36519	1			T6	6		T98	1		T63	1
auto[0]	auto[2]	auto[2]	37012	1			T1	11		T6	2		T24	21
auto[0]	auto[2]	auto[3]	39101	1			T1	1163		T24	1		T8	2
auto[0]	auto[3]	auto[0]	3338661	1			T1	6		T11	1442		T13	407
auto[0]	auto[3]	auto[1]	364181	1			T1	103		T4	2		T13	42
auto[0]	auto[3]	auto[2]	385100	1			T1	414		T4	2		T13	34
auto[0]	auto[3]	auto[3]	349961	1			T1	4147		T4	18		T13	2
auto[1]	auto[0]	auto[0]	11403	1			T5	143		T98	1187		T137	1
auto[1]	auto[0]	auto[1]	50621	1			T5	649		T98	5343		T101	1293
auto[1]	auto[0]	auto[2]	51047	1			T5	660		T98	5500		T101	1327
auto[1]	auto[0]	auto[3]	230874	1			T1	1		T5	2881		T98	24621
auto[1]	auto[1]	auto[0]	3671648	1			T4	3853		T5	274		T54	1
auto[1]	auto[1]	auto[1]	681141	1			T4	17899		T5	1993		T96	14725
auto[1]	auto[1]	auto[2]	664063	1			T4	17245		T5	1129		T96	14584
auto[1]	auto[1]	auto[3]	1556439	1			T4	80594		T5	8700		T96	65924
auto[1]	auto[2]	auto[0]	8286	1			T98	1179		T101	155		T138	318
auto[1]	auto[2]	auto[1]	37119	1			T98	5071		T101	802		T138	1463
auto[1]	auto[2]	auto[2]	39953	1			T5	577		T98	3716		T101	1243
auto[1]	auto[2]	auto[3]	180240	1			T5	2612		T98	16553		T84	1
auto[1]	auto[3]	auto[0]	3666960	1			T4	3758		T5	118		T40	2
auto[1]	auto[3]	auto[1]	650976	1			T4	17957		T5	518		T96	14567
auto[1]	auto[3]	auto[2]	671710	1			T4	17945		T5	1847		T96	14584
auto[1]	auto[3]	auto[3]	1509811	1			T4	80797		T5	8478		T96	65250