Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1170767170	269973	0	0
ctrl_regwen_rd_A	1170767170	5504	0	0
exec_rd_A	1170767170	4803	0	0
exec_regwen_rd_A	1170767170	5269	0	0
readback_rd_A	1170767170	3655	0	0
readback_regwen_rd_A	1170767170	3152	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1170767170	269973	0	0
T6	134884	0	0	0
T13	286933	14756	0	0
T14	581	0	0	0
T20	291835	0	0	0
T21	0	9191	0	0
T23	261099	11338	0	0
T24	109042	0	0	0
T25	34158	0	0	0
T39	80555	0	0	0
T40	107387	0	0	0
T44	0	5616	0	0
T48	0	3648	0	0
T50	0	8588	0	0
T65	876379	0	0	0
T66	0	1379	0	0
T67	0	1352	0	0
T68	0	1550	0	0
T69	0	5975	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1170767170	5504	0	0
T17	21254	0	0	0
T29	95493	0	0	0
T30	69581	0	0	0
T44	0	422	0	0
T45	0	452	0	0
T48	0	272	0	0
T67	33806	95	0	0
T103	0	96	0	0
T104	0	381	0	0
T105	0	262	0	0
T106	0	250	0	0
T107	0	138	0	0
T108	0	295	0	0
T109	72605	0	0	0
T110	369839	0	0	0
T111	33606	0	0	0
T112	100292	0	0	0
T113	120134	0	0	0
T114	320787	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1170767170	4803	0	0
T17	21254	0	0	0
T29	95493	0	0	0
T30	69581	0	0	0
T44	0	293	0	0
T45	0	378	0	0
T48	0	155	0	0
T67	33806	82	0	0
T103	0	88	0	0
T104	0	348	0	0
T105	0	235	0	0
T106	0	220	0	0
T107	0	143	0	0
T108	0	282	0	0
T109	72605	0	0	0
T110	369839	0	0	0
T111	33606	0	0	0
T112	100292	0	0	0
T113	120134	0	0	0
T114	320787	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1170767170	5269	0	0
T17	21254	0	0	0
T29	95493	0	0	0
T30	69581	0	0	0
T44	0	411	0	0
T45	0	350	0	0
T48	0	182	0	0
T67	33806	93	0	0
T103	0	133	0	0
T104	0	390	0	0
T105	0	247	0	0
T106	0	271	0	0
T107	0	177	0	0
T108	0	297	0	0
T109	72605	0	0	0
T110	369839	0	0	0
T111	33606	0	0	0
T112	100292	0	0	0
T113	120134	0	0	0
T114	320787	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1170767170	3655	0	0
T17	21254	0	0	0
T29	95493	0	0	0
T30	69581	0	0	0
T44	0	428	0	0
T45	0	384	0	0
T48	0	257	0	0
T67	33806	72	0	0
T103	0	60	0	0
T104	0	281	0	0
T105	0	312	0	0
T106	0	213	0	0
T107	0	126	0	0
T108	0	293	0	0
T109	72605	0	0	0
T110	369839	0	0	0
T111	33606	0	0	0
T112	100292	0	0	0
T113	120134	0	0	0
T114	320787	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1170767170	3152	0	0
T17	21254	0	0	0
T29	95493	0	0	0
T30	69581	0	0	0
T44	0	365	0	0
T45	0	269	0	0
T48	0	190	0	0
T67	33806	87	0	0
T103	0	98	0	0
T104	0	291	0	0
T105	0	150	0	0
T106	0	192	0	0
T107	0	73	0	0
T108	0	253	0	0
T109	72605	0	0	0
T110	369839	0	0	0
T111	33606	0	0	0
T112	100292	0	0	0
T113	120134	0	0	0
T114	320787	0	0	0