Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16790147	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

164720770

1

T1

94141

T2

22962

T3

136801

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	89398305	1			T1	52180		T2	12713		T3	74959
values[0x0]	44391768	1			T1	24868		T2	6081		T3	36148
values[0x1]	47720844	1			T1	26667		T2	6488		T3	39229

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8538929	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

172971988

1

T1

98920

T2

24121

T3

143620

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	663648	1			T1	384		T2	97		T3	571
valid_sources[0x01]	556198	1			T1	377		T2	99		T3	569
valid_sources[0x02]	574829	1			T1	502		T2	88		T3	597
valid_sources[0x03]	662261	1			T1	433		T2	81		T3	583
valid_sources[0x04]	1004250	1			T1	362		T2	95		T3	570
valid_sources[0x05]	1491756	1			T1	425		T2	79		T3	617
valid_sources[0x06]	605603	1			T1	390		T2	120		T3	585
valid_sources[0x07]	556981	1			T1	527		T2	103		T3	608
valid_sources[0x08]	589555	1			T1	550		T2	72		T3	554
valid_sources[0x09]	641642	1			T1	345		T2	104		T3	579
valid_sources[0x0a]	591701	1			T1	406		T2	87		T3	563
valid_sources[0x0b]	2103108	1			T1	462		T2	92		T3	571
valid_sources[0x0c]	685667	1			T1	453		T2	118		T3	625
valid_sources[0x0d]	584682	1			T1	479		T2	104		T3	600
valid_sources[0x0e]	587278	1			T1	479		T2	66		T3	619
valid_sources[0x0f]	563397	1			T1	412		T2	100		T3	576
valid_sources[0x10]	573025	1			T1	426		T2	112		T3	603
valid_sources[0x11]	561036	1			T1	398		T2	93		T3	582
valid_sources[0x12]	602531	1			T1	388		T2	105		T3	587
valid_sources[0x13]	560748	1			T1	377		T2	82		T3	582
valid_sources[0x14]	577322	1			T1	489		T2	82		T3	577
valid_sources[0x15]	616643	1			T1	428		T2	93		T3	607
valid_sources[0x16]	656450	1			T1	424		T2	83		T3	590
valid_sources[0x17]	656414	1			T1	337		T2	90		T3	653
valid_sources[0x18]	1591335	1			T1	394		T2	113		T3	574
valid_sources[0x19]	679418	1			T1	466		T2	149		T3	592
valid_sources[0x1a]	582242	1			T1	371		T2	85		T3	586
valid_sources[0x1b]	578950	1			T1	404		T2	87		T3	593
valid_sources[0x1c]	572929	1			T1	373		T2	79		T3	542
valid_sources[0x1d]	582028	1			T1	519		T2	132		T3	586
valid_sources[0x1e]	1308429	1			T1	356		T2	79		T3	644
valid_sources[0x1f]	589904	1			T1	467		T2	98		T3	610
valid_sources[0x20]	573922	1			T1	365		T2	70		T3	584
valid_sources[0x21]	593829	1			T1	360		T2	88		T3	582
valid_sources[0x22]	579699	1			T1	365		T2	82		T3	591
valid_sources[0x23]	625252	1			T1	321		T2	100		T3	558
valid_sources[0x24]	576589	1			T1	409		T2	103		T3	582
valid_sources[0x25]	588676	1			T1	385		T2	110		T3	557
valid_sources[0x26]	593764	1			T1	486		T2	75		T3	599
valid_sources[0x27]	582367	1			T1	422		T2	105		T3	607
valid_sources[0x28]	601167	1			T1	453		T2	101		T3	623
valid_sources[0x29]	628311	1			T1	383		T2	105		T3	559
valid_sources[0x2a]	605304	1			T1	326		T2	108		T3	558
valid_sources[0x2b]	610237	1			T1	372		T2	118		T3	592
valid_sources[0x2c]	602444	1			T1	402		T2	96		T3	632
valid_sources[0x2d]	565782	1			T1	408		T2	91		T3	583
valid_sources[0x2e]	634665	1			T1	399		T2	127		T3	658
valid_sources[0x2f]	575989	1			T1	366		T2	127		T3	577
valid_sources[0x30]	589989	1			T1	368		T2	115		T3	602
valid_sources[0x31]	621074	1			T1	281		T2	97		T3	608
valid_sources[0x32]	555216	1			T1	367		T2	67		T3	573
valid_sources[0x33]	632133	1			T1	398		T2	104		T3	578
valid_sources[0x34]	602933	1			T1	292		T2	95		T3	610
valid_sources[0x35]	609964	1			T1	548		T2	116		T3	593
valid_sources[0x36]	574008	1			T1	401		T2	75		T3	605
valid_sources[0x37]	580674	1			T1	443		T2	76		T3	572
valid_sources[0x38]	570579	1			T1	311		T2	87		T3	593
valid_sources[0x39]	599649	1			T1	382		T2	72		T3	601
valid_sources[0x3a]	575017	1			T1	319		T2	89		T3	565
valid_sources[0x3b]	580286	1			T1	371		T2	124		T3	559
valid_sources[0x3c]	590561	1			T1	369		T2	90		T3	590
valid_sources[0x3d]	609921	1			T1	386		T2	97		T3	552
valid_sources[0x3e]	1180068	1			T1	429		T2	93		T3	613
valid_sources[0x3f]	608932	1			T1	474		T2	98		T3	567
valid_sources[0x40]	581601	1			T1	403		T2	113		T3	565
valid_sources[0x41]	573395	1			T1	389		T2	91		T3	619
valid_sources[0x42]	593480	1			T1	358		T2	92		T3	550
valid_sources[0x43]	592282	1			T1	385		T2	111		T3	598
valid_sources[0x44]	592758	1			T1	394		T2	87		T3	581
valid_sources[0x45]	647437	1			T1	317		T2	59		T3	624
valid_sources[0x46]	588945	1			T1	420		T2	68		T3	586
valid_sources[0x47]	655216	1			T1	393		T2	76		T3	583
valid_sources[0x48]	565186	1			T1	369		T2	69		T3	591
valid_sources[0x49]	600802	1			T1	352		T2	110		T3	615
valid_sources[0x4a]	570095	1			T1	397		T2	125		T3	578
valid_sources[0x4b]	2139530	1			T1	399		T2	72		T3	655
valid_sources[0x4c]	2732455	1			T1	460		T2	95		T3	621
valid_sources[0x4d]	632414	1			T1	358		T2	84		T3	612
valid_sources[0x4e]	623362	1			T1	253		T2	63		T3	644
valid_sources[0x4f]	601504	1			T1	310		T2	66		T3	555
valid_sources[0x50]	887424	1			T1	377		T2	80		T3	622
valid_sources[0x51]	645658	1			T1	383		T2	116		T3	580
valid_sources[0x52]	598148	1			T1	369		T2	96		T3	593
valid_sources[0x53]	570279	1			T1	353		T2	72		T3	615
valid_sources[0x54]	570906	1			T1	287		T2	132		T3	550
valid_sources[0x55]	561650	1			T1	397		T2	123		T3	529
valid_sources[0x56]	568488	1			T1	449		T2	90		T3	572
valid_sources[0x57]	2086257	1			T1	372		T2	106		T3	620
valid_sources[0x58]	594083	1			T1	507		T2	108		T3	614
valid_sources[0x59]	1351338	1			T1	436		T2	104		T3	592
valid_sources[0x5a]	1214288	1			T1	424		T2	96		T3	602
valid_sources[0x5b]	602398	1			T1	390		T2	112		T3	623
valid_sources[0x5c]	570240	1			T1	452		T2	97		T3	609
valid_sources[0x5d]	1256133	1			T1	432		T2	78		T3	604
valid_sources[0x5e]	570125	1			T1	332		T2	113		T3	570
valid_sources[0x5f]	577549	1			T1	424		T2	64		T3	570
valid_sources[0x60]	571392	1			T1	390		T2	96		T3	556
valid_sources[0x61]	808804	1			T1	441		T2	113		T3	595
valid_sources[0x62]	597369	1			T1	348		T2	108		T3	588
valid_sources[0x63]	1441695	1			T1	306		T2	93		T3	578
valid_sources[0x64]	588714	1			T1	422		T2	98		T3	610
valid_sources[0x65]	598953	1			T1	337		T2	104		T3	580
valid_sources[0x66]	642500	1			T1	492		T2	125		T3	610
valid_sources[0x67]	565014	1			T1	317		T2	107		T3	546
valid_sources[0x68]	771260	1			T1	369		T2	94		T3	582
valid_sources[0x69]	589598	1			T1	413		T2	75		T3	598
valid_sources[0x6a]	574922	1			T1	431		T2	78		T3	567
valid_sources[0x6b]	621326	1			T1	459		T2	123		T3	550
valid_sources[0x6c]	603872	1			T1	386		T2	122		T3	606
valid_sources[0x6d]	586983	1			T1	381		T2	125		T3	594
valid_sources[0x6e]	602005	1			T1	394		T2	118		T3	582
valid_sources[0x6f]	561382	1			T1	489		T2	139		T3	597
valid_sources[0x70]	583403	1			T1	352		T2	115		T3	574
valid_sources[0x71]	571896	1			T1	465		T2	105		T3	575
valid_sources[0x72]	593102	1			T1	449		T2	82		T3	537
valid_sources[0x73]	2031901	1			T1	392		T2	118		T3	568
valid_sources[0x74]	617139	1			T1	429		T2	116		T3	562
valid_sources[0x75]	559688	1			T1	319		T2	101		T3	600
valid_sources[0x76]	579161	1			T1	493		T2	108		T3	589
valid_sources[0x77]	553206	1			T1	409		T2	85		T3	540
valid_sources[0x78]	579019	1			T1	429		T2	103		T3	577
valid_sources[0x79]	587346	1			T1	467		T2	71		T3	605
valid_sources[0x7a]	578530	1			T1	459		T2	84		T3	602
valid_sources[0x7b]	1297733	1			T1	488		T2	90		T3	514
valid_sources[0x7c]	596340	1			T1	359		T2	106		T3	589
valid_sources[0x7d]	592831	1			T1	537		T2	82		T3	577
valid_sources[0x7e]	637623	1			T1	350		T2	102		T3	597
valid_sources[0x7f]	796649	1			T1	353		T2	143		T3	618
valid_sources[0x80]	2019947	1			T1	360		T2	113		T3	587

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

80955410

1

T1

47412

T2

11587

T3

68169

values[0x0]

all_enables

biggest_size

41888091

1

T1

23402

T2

5740

T3

34073

values[0x1]

all_enables

biggest_size

41877269

1

T1

23327

T2

5635

T3

34559

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44819	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

146906

1

T1

18

T2

1

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	52276	1			T1	11		T4	31		T5	13
values[0x0]	67470	1			T1	21		T3	10		T7	4
values[0x1]	71979	1			T1	22		T2	2		T3	17

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35010	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

156715

1

T1

19

T2

1

T3

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	728	1			T43	3		T22	25		T55	1
valid_sources[0x01]	740	1			T43	2		T71	1		T22	14
valid_sources[0x02]	614	1			T43	1		T22	17		T81	1
valid_sources[0x03]	1027	1			T5	1		T71	1		T22	17
valid_sources[0x04]	593	1			T5	2		T22	24		T37	1
valid_sources[0x05]	757	1			T22	14		T66	1		T19	4
valid_sources[0x06]	602	1			T22	15		T78	1		T20	1
valid_sources[0x07]	592	1			T22	24		T98	1		T15	1
valid_sources[0x08]	918	1			T43	2		T22	23		T66	5
valid_sources[0x09]	749	1			T43	1		T22	24		T66	1
valid_sources[0x0a]	840	1			T5	1		T22	23		T66	4
valid_sources[0x0b]	947	1			T4	2		T22	24		T80	1
valid_sources[0x0c]	829	1			T43	2		T71	1		T22	19
valid_sources[0x0d]	860	1			T5	1		T43	1		T22	22
valid_sources[0x0e]	538	1			T5	1		T22	25		T66	3
valid_sources[0x0f]	710	1			T71	1		T14	1		T22	16
valid_sources[0x10]	895	1			T5	1		T43	2		T21	70
valid_sources[0x11]	709	1			T6	3		T24	1		T43	1
valid_sources[0x12]	900	1			T41	1		T22	18		T37	1
valid_sources[0x13]	699	1			T43	2		T22	28		T15	1
valid_sources[0x14]	963	1			T1	54		T4	1		T9	1
valid_sources[0x15]	717	1			T4	1		T5	1		T22	17
valid_sources[0x16]	608	1			T39	1		T22	17		T77	1
valid_sources[0x17]	604	1			T4	1		T43	3		T41	1
valid_sources[0x18]	754	1			T4	1		T43	1		T71	1
valid_sources[0x19]	670	1			T4	1		T6	2		T43	1
valid_sources[0x1a]	568	1			T43	1		T22	12		T55	3
valid_sources[0x1b]	697	1			T43	1		T22	43		T23	5
valid_sources[0x1c]	1102	1			T24	2		T22	28		T78	1
valid_sources[0x1d]	653	1			T43	2		T22	24		T55	1
valid_sources[0x1e]	588	1			T6	1		T43	1		T22	17
valid_sources[0x1f]	962	1			T43	2		T22	18		T78	1
valid_sources[0x20]	555	1			T5	1		T43	2		T22	21
valid_sources[0x21]	500	1			T5	2		T43	3		T22	18
valid_sources[0x22]	577	1			T62	6		T71	2		T22	22
valid_sources[0x23]	732	1			T5	1		T43	1		T22	30
valid_sources[0x24]	679	1			T22	16		T36	1		T52	1
valid_sources[0x25]	813	1			T43	1		T22	12		T81	1
valid_sources[0x26]	587	1			T9	1		T39	2		T22	18
valid_sources[0x27]	772	1			T43	2		T22	25		T55	5
valid_sources[0x28]	916	1			T5	1		T22	32		T55	1
valid_sources[0x29]	602	1			T43	1		T22	20		T19	2
valid_sources[0x2a]	734	1			T43	1		T71	1		T22	30
valid_sources[0x2b]	616	1			T6	3		T24	1		T43	2
valid_sources[0x2c]	594	1			T14	1		T21	3		T22	19
valid_sources[0x2d]	481	1			T43	2		T22	21		T55	1
valid_sources[0x2e]	878	1			T5	1		T22	14		T55	1
valid_sources[0x2f]	618	1			T6	2		T43	2		T22	22
valid_sources[0x30]	1078	1			T22	24		T55	2		T66	1
valid_sources[0x31]	537	1			T4	3		T11	9		T43	1
valid_sources[0x32]	907	1			T4	1		T43	2		T22	11
valid_sources[0x33]	1078	1			T43	5		T22	20		T96	1
valid_sources[0x34]	900	1			T2	2		T43	1		T22	24
valid_sources[0x35]	566	1			T43	1		T41	2		T22	18
valid_sources[0x36]	733	1			T6	1		T43	1		T22	16
valid_sources[0x37]	634	1			T5	1		T62	7		T22	23
valid_sources[0x38]	710	1			T3	27		T43	1		T22	18
valid_sources[0x39]	940	1			T5	1		T43	1		T12	13
valid_sources[0x3a]	705	1			T4	2		T5	2		T43	1
valid_sources[0x3b]	677	1			T43	2		T22	22		T18	1
valid_sources[0x3c]	511	1			T41	2		T22	16		T66	2
valid_sources[0x3d]	818	1			T56	1		T43	1		T22	23
valid_sources[0x3e]	1432	1			T5	1		T43	3		T21	307
valid_sources[0x3f]	695	1			T4	3		T24	1		T22	23
valid_sources[0x40]	662	1			T5	1		T43	1		T22	29
valid_sources[0x41]	894	1			T22	20		T55	1		T20	2
valid_sources[0x42]	694	1			T43	3		T22	31		T132	3
valid_sources[0x43]	926	1			T21	106		T22	20		T55	1
valid_sources[0x44]	804	1			T6	1		T43	1		T22	15
valid_sources[0x45]	927	1			T5	1		T43	1		T41	1
valid_sources[0x46]	730	1			T43	2		T152	2		T22	22
valid_sources[0x47]	651	1			T5	1		T22	21		T55	1
valid_sources[0x48]	668	1			T22	21		T42	38		T55	1
valid_sources[0x49]	953	1			T4	1		T43	2		T22	17
valid_sources[0x4a]	857	1			T22	22		T31	1		T23	2
valid_sources[0x4b]	511	1			T5	1		T22	25		T20	1
valid_sources[0x4c]	846	1			T6	1		T43	2		T22	22
valid_sources[0x4d]	692	1			T68	14		T22	22		T66	1
valid_sources[0x4e]	751	1			T7	1		T39	1		T21	255
valid_sources[0x4f]	858	1			T4	2		T43	2		T22	21
valid_sources[0x50]	738	1			T5	1		T6	1		T22	27
valid_sources[0x51]	598	1			T43	1		T22	24		T19	2
valid_sources[0x52]	725	1			T4	1		T5	2		T41	2
valid_sources[0x53]	735	1			T43	1		T22	22		T55	2
valid_sources[0x54]	543	1			T24	3		T22	22		T55	3
valid_sources[0x55]	734	1			T56	1		T43	4		T22	19
valid_sources[0x56]	813	1			T43	2		T22	34		T55	1
valid_sources[0x57]	629	1			T43	1		T22	12		T81	1
valid_sources[0x58]	929	1			T43	3		T153	1		T21	339
valid_sources[0x59]	979	1			T43	2		T22	27		T66	3
valid_sources[0x5a]	726	1			T7	1		T43	1		T22	20
valid_sources[0x5b]	630	1			T62	2		T22	22		T66	1
valid_sources[0x5c]	761	1			T4	2		T5	1		T24	4
valid_sources[0x5d]	717	1			T22	18		T66	2		T19	2
valid_sources[0x5e]	600	1			T10	2		T22	24		T23	2
valid_sources[0x5f]	932	1			T5	1		T43	1		T21	93
valid_sources[0x60]	509	1			T43	1		T22	10		T16	1
valid_sources[0x61]	765	1			T5	3		T43	1		T21	21
valid_sources[0x62]	752	1			T10	1		T43	1		T22	23
valid_sources[0x63]	1030	1			T43	1		T26	1		T22	16
valid_sources[0x64]	577	1			T71	1		T22	26		T37	1
valid_sources[0x65]	701	1			T4	2		T43	3		T22	24
valid_sources[0x66]	548	1			T4	2		T43	2		T22	20
valid_sources[0x67]	655	1			T7	1		T43	3		T22	13
valid_sources[0x68]	617	1			T24	1		T43	1		T21	2
valid_sources[0x69]	942	1			T4	1		T5	2		T43	1
valid_sources[0x6a]	920	1			T13	2		T22	18		T55	3
valid_sources[0x6b]	859	1			T6	1		T43	1		T22	25
valid_sources[0x6c]	632	1			T43	1		T22	17		T19	1
valid_sources[0x6d]	527	1			T5	1		T11	2		T43	2
valid_sources[0x6e]	837	1			T21	3		T22	26		T23	11
valid_sources[0x6f]	540	1			T71	1		T21	1		T22	26
valid_sources[0x70]	707	1			T43	2		T22	18		T66	3
valid_sources[0x71]	599	1			T4	2		T43	3		T22	20
valid_sources[0x72]	1045	1			T43	1		T22	23		T78	1
valid_sources[0x73]	588	1			T43	1		T22	25		T78	1
valid_sources[0x74]	643	1			T4	1		T6	1		T71	2
valid_sources[0x75]	636	1			T4	2		T22	13		T15	2
valid_sources[0x76]	521	1			T43	1		T22	19		T52	1
valid_sources[0x77]	948	1			T24	1		T22	23		T55	1
valid_sources[0x78]	496	1			T5	1		T43	2		T40	2
valid_sources[0x79]	1588	1			T43	1		T57	2		T21	662
valid_sources[0x7a]	878	1			T24	1		T22	16		T66	1
valid_sources[0x7b]	927	1			T5	1		T10	1		T24	1
valid_sources[0x7c]	662	1			T4	1		T5	1		T71	1
valid_sources[0x7d]	570	1			T43	1		T22	19		T66	1
valid_sources[0x7e]	606	1			T43	1		T22	22		T18	1
valid_sources[0x7f]	954	1			T5	1		T43	1		T22	13
valid_sources[0x80]	870	1			T5	2		T43	1		T22	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

39792

1

T1

5

T4

17

T5

8

values[0x0]

all_enables

biggest_size

55064

1

T1

7

T3

4

T7

1

values[0x1]

all_enables

biggest_size

52050

1

T1

6

T2

1

T3

4