Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16666937

1

T1

8686

T2

2320

T3

13535

full_word

161452229

1

T1

84834

T2

22962

T3

136801

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	178118906	1			T1	93520		T2	25282		T3	150336
auto[TlIntgErrCmd]	86	1			T63	5		T64	5		T65	2
auto[TlIntgErrData]	87	1			T63	2		T64	5		T65	7
auto[TlIntgErrBoth]	87	1			T63	3		T65	1		T134	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

85938288

1

T1

41985

T2

12713

T3

74959

auto[1]

92180878

1

T1

51535

T2

12569

T3

75377

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8165421	1			T1	3880		T2	1126		T3	6790
auto[TlIntgErrNone]	partial	auto[1]	8501285	1			T1	4806		T2	1194		T3	6745
auto[TlIntgErrNone]	full_word	auto[0]	77772747	1			T1	38105		T2	11587		T3	68169
auto[TlIntgErrNone]	full_word	auto[1]	83679453	1			T1	46729		T2	11375		T3	68632
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T63	2		T64	3		T65	1
auto[TlIntgErrCmd]	partial	auto[1]	44	1			T63	2		T64	2		T65	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T63	1		T134	1		T141	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T142	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	31	1			T63	1		T64	3		T65	1
auto[TlIntgErrData]	partial	auto[1]	42	1			T63	1		T64	1		T65	5
auto[TlIntgErrData]	full_word	auto[0]	9	1			T133	1		T135	1		T137	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T64	1		T65	1		T135	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T63	2		T65	1		T134	1
auto[TlIntgErrBoth]	partial	auto[1]	44	1			T134	2		T133	5		T135	3
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T63	1		T135	1		T137	2
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T137	1		T142	1		T143	1