Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	652572	1			T1	40		T4	18		T10	181
auto[1]	11606022	1			T1	336		T2	6648		T3	29671
auto[2]	481547	1			T1	30		T4	29		T10	97
auto[3]	11348347	1			T1	225		T2	6570		T3	29864

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14731804	1			T1	459		T2	10973		T3	49803
auto[1]	2300503	1			T1	56		T2	1061		T3	4567
auto[2]	2344603	1			T1	105		T2	1082		T3	4729
auto[3]	4711578	1			T1	11		T2	102		T3	436

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9646891

1

T1

631

T2

13218

T3

59533

auto[1]

14441597

1

T3

2

T5

1

T11

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	241164	1			T1	31		T4	17		T10	151
auto[0]	auto[0]	auto[1]	25870	1			T1	6		T10	14		T11	465
auto[0]	auto[0]	auto[2]	25704	1			T1	3		T4	1		T10	14
auto[0]	auto[0]	auto[3]	70852	1			T10	2		T11	66		T24	1
auto[0]	auto[1]	auto[0]	3500656	1			T1	263		T2	5545		T3	24798
auto[0]	auto[1]	auto[1]	358739	1			T1	40		T2	492		T3	2125
auto[0]	auto[1]	auto[2]	382960	1			T1	30		T2	561		T3	2540
auto[0]	auto[1]	auto[3]	373837	1			T1	3		T2	50		T3	207
auto[0]	auto[2]	auto[0]	158598	1			T4	23		T11	4355		T40	44
auto[0]	auto[2]	auto[1]	21301	1			T4	2		T11	425		T40	181
auto[0]	auto[2]	auto[2]	21176	1			T1	26		T4	4		T10	88
auto[0]	auto[2]	auto[3]	49461	1			T1	4		T10	9		T11	35
auto[0]	auto[3]	auto[0]	3347590	1			T1	165		T2	5428		T3	25003
auto[0]	auto[3]	auto[1]	363152	1			T1	10		T2	569		T3	2442
auto[0]	auto[3]	auto[2]	370049	1			T1	46		T2	521		T3	2189
auto[0]	auto[3]	auto[3]	335782	1			T1	4		T2	52		T3	229
auto[1]	auto[0]	auto[0]	9537	1			T11	1		T36	466		T148	119
auto[1]	auto[0]	auto[1]	43079	1			T36	2065		T148	507		T149	3777
auto[1]	auto[0]	auto[2]	43002	1			T36	1985		T148	519		T149	3776
auto[1]	auto[0]	auto[3]	193364	1			T36	9044		T147	2		T148	2257
auto[1]	auto[1]	auto[0]	3733670	1			T3	1		T39	41403		T62	1
auto[1]	auto[1]	auto[1]	738519	1			T39	3872		T67	9462		T36	2038
auto[1]	auto[1]	auto[2]	735780	1			T39	4069		T67	10289		T66	1
auto[1]	auto[1]	auto[3]	1781861	1			T39	352		T40	1		T67	42448
auto[1]	auto[2]	auto[0]	6353	1			T36	387		T150	1		T149	762
auto[1]	auto[2]	auto[1]	28901	1			T36	1906		T149	3608		T151	2585
auto[1]	auto[2]	auto[2]	35468	1			T36	1314		T148	510		T149	3245
auto[1]	auto[2]	auto[3]	160289	1			T36	6212		T148	2018		T149	14460
auto[1]	auto[3]	auto[0]	3734236	1			T3	1		T5	1		T39	41318
auto[1]	auto[3]	auto[1]	720942	1			T39	4121		T67	10366		T98	1
auto[1]	auto[3]	auto[2]	730464	1			T39	3786		T62	1		T67	9354
auto[1]	auto[3]	auto[3]	1746132	1			T39	375		T67	42426		T36	6222