Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1149823490	214130	0	0
ctrl_regwen_rd_A	1149823490	4564	0	0
exec_rd_A	1149823490	4135	0	0
exec_regwen_rd_A	1149823490	4398	0	0
readback_rd_A	1149823490	2991	0	0
readback_regwen_rd_A	1149823490	2636	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149823490	214130	0	0
T18	133357	0	0	0
T21	111596	5033	0	0
T22	95649	6968	0	0
T23	0	1657	0	0
T42	169528	0	0	0
T44	691159	0	0	0
T45	0	4660	0	0
T50	0	7441	0	0
T72	0	981	0	0
T73	0	3661	0	0
T74	0	5966	0	0
T75	0	1078	0	0
T76	0	3890	0	0
T77	48698	0	0	0
T78	188341	0	0	0
T79	76038	0	0	0
T80	586279	0	0	0
T81	122970	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149823490	4564	0	0
T23	40527	159	0	0
T45	0	340	0	0
T47	0	578	0	0
T50	0	572	0	0
T75	0	71	0	0
T113	327936	0	0	0
T118	0	105	0	0
T119	0	222	0	0
T120	0	417	0	0
T121	0	457	0	0
T122	0	86	0	0
T123	215023	0	0	0
T124	85042	0	0	0
T125	53387	0	0	0
T126	154658	0	0	0
T127	165896	0	0	0
T128	576349	0	0	0
T129	161085	0	0	0
T130	149330	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149823490	4135	0	0
T23	40527	142	0	0
T45	0	377	0	0
T47	0	425	0	0
T50	0	548	0	0
T75	0	51	0	0
T113	327936	0	0	0
T118	0	48	0	0
T119	0	278	0	0
T120	0	378	0	0
T121	0	370	0	0
T122	0	67	0	0
T123	215023	0	0	0
T124	85042	0	0	0
T125	53387	0	0	0
T126	154658	0	0	0
T127	165896	0	0	0
T128	576349	0	0	0
T129	161085	0	0	0
T130	149330	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149823490	4398	0	0
T23	40527	157	0	0
T45	0	298	0	0
T47	0	437	0	0
T50	0	605	0	0
T75	0	56	0	0
T113	327936	0	0	0
T118	0	97	0	0
T119	0	207	0	0
T120	0	472	0	0
T121	0	485	0	0
T122	0	59	0	0
T123	215023	0	0	0
T124	85042	0	0	0
T125	53387	0	0	0
T126	154658	0	0	0
T127	165896	0	0	0
T128	576349	0	0	0
T129	161085	0	0	0
T130	149330	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149823490	2991	0	0
T23	40527	125	0	0
T45	0	327	0	0
T47	0	481	0	0
T50	0	601	0	0
T75	0	69	0	0
T113	327936	0	0	0
T118	0	73	0	0
T119	0	216	0	0
T120	0	337	0	0
T121	0	373	0	0
T122	0	32	0	0
T123	215023	0	0	0
T124	85042	0	0	0
T125	53387	0	0	0
T126	154658	0	0	0
T127	165896	0	0	0
T128	576349	0	0	0
T129	161085	0	0	0
T130	149330	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149823490	2636	0	0
T23	40527	172	0	0
T45	0	383	0	0
T47	0	398	0	0
T50	0	403	0	0
T75	0	35	0	0
T113	327936	0	0	0
T118	0	47	0	0
T119	0	171	0	0
T120	0	358	0	0
T121	0	278	0	0
T122	0	37	0	0
T123	215023	0	0	0
T124	85042	0	0	0
T125	53387	0	0	0
T126	154658	0	0	0
T127	165896	0	0	0
T128	576349	0	0	0
T129	161085	0	0	0
T130	149330	0	0	0