Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16804698	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

162829568

1

T1

655360

T2

2349

T3

1430

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	88438569	1			T1	327680		T2	555		T3	4082
values[0x0]	43919789	1			T1	164369		T2	904		T3	1401
values[0x1]	47275908	1			T1	163311		T2	890		T3	2655

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8546843	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

171087423

1

T1

655360

T2

2349

T3

4784

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	615589	1			T1	2496		T3	34		T6	6
valid_sources[0x01]	648748	1			T1	2599		T3	30		T4	14695
valid_sources[0x02]	623040	1			T1	2456		T3	36		T6	18
valid_sources[0x03]	1627761	1			T1	2542		T3	29		T6	4
valid_sources[0x04]	806055	1			T1	2561		T3	18		T9	8
valid_sources[0x05]	742469	1			T1	2498		T3	27		T6	3
valid_sources[0x06]	625878	1			T1	2585		T3	35		T6	2
valid_sources[0x07]	596705	1			T1	2599		T3	27		T6	17
valid_sources[0x08]	617666	1			T1	2488		T3	32		T6	10
valid_sources[0x09]	650688	1			T1	2441		T3	26		T6	12
valid_sources[0x0a]	604902	1			T1	2540		T3	44		T6	7
valid_sources[0x0b]	609676	1			T1	2545		T3	33		T4	3897
valid_sources[0x0c]	885147	1			T1	2620		T3	30		T6	19
valid_sources[0x0d]	602490	1			T1	2607		T3	36		T6	5
valid_sources[0x0e]	593627	1			T1	2525		T3	37		T6	21
valid_sources[0x0f]	574369	1			T1	2624		T3	44		T6	4
valid_sources[0x10]	572831	1			T1	2408		T2	481		T3	41
valid_sources[0x11]	609360	1			T1	2486		T3	28		T6	9
valid_sources[0x12]	603323	1			T1	2487		T3	31		T6	16
valid_sources[0x13]	592903	1			T1	2625		T3	30		T6	5
valid_sources[0x14]	616549	1			T1	2593		T3	26		T6	2
valid_sources[0x15]	644485	1			T1	2502		T3	32		T6	20
valid_sources[0x16]	601544	1			T1	2516		T3	24		T6	1
valid_sources[0x17]	2235463	1			T1	2607		T3	24		T6	18
valid_sources[0x18]	620091	1			T1	2541		T3	27		T6	6
valid_sources[0x19]	601174	1			T1	2670		T3	36		T6	22
valid_sources[0x1a]	593582	1			T1	2527		T3	41		T6	8
valid_sources[0x1b]	611048	1			T1	2448		T3	34		T6	7
valid_sources[0x1c]	1839898	1			T1	2526		T3	26		T6	7
valid_sources[0x1d]	2327549	1			T1	2512		T3	30		T6	6
valid_sources[0x1e]	593374	1			T1	2600		T3	33		T6	2
valid_sources[0x1f]	579738	1			T1	2507		T3	31		T4	19
valid_sources[0x20]	615156	1			T1	2552		T3	41		T6	26
valid_sources[0x21]	650073	1			T1	2548		T3	47		T6	17
valid_sources[0x22]	631302	1			T1	2638		T3	34		T6	12
valid_sources[0x23]	576292	1			T1	2593		T3	38		T6	12
valid_sources[0x24]	591647	1			T1	2523		T3	34		T6	26
valid_sources[0x25]	612821	1			T1	2521		T3	22		T6	5
valid_sources[0x26]	607064	1			T1	2554		T3	37		T6	13
valid_sources[0x27]	638747	1			T1	2493		T3	28		T6	11
valid_sources[0x28]	606021	1			T1	2605		T3	30		T6	19
valid_sources[0x29]	595107	1			T1	2488		T3	34		T6	19
valid_sources[0x2a]	600859	1			T1	2543		T3	37		T6	13
valid_sources[0x2b]	614433	1			T1	2422		T3	32		T6	2
valid_sources[0x2c]	805844	1			T1	2573		T3	38		T6	8
valid_sources[0x2d]	579007	1			T1	2591		T3	38		T6	10
valid_sources[0x2e]	576058	1			T1	2531		T3	26		T6	25
valid_sources[0x2f]	593890	1			T1	2516		T3	41		T6	20
valid_sources[0x30]	612225	1			T1	2655		T3	31		T6	14
valid_sources[0x31]	598512	1			T1	2557		T3	38		T6	23
valid_sources[0x32]	1139734	1			T1	2674		T3	26		T6	20
valid_sources[0x33]	609628	1			T1	2556		T3	26		T6	26
valid_sources[0x34]	651442	1			T1	2602		T3	36		T6	25
valid_sources[0x35]	584338	1			T1	2523		T3	26		T6	25
valid_sources[0x36]	598430	1			T1	2543		T3	28		T6	22
valid_sources[0x37]	597352	1			T1	2545		T3	28		T6	1
valid_sources[0x38]	646875	1			T1	2497		T3	23		T6	7
valid_sources[0x39]	661118	1			T1	2485		T3	31		T6	8
valid_sources[0x3a]	575271	1			T1	2546		T3	37		T6	29
valid_sources[0x3b]	614597	1			T1	2625		T3	27		T6	20
valid_sources[0x3c]	692504	1			T1	2598		T3	21		T6	17
valid_sources[0x3d]	600403	1			T1	2582		T3	29		T6	14
valid_sources[0x3e]	587234	1			T1	2579		T3	28		T4	6949
valid_sources[0x3f]	614920	1			T1	2559		T3	26		T6	9
valid_sources[0x40]	646232	1			T1	2571		T3	39		T6	20
valid_sources[0x41]	580903	1			T1	2478		T3	30		T6	6
valid_sources[0x42]	576955	1			T1	2564		T3	49		T9	10
valid_sources[0x43]	611914	1			T1	2433		T3	38		T6	8
valid_sources[0x44]	2660189	1			T1	2558		T3	32		T6	3
valid_sources[0x45]	645130	1			T1	2516		T3	31		T9	9
valid_sources[0x46]	813409	1			T1	2538		T3	21		T6	8
valid_sources[0x47]	669556	1			T1	2570		T3	26		T6	11
valid_sources[0x48]	1185227	1			T1	2533		T3	20		T6	9
valid_sources[0x49]	592830	1			T1	2672		T3	31		T6	5
valid_sources[0x4a]	589349	1			T1	2571		T3	40		T6	4
valid_sources[0x4b]	669913	1			T1	2585		T3	32		T6	9
valid_sources[0x4c]	638845	1			T1	2540		T3	36		T9	7
valid_sources[0x4d]	584111	1			T1	2520		T3	50		T6	35
valid_sources[0x4e]	601045	1			T1	2588		T3	33		T6	22
valid_sources[0x4f]	621320	1			T1	2639		T3	40		T6	8
valid_sources[0x50]	634281	1			T1	2629		T3	26		T6	7
valid_sources[0x51]	598182	1			T1	2548		T3	26		T6	2
valid_sources[0x52]	629710	1			T1	2610		T3	50		T6	6
valid_sources[0x53]	781722	1			T1	2535		T3	29		T6	1
valid_sources[0x54]	1070982	1			T1	2544		T3	34		T6	3
valid_sources[0x55]	594426	1			T1	2550		T3	32		T6	35
valid_sources[0x56]	724798	1			T1	2572		T3	29		T6	3
valid_sources[0x57]	588490	1			T1	2579		T3	29		T6	10
valid_sources[0x58]	623481	1			T1	2536		T3	28		T6	13
valid_sources[0x59]	680612	1			T1	2594		T3	35		T6	23
valid_sources[0x5a]	627129	1			T1	2545		T3	37		T6	26
valid_sources[0x5b]	667344	1			T1	2504		T3	28		T6	36
valid_sources[0x5c]	652188	1			T1	2571		T3	20		T6	13
valid_sources[0x5d]	597911	1			T1	2615		T3	32		T9	11
valid_sources[0x5e]	603547	1			T1	2446		T3	30		T6	11
valid_sources[0x5f]	585763	1			T1	2517		T3	36		T6	9
valid_sources[0x60]	1939336	1			T1	2646		T3	24		T6	2
valid_sources[0x61]	654190	1			T1	2588		T3	25		T6	18
valid_sources[0x62]	579947	1			T1	2494		T3	29		T6	14
valid_sources[0x63]	588705	1			T1	2621		T3	31		T6	12
valid_sources[0x64]	642217	1			T1	2531		T3	29		T6	6
valid_sources[0x65]	615734	1			T1	2519		T3	32		T6	20
valid_sources[0x66]	711660	1			T1	2594		T3	38		T6	5
valid_sources[0x67]	594650	1			T1	2617		T3	27		T6	4
valid_sources[0x68]	586429	1			T1	2608		T3	34		T6	1
valid_sources[0x69]	579968	1			T1	2606		T3	31		T6	32
valid_sources[0x6a]	627752	1			T1	2589		T3	24		T6	2
valid_sources[0x6b]	582625	1			T1	2551		T3	39		T9	12
valid_sources[0x6c]	650182	1			T1	2538		T2	303		T3	24
valid_sources[0x6d]	703264	1			T1	2532		T2	315		T3	39
valid_sources[0x6e]	612660	1			T1	2569		T3	39		T6	26
valid_sources[0x6f]	1181979	1			T1	2526		T3	29		T6	1
valid_sources[0x70]	611088	1			T1	2597		T3	34		T6	8
valid_sources[0x71]	615060	1			T1	2591		T3	33		T6	12
valid_sources[0x72]	600451	1			T1	2540		T3	32		T6	20
valid_sources[0x73]	589091	1			T1	2588		T3	27		T6	8
valid_sources[0x74]	609076	1			T1	2682		T3	23		T4	18801
valid_sources[0x75]	610857	1			T1	2555		T3	33		T6	5
valid_sources[0x76]	576809	1			T1	2614		T3	36		T6	23
valid_sources[0x77]	1334790	1			T1	2534		T3	29		T6	14
valid_sources[0x78]	580149	1			T1	2605		T3	37		T6	5
valid_sources[0x79]	623819	1			T1	2475		T3	41		T6	5
valid_sources[0x7a]	610470	1			T1	2550		T3	39		T6	16
valid_sources[0x7b]	599139	1			T1	2516		T3	33		T6	15
valid_sources[0x7c]	818334	1			T1	2661		T3	36		T6	2
valid_sources[0x7d]	593305	1			T1	2603		T3	30		T6	7
valid_sources[0x7e]	625316	1			T1	2525		T3	34		T6	6
valid_sources[0x7f]	587306	1			T1	2535		T3	29		T6	10
valid_sources[0x80]	642412	1			T1	2506		T3	35		T6	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

79993248

1

T1

327680

T2

555

T3

712

values[0x0]

all_enables

biggest_size

41414064

1

T1

164369

T2

904

T3

371

values[0x1]

all_enables

biggest_size

41422256

1

T1

163311

T2

890

T3

347

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45889	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

156509

1

T1

3

T2

1907

T4

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	55541	1			T2	533		T4	6		T6	25
values[0x0]	70553	1			T1	5		T2	681		T4	11
values[0x1]	76304	1			T1	5		T2	751		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35503	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

166895

1

T1

3

T2

1924

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	655	1			T2	4		T43	4		T22	5
valid_sources[0x01]	850	1			T2	10		T22	8		T23	16
valid_sources[0x02]	706	1			T2	10		T22	6		T23	18
valid_sources[0x03]	1009	1			T2	6		T6	1		T22	10
valid_sources[0x04]	709	1			T2	12		T22	7		T23	12
valid_sources[0x05]	689	1			T2	6		T22	8		T23	21
valid_sources[0x06]	783	1			T2	6		T6	3		T39	1
valid_sources[0x07]	672	1			T2	9		T22	9		T23	9
valid_sources[0x08]	740	1			T2	8		T22	4		T23	6
valid_sources[0x09]	701	1			T2	4		T22	8		T23	15
valid_sources[0x0a]	792	1			T2	5		T22	6		T23	6
valid_sources[0x0b]	764	1			T2	7		T22	5		T23	11
valid_sources[0x0c]	662	1			T2	8		T22	5		T23	6
valid_sources[0x0d]	715	1			T2	5		T42	1		T22	10
valid_sources[0x0e]	705	1			T2	7		T22	10		T23	10
valid_sources[0x0f]	752	1			T2	6		T22	7		T23	11
valid_sources[0x10]	743	1			T2	2		T22	8		T23	16
valid_sources[0x11]	749	1			T2	10		T22	9		T23	11
valid_sources[0x12]	783	1			T2	6		T22	7		T23	12
valid_sources[0x13]	756	1			T2	10		T22	9		T23	21
valid_sources[0x14]	910	1			T2	8		T22	8		T23	22
valid_sources[0x15]	738	1			T2	4		T22	14		T23	12
valid_sources[0x16]	706	1			T2	9		T6	3		T22	9
valid_sources[0x17]	623	1			T2	6		T22	5		T23	23
valid_sources[0x18]	699	1			T2	5		T22	4		T23	7
valid_sources[0x19]	648	1			T2	6		T22	4		T23	13
valid_sources[0x1a]	706	1			T2	10		T22	11		T23	6
valid_sources[0x1b]	740	1			T2	10		T22	5		T23	20
valid_sources[0x1c]	574	1			T2	3		T22	9		T23	15
valid_sources[0x1d]	838	1			T2	11		T22	8		T23	15
valid_sources[0x1e]	1046	1			T1	1		T2	8		T22	9
valid_sources[0x1f]	784	1			T2	7		T22	12		T23	12
valid_sources[0x20]	759	1			T2	9		T22	1		T23	13
valid_sources[0x21]	792	1			T2	11		T22	4		T23	13
valid_sources[0x22]	774	1			T2	13		T22	6		T23	11
valid_sources[0x23]	748	1			T2	5		T22	10		T23	10
valid_sources[0x24]	670	1			T2	12		T6	2		T9	1
valid_sources[0x25]	762	1			T2	5		T5	1		T22	5
valid_sources[0x26]	706	1			T2	13		T22	8		T23	11
valid_sources[0x27]	824	1			T2	8		T48	22		T22	7
valid_sources[0x28]	731	1			T2	7		T42	1		T22	3
valid_sources[0x29]	764	1			T2	7		T22	3		T23	7
valid_sources[0x2a]	691	1			T2	8		T22	6		T23	8
valid_sources[0x2b]	1269	1			T2	3		T22	5		T23	14
valid_sources[0x2c]	654	1			T2	7		T22	7		T23	19
valid_sources[0x2d]	854	1			T2	3		T22	8		T23	15
valid_sources[0x2e]	815	1			T2	9		T22	3		T23	10
valid_sources[0x2f]	615	1			T2	7		T22	6		T23	26
valid_sources[0x30]	767	1			T2	8		T22	3		T23	20
valid_sources[0x31]	799	1			T2	8		T22	2		T23	13
valid_sources[0x32]	669	1			T2	12		T6	1		T43	3
valid_sources[0x33]	899	1			T2	5		T42	1		T22	12
valid_sources[0x34]	684	1			T2	8		T22	8		T23	23
valid_sources[0x35]	683	1			T2	10		T22	6		T23	11
valid_sources[0x36]	709	1			T2	10		T42	1		T22	18
valid_sources[0x37]	786	1			T2	10		T48	9		T22	5
valid_sources[0x38]	672	1			T2	9		T22	9		T23	12
valid_sources[0x39]	783	1			T2	4		T22	4		T23	12
valid_sources[0x3a]	1041	1			T2	11		T22	8		T23	18
valid_sources[0x3b]	686	1			T1	1		T2	8		T22	9
valid_sources[0x3c]	697	1			T2	7		T22	7		T23	16
valid_sources[0x3d]	718	1			T1	1		T2	9		T22	2
valid_sources[0x3e]	910	1			T2	6		T22	8		T23	18
valid_sources[0x3f]	674	1			T2	6		T22	7		T23	14
valid_sources[0x40]	1070	1			T2	8		T7	2		T22	15
valid_sources[0x41]	885	1			T2	5		T22	7		T23	14
valid_sources[0x42]	938	1			T2	4		T22	6		T23	25
valid_sources[0x43]	784	1			T2	9		T22	2		T23	4
valid_sources[0x44]	704	1			T2	14		T22	6		T23	19
valid_sources[0x45]	720	1			T2	4		T43	2		T22	5
valid_sources[0x46]	948	1			T2	7		T42	3		T22	13
valid_sources[0x47]	675	1			T2	13		T48	35		T22	8
valid_sources[0x48]	752	1			T2	6		T22	10		T23	8
valid_sources[0x49]	808	1			T2	7		T22	8		T23	12
valid_sources[0x4a]	622	1			T2	5		T22	2		T23	15
valid_sources[0x4b]	796	1			T2	7		T6	2		T22	8
valid_sources[0x4c]	761	1			T2	11		T22	9		T23	20
valid_sources[0x4d]	844	1			T2	9		T22	7		T23	18
valid_sources[0x4e]	610	1			T2	11		T22	10		T23	11
valid_sources[0x4f]	683	1			T2	10		T42	2		T22	7
valid_sources[0x50]	817	1			T2	11		T22	7		T23	7
valid_sources[0x51]	1026	1			T2	8		T22	6		T23	20
valid_sources[0x52]	1040	1			T1	1		T2	7		T22	10
valid_sources[0x53]	578	1			T2	11		T6	4		T22	8
valid_sources[0x54]	887	1			T2	2		T42	1		T22	12
valid_sources[0x55]	727	1			T2	7		T22	7		T23	14
valid_sources[0x56]	741	1			T2	4		T6	2		T22	8
valid_sources[0x57]	763	1			T2	6		T22	9		T23	13
valid_sources[0x58]	630	1			T2	6		T22	3		T23	15
valid_sources[0x59]	813	1			T2	1		T22	17		T23	9
valid_sources[0x5a]	1036	1			T2	5		T42	1		T22	14
valid_sources[0x5b]	822	1			T2	9		T22	6		T23	11
valid_sources[0x5c]	621	1			T2	5		T22	11		T23	11
valid_sources[0x5d]	709	1			T2	5		T48	6		T22	11
valid_sources[0x5e]	742	1			T2	10		T22	8		T23	12
valid_sources[0x5f]	580	1			T2	7		T22	6		T23	11
valid_sources[0x60]	899	1			T2	9		T22	9		T23	21
valid_sources[0x61]	1141	1			T2	5		T22	4		T23	19
valid_sources[0x62]	705	1			T2	9		T6	3		T22	5
valid_sources[0x63]	756	1			T2	9		T7	15		T22	7
valid_sources[0x64]	827	1			T2	13		T22	3		T23	13
valid_sources[0x65]	675	1			T2	11		T22	9		T23	14
valid_sources[0x66]	761	1			T2	6		T22	3		T23	13
valid_sources[0x67]	720	1			T2	7		T48	6		T22	5
valid_sources[0x68]	883	1			T2	10		T22	12		T23	10
valid_sources[0x69]	812	1			T2	7		T22	5		T23	22
valid_sources[0x6a]	781	1			T2	11		T22	2		T23	9
valid_sources[0x6b]	662	1			T2	7		T22	5		T23	12
valid_sources[0x6c]	704	1			T2	12		T22	5		T23	8
valid_sources[0x6d]	884	1			T2	8		T22	7		T23	14
valid_sources[0x6e]	669	1			T2	1		T22	9		T23	10
valid_sources[0x6f]	740	1			T1	1		T2	11		T22	1
valid_sources[0x70]	651	1			T2	4		T22	3		T23	13
valid_sources[0x71]	739	1			T2	8		T22	5		T23	20
valid_sources[0x72]	1028	1			T2	7		T22	18		T23	7
valid_sources[0x73]	947	1			T2	10		T22	6		T23	12
valid_sources[0x74]	933	1			T1	1		T2	10		T22	4
valid_sources[0x75]	710	1			T2	6		T6	2		T22	3
valid_sources[0x76]	1360	1			T2	11		T39	2		T22	8
valid_sources[0x77]	698	1			T2	8		T22	9		T23	7
valid_sources[0x78]	1269	1			T2	10		T22	13		T23	16
valid_sources[0x79]	601	1			T2	9		T22	3		T23	13
valid_sources[0x7a]	651	1			T2	9		T6	1		T22	8
valid_sources[0x7b]	1024	1			T2	12		T22	5		T23	5
valid_sources[0x7c]	1026	1			T2	9		T22	6		T23	19
valid_sources[0x7d]	757	1			T2	6		T22	16		T23	13
valid_sources[0x7e]	755	1			T2	8		T22	12		T23	12
valid_sources[0x7f]	689	1			T2	16		T22	7		T23	17
valid_sources[0x80]	817	1			T2	6		T22	7		T23	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

41908

1

T2

515

T4

2

T6

13

values[0x0]

all_enables

biggest_size

58392

1

T1

2

T2

679

T4

4

values[0x1]

all_enables

biggest_size

56209

1

T1

1

T2

713

T39

1