Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16678375

1

T2

1687

T3

6708

T4

3557

full_word

159483106

1

T1

655360

T2

2531

T3

1430

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	176161161	1			T1	655360		T2	4218		T3	8138
auto[TlIntgErrCmd]	106	1			T69	6		T70	11		T71	4
auto[TlIntgErrData]	106	1			T69	5		T70	5		T71	2
auto[TlIntgErrBoth]	108	1			T69	9		T70	4		T71	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

84884170

1

T1

327680

T2

945

T3

4082

auto[1]

91277311

1

T1

327680

T2

3273

T3

4056

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8160908	1			T2	343		T3	3370		T4	1460
auto[TlIntgErrNone]	partial	auto[1]	8517177	1			T2	1344		T3	3338		T4	2097
auto[TlIntgErrNone]	full_word	auto[0]	76723130	1			T1	327680		T2	602		T3	712
auto[TlIntgErrNone]	full_word	auto[1]	82759946	1			T1	327680		T2	1929		T3	718
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T69	1		T70	2		T71	2
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T69	5		T70	8		T71	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T70	1		T122	1		T124	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T123	1		T125	1		T126	1
auto[TlIntgErrData]	partial	auto[0]	35	1			T69	2		T70	3		T120	3
auto[TlIntgErrData]	partial	auto[1]	56	1			T69	3		T71	2		T120	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T70	2		T126	2		T127	1
auto[TlIntgErrData]	full_word	auto[1]	10	1			T119	1		T122	2		T123	1
auto[TlIntgErrBoth]	partial	auto[0]	54	1			T69	3		T70	2		T71	3
auto[TlIntgErrBoth]	partial	auto[1]	48	1			T69	4		T70	2		T71	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T124	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T69	2		T118	2		T123	1