Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	763193	1			T10	384		T42	384		T22	3
auto[1]	11422372	1			T4	1789		T6	365		T9	20
auto[2]	582115	1			T10	184		T42	187		T22	6
auto[3]	11136106	1			T4	1277		T6	370		T9	26

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14485115	1			T4	2547		T6	569		T9	42
auto[1]	2274066	1			T4	236		T6	84		T9	2
auto[2]	2325856	1			T4	259		T6	71		T9	2
auto[3]	4818749	1			T4	24		T6	11		T5	2557

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9179545

1

T4

3066

T6

735

T9

46

auto[1]

14724241

1

T12

4

T43

1

T45

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	279513	1			T10	301		T42	323		T22	1
auto[0]	auto[0]	auto[1]	29053	1			T10	42		T42	37		T40	288
auto[0]	auto[0]	auto[2]	29106	1			T10	37		T42	23		T22	2
auto[0]	auto[0]	auto[3]	62474	1			T10	4		T42	1		T40	29
auto[0]	auto[1]	auto[0]	3237773	1			T4	1494		T6	281		T9	20
auto[0]	auto[1]	auto[1]	336596	1			T4	124		T6	43		T5	291
auto[0]	auto[1]	auto[2]	358752	1			T4	156		T6	36		T5	272
auto[0]	auto[1]	auto[3]	415805	1			T4	15		T6	5		T5	1277
auto[0]	auto[2]	auto[0]	196945	1			T22	6		T40	991		T76	2153
auto[0]	auto[2]	auto[1]	23775	1			T40	92		T76	207		T89	216
auto[0]	auto[2]	auto[2]	25974	1			T10	169		T42	170		T40	149
auto[0]	auto[2]	auto[3]	46800	1			T10	15		T42	17		T40	15
auto[0]	auto[3]	auto[0]	3064486	1			T4	1053		T6	288		T9	22
auto[0]	auto[3]	auto[1]	337788	1			T4	112		T6	41		T9	2
auto[0]	auto[3]	auto[2]	354618	1			T4	103		T6	35		T9	2
auto[0]	auto[3]	auto[3]	380087	1			T4	9		T6	6		T5	1280
auto[1]	auto[0]	auto[0]	11888	1			T106	592		T134	1		T109	181
auto[1]	auto[0]	auto[1]	54347	1			T106	2867		T109	886		T135	3897
auto[1]	auto[0]	auto[2]	53625	1			T106	2757		T109	847		T135	3741
auto[1]	auto[0]	auto[3]	243187	1			T89	3		T106	12808		T98	7
auto[1]	auto[1]	auto[0]	3845157	1			T45	1		T62	1		T19	1
auto[1]	auto[1]	auto[1]	742427	1			T43	1		T68	10144		T104	7527
auto[1]	auto[1]	auto[2]	727267	1			T68	9982		T104	7563		T105	15897
auto[1]	auto[1]	auto[3]	1758595	1			T12	3		T68	989		T104	746
auto[1]	auto[2]	auto[0]	8844	1			T106	571		T116	2		T135	736
auto[1]	auto[2]	auto[1]	40058	1			T106	2668		T135	3444		T136	1578
auto[1]	auto[2]	auto[2]	43891	1			T106	1896		T109	750		T135	2587
auto[1]	auto[2]	auto[3]	195828	1			T106	8622		T109	3279		T135	11324
auto[1]	auto[3]	auto[0]	3840509	1			T61	1		T62	1		T24	1
auto[1]	auto[3]	auto[1]	710022	1			T68	10021		T104	7593		T105	15702
auto[1]	auto[3]	auto[2]	732623	1			T68	10015		T104	7483		T105	15627
auto[1]	auto[3]	auto[3]	1715973	1			T12	1		T68	1056		T104	774