Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1124863977	223572	0	0
ctrl_regwen_rd_A	1124863977	4176	0	0
exec_rd_A	1124863977	3779	0	0
exec_regwen_rd_A	1124863977	4151	0	0
readback_rd_A	1124863977	2647	0	0
readback_regwen_rd_A	1124863977	2397	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1124863977	223572	0	0
T2	24705	1754	0	0
T3	158052	0	0	0
T4	233765	0	0	0
T5	40418	0	0	0
T6	101653	0	0	0
T9	70511	0	0	0
T10	180189	0	0	0
T11	1316	0	0	0
T12	158447	0	0	0
T22	0	3037	0	0
T23	0	4569	0	0
T39	108225	0	0	0
T51	0	2340	0	0
T52	0	7830	0	0
T58	0	2822	0	0
T65	0	3726	0	0
T66	0	4690	0	0
T74	0	2010	0	0
T75	0	1036	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1124863977	4176	0	0
T8	108046	0	0	0
T19	830687	0	0	0
T22	96841	155	0	0
T23	102787	207	0	0
T24	184663	0	0	0
T49	137923	0	0	0
T51	0	120	0	0
T53	0	209	0	0
T61	401627	0	0	0
T62	946576	0	0	0
T63	134454	0	0	0
T66	0	322	0	0
T67	197885	0	0	0
T75	0	71	0	0
T112	0	88	0	0
T113	0	183	0	0
T114	0	96	0	0
T115	0	279	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1124863977	3779	0	0
T8	108046	0	0	0
T19	830687	0	0	0
T22	96841	119	0	0
T23	102787	152	0	0
T24	184663	0	0	0
T49	137923	0	0	0
T51	0	59	0	0
T53	0	167	0	0
T61	401627	0	0	0
T62	946576	0	0	0
T63	134454	0	0	0
T66	0	302	0	0
T67	197885	0	0	0
T75	0	49	0	0
T112	0	112	0	0
T113	0	218	0	0
T114	0	131	0	0
T115	0	159	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1124863977	4151	0	0
T8	108046	0	0	0
T19	830687	0	0	0
T22	96841	190	0	0
T23	102787	191	0	0
T24	184663	0	0	0
T49	137923	0	0	0
T51	0	109	0	0
T53	0	155	0	0
T61	401627	0	0	0
T62	946576	0	0	0
T63	134454	0	0	0
T66	0	325	0	0
T67	197885	0	0	0
T75	0	77	0	0
T112	0	171	0	0
T113	0	242	0	0
T114	0	80	0	0
T115	0	259	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1124863977	2647	0	0
T8	108046	0	0	0
T19	830687	0	0	0
T22	96841	135	0	0
T23	102787	139	0	0
T24	184663	0	0	0
T49	137923	0	0	0
T51	0	81	0	0
T53	0	161	0	0
T61	401627	0	0	0
T62	946576	0	0	0
T63	134454	0	0	0
T66	0	333	0	0
T67	197885	0	0	0
T75	0	74	0	0
T112	0	113	0	0
T113	0	183	0	0
T114	0	99	0	0
T115	0	195	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1124863977	2397	0	0
T8	108046	0	0	0
T19	830687	0	0	0
T22	96841	118	0	0
T23	102787	180	0	0
T24	184663	0	0	0
T49	137923	0	0	0
T51	0	88	0	0
T53	0	149	0	0
T61	401627	0	0	0
T62	946576	0	0	0
T63	134454	0	0	0
T66	0	278	0	0
T67	197885	0	0	0
T75	0	62	0	0
T112	0	96	0	0
T113	0	133	0	0
T114	0	96	0	0
T115	0	258	0	0