Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44


Total test records in report: 1038
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T789 /workspace/coverage/default/38.sram_ctrl_access_during_key_req.2215305956 Jun 30 04:45:21 PM PDT 24 Jun 30 05:01:04 PM PDT 24 9415851729 ps
T790 /workspace/coverage/default/8.sram_ctrl_mem_walk.3329266850 Jun 30 04:44:04 PM PDT 24 Jun 30 04:46:41 PM PDT 24 13837253977 ps
T791 /workspace/coverage/default/27.sram_ctrl_access_during_key_req.2273555858 Jun 30 04:44:35 PM PDT 24 Jun 30 04:49:16 PM PDT 24 6748350082 ps
T792 /workspace/coverage/default/24.sram_ctrl_stress_all.4251074118 Jun 30 04:44:29 PM PDT 24 Jun 30 05:33:11 PM PDT 24 155575161269 ps
T793 /workspace/coverage/default/19.sram_ctrl_stress_all.4150307653 Jun 30 04:44:16 PM PDT 24 Jun 30 06:20:36 PM PDT 24 335494308579 ps
T794 /workspace/coverage/default/35.sram_ctrl_lc_escalation.2071502799 Jun 30 04:45:14 PM PDT 24 Jun 30 04:46:03 PM PDT 24 14910080388 ps
T795 /workspace/coverage/default/48.sram_ctrl_mem_partial_access.3499601459 Jun 30 04:46:22 PM PDT 24 Jun 30 04:47:24 PM PDT 24 1917231912 ps
T796 /workspace/coverage/default/25.sram_ctrl_executable.3458159202 Jun 30 04:44:27 PM PDT 24 Jun 30 04:47:33 PM PDT 24 5509935169 ps
T797 /workspace/coverage/default/14.sram_ctrl_multiple_keys.3459717868 Jun 30 04:44:06 PM PDT 24 Jun 30 04:50:33 PM PDT 24 35013056379 ps
T798 /workspace/coverage/default/30.sram_ctrl_regwen.1211453844 Jun 30 04:44:40 PM PDT 24 Jun 30 04:55:16 PM PDT 24 19317788043 ps
T54 /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.106355691 Jun 30 04:46:08 PM PDT 24 Jun 30 04:46:36 PM PDT 24 1901031914 ps
T799 /workspace/coverage/default/32.sram_ctrl_ram_cfg.2951754872 Jun 30 04:44:56 PM PDT 24 Jun 30 04:45:00 PM PDT 24 359487697 ps
T800 /workspace/coverage/default/16.sram_ctrl_ram_cfg.1083530406 Jun 30 04:44:00 PM PDT 24 Jun 30 04:44:04 PM PDT 24 691651671 ps
T801 /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.3643410713 Jun 30 04:45:20 PM PDT 24 Jun 30 04:49:24 PM PDT 24 8727644663 ps
T802 /workspace/coverage/default/8.sram_ctrl_max_throughput.1994442377 Jun 30 04:43:48 PM PDT 24 Jun 30 04:46:30 PM PDT 24 3061456198 ps
T803 /workspace/coverage/default/34.sram_ctrl_access_during_key_req.2690667090 Jun 30 04:45:07 PM PDT 24 Jun 30 04:59:47 PM PDT 24 11314344032 ps
T804 /workspace/coverage/default/6.sram_ctrl_bijection.2056652155 Jun 30 04:43:43 PM PDT 24 Jun 30 05:20:39 PM PDT 24 151626539678 ps
T805 /workspace/coverage/default/13.sram_ctrl_ram_cfg.2792195607 Jun 30 04:44:07 PM PDT 24 Jun 30 04:44:11 PM PDT 24 803903623 ps
T806 /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3427859773 Jun 30 04:43:56 PM PDT 24 Jun 30 04:44:05 PM PDT 24 1426936280 ps
T807 /workspace/coverage/default/1.sram_ctrl_stress_all.3876058047 Jun 30 04:43:42 PM PDT 24 Jun 30 06:13:56 PM PDT 24 270589095675 ps
T808 /workspace/coverage/default/6.sram_ctrl_multiple_keys.814782457 Jun 30 04:43:37 PM PDT 24 Jun 30 04:56:01 PM PDT 24 64797512324 ps
T809 /workspace/coverage/default/18.sram_ctrl_mem_walk.798086375 Jun 30 04:44:24 PM PDT 24 Jun 30 04:49:43 PM PDT 24 104975450266 ps
T810 /workspace/coverage/default/11.sram_ctrl_lc_escalation.2172551498 Jun 30 04:43:59 PM PDT 24 Jun 30 04:44:44 PM PDT 24 23111393253 ps
T811 /workspace/coverage/default/46.sram_ctrl_max_throughput.3782094738 Jun 30 04:46:01 PM PDT 24 Jun 30 04:46:15 PM PDT 24 697498208 ps
T812 /workspace/coverage/default/20.sram_ctrl_partial_access.874336298 Jun 30 04:44:27 PM PDT 24 Jun 30 04:44:40 PM PDT 24 6386564083 ps
T813 /workspace/coverage/default/11.sram_ctrl_alert_test.584020897 Jun 30 04:44:01 PM PDT 24 Jun 30 04:44:03 PM PDT 24 15707244 ps
T814 /workspace/coverage/default/19.sram_ctrl_bijection.3753899202 Jun 30 04:44:12 PM PDT 24 Jun 30 05:13:09 PM PDT 24 47980276199 ps
T815 /workspace/coverage/default/43.sram_ctrl_ram_cfg.3373582047 Jun 30 04:45:51 PM PDT 24 Jun 30 04:45:55 PM PDT 24 2234568330 ps
T816 /workspace/coverage/default/23.sram_ctrl_mem_partial_access.2083308577 Jun 30 04:44:30 PM PDT 24 Jun 30 04:46:01 PM PDT 24 5584398902 ps
T817 /workspace/coverage/default/13.sram_ctrl_regwen.2261320327 Jun 30 04:44:02 PM PDT 24 Jun 30 05:03:10 PM PDT 24 11773065779 ps
T818 /workspace/coverage/default/17.sram_ctrl_mem_walk.1745224354 Jun 30 04:44:22 PM PDT 24 Jun 30 04:48:35 PM PDT 24 4583800891 ps
T819 /workspace/coverage/default/46.sram_ctrl_smoke.3134360149 Jun 30 04:46:00 PM PDT 24 Jun 30 04:46:50 PM PDT 24 1647975709 ps
T820 /workspace/coverage/default/3.sram_ctrl_ram_cfg.66094243 Jun 30 04:43:37 PM PDT 24 Jun 30 04:43:40 PM PDT 24 359391119 ps
T821 /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.199000002 Jun 30 04:44:17 PM PDT 24 Jun 30 04:45:20 PM PDT 24 1757101329 ps
T822 /workspace/coverage/default/6.sram_ctrl_mem_partial_access.2140645519 Jun 30 04:43:40 PM PDT 24 Jun 30 04:46:16 PM PDT 24 8771384243 ps
T823 /workspace/coverage/default/35.sram_ctrl_stress_all.2199436808 Jun 30 04:45:16 PM PDT 24 Jun 30 05:27:49 PM PDT 24 57445237086 ps
T824 /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.458084243 Jun 30 04:44:49 PM PDT 24 Jun 30 04:46:13 PM PDT 24 1982608665 ps
T825 /workspace/coverage/default/16.sram_ctrl_mem_partial_access.4109053454 Jun 30 04:44:22 PM PDT 24 Jun 30 04:45:44 PM PDT 24 12420063000 ps
T826 /workspace/coverage/default/42.sram_ctrl_stress_all.1597300415 Jun 30 04:45:41 PM PDT 24 Jun 30 05:53:35 PM PDT 24 499360487325 ps
T827 /workspace/coverage/default/47.sram_ctrl_ram_cfg.270703782 Jun 30 04:46:14 PM PDT 24 Jun 30 04:46:18 PM PDT 24 1405188119 ps
T828 /workspace/coverage/default/23.sram_ctrl_executable.3794749945 Jun 30 04:44:33 PM PDT 24 Jun 30 05:01:33 PM PDT 24 21728731347 ps
T829 /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3241704998 Jun 30 04:43:54 PM PDT 24 Jun 30 04:44:16 PM PDT 24 1486935308 ps
T830 /workspace/coverage/default/24.sram_ctrl_mem_walk.532246631 Jun 30 04:44:33 PM PDT 24 Jun 30 04:50:26 PM PDT 24 276768929914 ps
T831 /workspace/coverage/default/4.sram_ctrl_executable.3103115011 Jun 30 04:43:37 PM PDT 24 Jun 30 05:14:23 PM PDT 24 26317694332 ps
T832 /workspace/coverage/default/37.sram_ctrl_multiple_keys.2330653317 Jun 30 04:45:16 PM PDT 24 Jun 30 04:54:39 PM PDT 24 27210623284 ps
T833 /workspace/coverage/default/10.sram_ctrl_stress_pipeline.924449358 Jun 30 04:43:57 PM PDT 24 Jun 30 04:46:26 PM PDT 24 9511420553 ps
T834 /workspace/coverage/default/24.sram_ctrl_alert_test.2552817309 Jun 30 04:44:25 PM PDT 24 Jun 30 04:44:26 PM PDT 24 46849563 ps
T835 /workspace/coverage/default/3.sram_ctrl_mem_walk.1780992527 Jun 30 04:43:41 PM PDT 24 Jun 30 04:48:06 PM PDT 24 3942338993 ps
T836 /workspace/coverage/default/38.sram_ctrl_ram_cfg.196758458 Jun 30 04:45:19 PM PDT 24 Jun 30 04:45:23 PM PDT 24 1409839052 ps
T837 /workspace/coverage/default/23.sram_ctrl_bijection.8826971 Jun 30 04:44:21 PM PDT 24 Jun 30 05:18:03 PM PDT 24 88362781826 ps
T838 /workspace/coverage/default/13.sram_ctrl_stress_pipeline.1801815919 Jun 30 04:44:03 PM PDT 24 Jun 30 04:49:45 PM PDT 24 4554902407 ps
T839 /workspace/coverage/default/26.sram_ctrl_regwen.2926997540 Jun 30 04:44:31 PM PDT 24 Jun 30 04:48:42 PM PDT 24 2286191874 ps
T840 /workspace/coverage/default/38.sram_ctrl_stress_pipeline.4036332689 Jun 30 04:45:21 PM PDT 24 Jun 30 04:50:55 PM PDT 24 4465204483 ps
T841 /workspace/coverage/default/29.sram_ctrl_regwen.4273073523 Jun 30 04:44:42 PM PDT 24 Jun 30 04:46:41 PM PDT 24 7552011973 ps
T842 /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.970015810 Jun 30 04:44:12 PM PDT 24 Jun 30 04:51:28 PM PDT 24 29602326511 ps
T843 /workspace/coverage/default/31.sram_ctrl_stress_all.632125297 Jun 30 04:44:50 PM PDT 24 Jun 30 05:44:39 PM PDT 24 209058765334 ps
T844 /workspace/coverage/default/22.sram_ctrl_mem_walk.3338938544 Jun 30 04:44:25 PM PDT 24 Jun 30 04:50:02 PM PDT 24 44935673215 ps
T845 /workspace/coverage/default/45.sram_ctrl_max_throughput.1549064623 Jun 30 04:46:01 PM PDT 24 Jun 30 04:46:53 PM PDT 24 5228333201 ps
T846 /workspace/coverage/default/47.sram_ctrl_smoke.1380663893 Jun 30 04:46:05 PM PDT 24 Jun 30 04:46:21 PM PDT 24 10107793088 ps
T847 /workspace/coverage/default/12.sram_ctrl_max_throughput.2164030921 Jun 30 04:44:13 PM PDT 24 Jun 30 04:45:56 PM PDT 24 790890757 ps
T848 /workspace/coverage/default/40.sram_ctrl_access_during_key_req.1130308650 Jun 30 04:45:31 PM PDT 24 Jun 30 05:04:55 PM PDT 24 14414784396 ps
T849 /workspace/coverage/default/34.sram_ctrl_ram_cfg.1830013275 Jun 30 04:45:03 PM PDT 24 Jun 30 04:45:06 PM PDT 24 607155255 ps
T850 /workspace/coverage/default/42.sram_ctrl_lc_escalation.3186019114 Jun 30 04:45:41 PM PDT 24 Jun 30 04:46:19 PM PDT 24 13623653649 ps
T851 /workspace/coverage/default/0.sram_ctrl_bijection.124398256 Jun 30 04:43:30 PM PDT 24 Jun 30 05:05:40 PM PDT 24 144823216049 ps
T852 /workspace/coverage/default/0.sram_ctrl_alert_test.212067117 Jun 30 04:43:28 PM PDT 24 Jun 30 04:43:29 PM PDT 24 13426693 ps
T853 /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2009974272 Jun 30 04:44:47 PM PDT 24 Jun 30 04:45:14 PM PDT 24 1061316150 ps
T854 /workspace/coverage/default/27.sram_ctrl_partial_access.3586998113 Jun 30 04:44:38 PM PDT 24 Jun 30 04:45:46 PM PDT 24 5199684897 ps
T855 /workspace/coverage/default/5.sram_ctrl_partial_access.3748006003 Jun 30 04:43:41 PM PDT 24 Jun 30 04:43:56 PM PDT 24 1047478595 ps
T856 /workspace/coverage/default/25.sram_ctrl_bijection.967760752 Jun 30 04:44:27 PM PDT 24 Jun 30 04:58:54 PM PDT 24 168252033801 ps
T857 /workspace/coverage/default/48.sram_ctrl_access_during_key_req.1227302273 Jun 30 04:46:12 PM PDT 24 Jun 30 05:03:56 PM PDT 24 50044470363 ps
T858 /workspace/coverage/default/34.sram_ctrl_regwen.776685231 Jun 30 04:45:02 PM PDT 24 Jun 30 04:49:01 PM PDT 24 4574738064 ps
T859 /workspace/coverage/default/38.sram_ctrl_max_throughput.1405351225 Jun 30 04:45:20 PM PDT 24 Jun 30 04:45:42 PM PDT 24 2914249423 ps
T860 /workspace/coverage/default/41.sram_ctrl_alert_test.1447931015 Jun 30 04:45:44 PM PDT 24 Jun 30 04:45:45 PM PDT 24 161825883 ps
T861 /workspace/coverage/default/7.sram_ctrl_mem_partial_access.1067426472 Jun 30 04:44:03 PM PDT 24 Jun 30 04:46:53 PM PDT 24 6293151779 ps
T862 /workspace/coverage/default/46.sram_ctrl_alert_test.2292260521 Jun 30 04:46:04 PM PDT 24 Jun 30 04:46:05 PM PDT 24 13472001 ps
T863 /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.2471205558 Jun 30 04:45:13 PM PDT 24 Jun 30 04:45:21 PM PDT 24 2411661176 ps
T864 /workspace/coverage/default/43.sram_ctrl_max_throughput.2934763004 Jun 30 04:45:43 PM PDT 24 Jun 30 04:46:52 PM PDT 24 781659646 ps
T865 /workspace/coverage/default/26.sram_ctrl_lc_escalation.1423434650 Jun 30 04:44:30 PM PDT 24 Jun 30 04:45:52 PM PDT 24 13257673428 ps
T866 /workspace/coverage/default/38.sram_ctrl_alert_test.3664207877 Jun 30 04:45:21 PM PDT 24 Jun 30 04:45:22 PM PDT 24 62416460 ps
T867 /workspace/coverage/default/35.sram_ctrl_multiple_keys.2726019096 Jun 30 04:45:03 PM PDT 24 Jun 30 04:47:19 PM PDT 24 5421714607 ps
T868 /workspace/coverage/default/4.sram_ctrl_mem_walk.1441566076 Jun 30 04:43:51 PM PDT 24 Jun 30 04:49:20 PM PDT 24 27676047095 ps
T869 /workspace/coverage/default/41.sram_ctrl_stress_pipeline.3152746674 Jun 30 04:45:34 PM PDT 24 Jun 30 04:49:44 PM PDT 24 16008236763 ps
T870 /workspace/coverage/default/17.sram_ctrl_mem_partial_access.1921124144 Jun 30 04:44:07 PM PDT 24 Jun 30 04:46:55 PM PDT 24 20473490167 ps
T871 /workspace/coverage/default/33.sram_ctrl_regwen.3581679756 Jun 30 04:44:55 PM PDT 24 Jun 30 05:03:40 PM PDT 24 26133574842 ps
T872 /workspace/coverage/default/0.sram_ctrl_smoke.1865374533 Jun 30 04:43:24 PM PDT 24 Jun 30 04:43:46 PM PDT 24 3634005571 ps
T873 /workspace/coverage/default/31.sram_ctrl_multiple_keys.568029559 Jun 30 04:44:50 PM PDT 24 Jun 30 04:53:50 PM PDT 24 56338802238 ps
T874 /workspace/coverage/default/21.sram_ctrl_lc_escalation.3683730519 Jun 30 04:44:16 PM PDT 24 Jun 30 04:44:59 PM PDT 24 26614049201 ps
T875 /workspace/coverage/default/37.sram_ctrl_partial_access.1259281524 Jun 30 04:45:20 PM PDT 24 Jun 30 04:45:50 PM PDT 24 6533398722 ps
T876 /workspace/coverage/default/26.sram_ctrl_access_during_key_req.1356924512 Jun 30 04:44:34 PM PDT 24 Jun 30 05:00:13 PM PDT 24 31424279368 ps
T877 /workspace/coverage/default/28.sram_ctrl_executable.959354806 Jun 30 04:44:29 PM PDT 24 Jun 30 04:55:00 PM PDT 24 15091007553 ps
T878 /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2214916072 Jun 30 04:43:56 PM PDT 24 Jun 30 04:44:03 PM PDT 24 156592712 ps
T879 /workspace/coverage/default/43.sram_ctrl_mem_partial_access.193508153 Jun 30 04:45:50 PM PDT 24 Jun 30 04:48:34 PM PDT 24 19085143529 ps
T880 /workspace/coverage/default/17.sram_ctrl_smoke.2435313392 Jun 30 04:44:15 PM PDT 24 Jun 30 04:44:30 PM PDT 24 4131580205 ps
T881 /workspace/coverage/default/9.sram_ctrl_ram_cfg.603324092 Jun 30 04:43:54 PM PDT 24 Jun 30 04:43:58 PM PDT 24 363100327 ps
T882 /workspace/coverage/default/22.sram_ctrl_partial_access.1145445427 Jun 30 04:44:32 PM PDT 24 Jun 30 04:46:14 PM PDT 24 842884210 ps
T883 /workspace/coverage/default/44.sram_ctrl_access_during_key_req.2228833658 Jun 30 04:45:51 PM PDT 24 Jun 30 04:50:34 PM PDT 24 5438130709 ps
T884 /workspace/coverage/default/49.sram_ctrl_multiple_keys.3719700785 Jun 30 04:46:19 PM PDT 24 Jun 30 04:57:48 PM PDT 24 5731649512 ps
T885 /workspace/coverage/default/20.sram_ctrl_mem_partial_access.3394395598 Jun 30 04:44:28 PM PDT 24 Jun 30 04:46:33 PM PDT 24 1648335330 ps
T886 /workspace/coverage/default/37.sram_ctrl_stress_pipeline.1016384519 Jun 30 04:45:25 PM PDT 24 Jun 30 04:50:59 PM PDT 24 22343930633 ps
T887 /workspace/coverage/default/24.sram_ctrl_lc_escalation.2571247934 Jun 30 04:44:36 PM PDT 24 Jun 30 04:44:56 PM PDT 24 2523396100 ps
T888 /workspace/coverage/default/48.sram_ctrl_max_throughput.2252899779 Jun 30 04:46:10 PM PDT 24 Jun 30 04:46:18 PM PDT 24 1344522270 ps
T889 /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2158900610 Jun 30 04:44:09 PM PDT 24 Jun 30 04:46:11 PM PDT 24 5596735152 ps
T890 /workspace/coverage/default/20.sram_ctrl_alert_test.2400787561 Jun 30 04:44:21 PM PDT 24 Jun 30 04:44:22 PM PDT 24 40471398 ps
T891 /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2591626246 Jun 30 04:44:33 PM PDT 24 Jun 30 04:47:17 PM PDT 24 2509923789 ps
T892 /workspace/coverage/default/32.sram_ctrl_stress_pipeline.3324910639 Jun 30 04:44:50 PM PDT 24 Jun 30 04:52:51 PM PDT 24 25573727798 ps
T893 /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.4127312587 Jun 30 04:46:00 PM PDT 24 Jun 30 04:46:50 PM PDT 24 1171980567 ps
T894 /workspace/coverage/default/21.sram_ctrl_smoke.3219976491 Jun 30 04:44:32 PM PDT 24 Jun 30 04:44:42 PM PDT 24 7631656424 ps
T895 /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1757407541 Jun 30 04:46:12 PM PDT 24 Jun 30 04:51:41 PM PDT 24 16609956494 ps
T896 /workspace/coverage/default/29.sram_ctrl_partial_access.2425907183 Jun 30 04:44:41 PM PDT 24 Jun 30 04:45:09 PM PDT 24 9146990499 ps
T897 /workspace/coverage/default/24.sram_ctrl_regwen.2807641078 Jun 30 04:44:32 PM PDT 24 Jun 30 05:02:30 PM PDT 24 101964510415 ps
T898 /workspace/coverage/default/45.sram_ctrl_partial_access.3649725733 Jun 30 04:45:59 PM PDT 24 Jun 30 04:46:07 PM PDT 24 2623675388 ps
T899 /workspace/coverage/default/19.sram_ctrl_smoke.920502744 Jun 30 04:44:13 PM PDT 24 Jun 30 04:46:54 PM PDT 24 4288594442 ps
T900 /workspace/coverage/default/33.sram_ctrl_lc_escalation.2388754415 Jun 30 04:44:54 PM PDT 24 Jun 30 04:45:26 PM PDT 24 9426773105 ps
T901 /workspace/coverage/default/44.sram_ctrl_mem_walk.2008369925 Jun 30 04:46:00 PM PDT 24 Jun 30 04:49:04 PM PDT 24 35891896666 ps
T902 /workspace/coverage/default/3.sram_ctrl_stress_all.3111743949 Jun 30 04:43:40 PM PDT 24 Jun 30 06:26:42 PM PDT 24 94538682368 ps
T903 /workspace/coverage/default/3.sram_ctrl_bijection.1451536268 Jun 30 04:43:28 PM PDT 24 Jun 30 05:06:31 PM PDT 24 261010366623 ps
T904 /workspace/coverage/default/31.sram_ctrl_access_during_key_req.3640295970 Jun 30 04:44:48 PM PDT 24 Jun 30 04:58:29 PM PDT 24 28518801958 ps
T905 /workspace/coverage/default/43.sram_ctrl_regwen.1933773711 Jun 30 04:45:51 PM PDT 24 Jun 30 04:56:51 PM PDT 24 48205544917 ps
T906 /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.2803999083 Jun 30 04:44:26 PM PDT 24 Jun 30 04:45:21 PM PDT 24 5686394445 ps
T907 /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2380579588 Jun 30 04:44:19 PM PDT 24 Jun 30 04:44:40 PM PDT 24 975077415 ps
T908 /workspace/coverage/default/28.sram_ctrl_max_throughput.426632714 Jun 30 04:44:31 PM PDT 24 Jun 30 04:44:39 PM PDT 24 708130199 ps
T909 /workspace/coverage/default/4.sram_ctrl_stress_pipeline.4231646886 Jun 30 04:43:50 PM PDT 24 Jun 30 04:48:58 PM PDT 24 21537968921 ps
T910 /workspace/coverage/default/5.sram_ctrl_access_during_key_req.110015264 Jun 30 04:43:48 PM PDT 24 Jun 30 04:46:42 PM PDT 24 3370133900 ps
T911 /workspace/coverage/default/39.sram_ctrl_smoke.1117189840 Jun 30 04:45:25 PM PDT 24 Jun 30 04:45:30 PM PDT 24 420967085 ps
T912 /workspace/coverage/default/33.sram_ctrl_mem_walk.1355454192 Jun 30 04:44:59 PM PDT 24 Jun 30 04:50:38 PM PDT 24 13974935014 ps
T913 /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.3273673131 Jun 30 04:45:35 PM PDT 24 Jun 30 04:50:14 PM PDT 24 135126754330 ps
T914 /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2243306690 Jun 30 04:43:59 PM PDT 24 Jun 30 04:44:15 PM PDT 24 424258423 ps
T915 /workspace/coverage/default/42.sram_ctrl_stress_pipeline.1360186715 Jun 30 04:45:43 PM PDT 24 Jun 30 04:50:30 PM PDT 24 46362706949 ps
T916 /workspace/coverage/default/36.sram_ctrl_bijection.1668979428 Jun 30 04:45:16 PM PDT 24 Jun 30 05:20:06 PM PDT 24 180490069919 ps
T917 /workspace/coverage/default/43.sram_ctrl_mem_walk.3346181470 Jun 30 04:45:52 PM PDT 24 Jun 30 04:50:09 PM PDT 24 3982561420 ps
T918 /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3142821949 Jun 30 04:45:51 PM PDT 24 Jun 30 04:47:04 PM PDT 24 783117704 ps
T919 /workspace/coverage/default/22.sram_ctrl_stress_pipeline.1374255644 Jun 30 04:44:13 PM PDT 24 Jun 30 04:48:46 PM PDT 24 13182225012 ps
T920 /workspace/coverage/default/42.sram_ctrl_multiple_keys.749984508 Jun 30 04:45:42 PM PDT 24 Jun 30 05:01:22 PM PDT 24 9041431198 ps
T921 /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.786899944 Jun 30 04:45:50 PM PDT 24 Jun 30 04:54:24 PM PDT 24 21962226745 ps
T922 /workspace/coverage/default/17.sram_ctrl_bijection.2473172073 Jun 30 04:44:14 PM PDT 24 Jun 30 05:22:26 PM PDT 24 132924488364 ps
T923 /workspace/coverage/default/14.sram_ctrl_mem_walk.3971798002 Jun 30 04:44:08 PM PDT 24 Jun 30 04:49:05 PM PDT 24 14423517278 ps
T924 /workspace/coverage/default/39.sram_ctrl_alert_test.3876371567 Jun 30 04:45:27 PM PDT 24 Jun 30 04:45:28 PM PDT 24 105370821 ps
T925 /workspace/coverage/default/6.sram_ctrl_smoke.1095511197 Jun 30 04:43:47 PM PDT 24 Jun 30 04:44:05 PM PDT 24 4633030866 ps
T926 /workspace/coverage/default/7.sram_ctrl_bijection.3224103138 Jun 30 04:43:43 PM PDT 24 Jun 30 05:07:20 PM PDT 24 461459950446 ps
T927 /workspace/coverage/default/10.sram_ctrl_smoke.1166399554 Jun 30 04:44:00 PM PDT 24 Jun 30 04:45:02 PM PDT 24 12246198704 ps
T928 /workspace/coverage/default/28.sram_ctrl_alert_test.4017726854 Jun 30 04:44:39 PM PDT 24 Jun 30 04:44:41 PM PDT 24 11850172 ps
T929 /workspace/coverage/default/32.sram_ctrl_partial_access.1716063947 Jun 30 04:44:48 PM PDT 24 Jun 30 04:46:33 PM PDT 24 1452043272 ps
T930 /workspace/coverage/default/20.sram_ctrl_smoke.3169062762 Jun 30 04:44:12 PM PDT 24 Jun 30 04:44:21 PM PDT 24 12088020497 ps
T931 /workspace/coverage/default/29.sram_ctrl_stress_all.3512013055 Jun 30 04:44:42 PM PDT 24 Jun 30 06:23:41 PM PDT 24 166577369861 ps
T932 /workspace/coverage/default/15.sram_ctrl_executable.1672502110 Jun 30 04:44:14 PM PDT 24 Jun 30 05:15:44 PM PDT 24 36068783560 ps
T933 /workspace/coverage/default/9.sram_ctrl_smoke.3427659962 Jun 30 04:43:58 PM PDT 24 Jun 30 04:44:18 PM PDT 24 1112368698 ps
T934 /workspace/coverage/default/21.sram_ctrl_stress_pipeline.3827218471 Jun 30 04:44:19 PM PDT 24 Jun 30 04:49:35 PM PDT 24 21200083826 ps
T935 /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.919470043 Jun 30 04:46:27 PM PDT 24 Jun 30 04:51:11 PM PDT 24 9073258435 ps
T936 /workspace/coverage/default/34.sram_ctrl_max_throughput.2261586563 Jun 30 04:45:04 PM PDT 24 Jun 30 04:46:01 PM PDT 24 6166268361 ps
T937 /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.1063293188 Jun 30 04:45:30 PM PDT 24 Jun 30 04:50:46 PM PDT 24 10646773599 ps
T938 /workspace/coverage/default/32.sram_ctrl_lc_escalation.2509219427 Jun 30 04:44:49 PM PDT 24 Jun 30 04:45:57 PM PDT 24 23030610954 ps
T939 /workspace/coverage/default/13.sram_ctrl_mem_walk.4173800619 Jun 30 04:44:02 PM PDT 24 Jun 30 04:46:33 PM PDT 24 5269087679 ps
T940 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.1042508809 Jun 30 04:45:42 PM PDT 24 Jun 30 04:49:50 PM PDT 24 3855924902 ps
T72 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1417720648 Jun 30 04:42:53 PM PDT 24 Jun 30 04:42:54 PM PDT 24 73829281 ps
T941 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4160184029 Jun 30 04:42:50 PM PDT 24 Jun 30 04:42:55 PM PDT 24 1391759847 ps
T942 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2334242269 Jun 30 04:42:58 PM PDT 24 Jun 30 04:43:03 PM PDT 24 87646126 ps
T73 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2562356114 Jun 30 04:42:19 PM PDT 24 Jun 30 04:42:50 PM PDT 24 14762172811 ps
T69 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2501437750 Jun 30 04:42:29 PM PDT 24 Jun 30 04:42:32 PM PDT 24 471922551 ps
T99 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3915874658 Jun 30 04:42:54 PM PDT 24 Jun 30 04:42:56 PM PDT 24 48362570 ps
T128 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4294870024 Jun 30 04:42:55 PM PDT 24 Jun 30 04:42:56 PM PDT 24 133847189 ps
T77 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.585709814 Jun 30 04:42:46 PM PDT 24 Jun 30 04:42:47 PM PDT 24 16708896 ps
T100 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1653246564 Jun 30 04:42:48 PM PDT 24 Jun 30 04:43:19 PM PDT 24 3814160331 ps
T943 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.132731570 Jun 30 04:42:49 PM PDT 24 Jun 30 04:42:52 PM PDT 24 622096084 ps
T110 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.4258961334 Jun 30 04:42:40 PM PDT 24 Jun 30 04:43:16 PM PDT 24 73997386073 ps
T78 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1231796275 Jun 30 04:42:19 PM PDT 24 Jun 30 04:42:21 PM PDT 24 51549217 ps
T944 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.531323435 Jun 30 04:42:58 PM PDT 24 Jun 30 04:43:02 PM PDT 24 318972181 ps
T945 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1479078975 Jun 30 04:42:33 PM PDT 24 Jun 30 04:42:38 PM PDT 24 1430280523 ps
T70 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4229583335 Jun 30 04:42:39 PM PDT 24 Jun 30 04:42:42 PM PDT 24 1108650119 ps
T79 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3320656499 Jun 30 04:42:55 PM PDT 24 Jun 30 04:42:56 PM PDT 24 45694519 ps
T946 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3680525248 Jun 30 04:42:22 PM PDT 24 Jun 30 04:42:25 PM PDT 24 25260591 ps
T101 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1872574320 Jun 30 04:42:29 PM PDT 24 Jun 30 04:42:31 PM PDT 24 29015026 ps
T947 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3239213187 Jun 30 04:42:39 PM PDT 24 Jun 30 04:42:44 PM PDT 24 722907560 ps
T111 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3639461989 Jun 30 04:42:39 PM PDT 24 Jun 30 04:42:40 PM PDT 24 142430747 ps
T948 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.340077529 Jun 30 04:42:51 PM PDT 24 Jun 30 04:42:54 PM PDT 24 1263179977 ps
T71 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.4121993711 Jun 30 04:42:50 PM PDT 24 Jun 30 04:42:52 PM PDT 24 227176642 ps
T949 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1371307654 Jun 30 04:42:24 PM PDT 24 Jun 30 04:42:25 PM PDT 24 52889781 ps
T950 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1991072051 Jun 30 04:42:37 PM PDT 24 Jun 30 04:42:40 PM PDT 24 118549541 ps
T951 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3147136130 Jun 30 04:42:47 PM PDT 24 Jun 30 04:42:52 PM PDT 24 112806311 ps
T120 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1934596177 Jun 30 04:42:55 PM PDT 24 Jun 30 04:42:57 PM PDT 24 143612588 ps
T121 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.4093154877 Jun 30 04:42:48 PM PDT 24 Jun 30 04:42:50 PM PDT 24 274674186 ps
T102 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.149215629 Jun 30 04:42:48 PM PDT 24 Jun 30 04:42:49 PM PDT 24 22466417 ps
T118 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3683464873 Jun 30 04:42:27 PM PDT 24 Jun 30 04:42:30 PM PDT 24 727234965 ps
T952 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1540096378 Jun 30 04:42:47 PM PDT 24 Jun 30 04:42:48 PM PDT 24 17446277 ps
T80 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2008308700 Jun 30 04:42:57 PM PDT 24 Jun 30 04:43:54 PM PDT 24 28167482321 ps
T953 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1724341251 Jun 30 04:42:40 PM PDT 24 Jun 30 04:42:46 PM PDT 24 7055430164 ps
T81 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1943307287 Jun 30 04:42:32 PM PDT 24 Jun 30 04:42:34 PM PDT 24 17807183 ps
T954 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3621257392 Jun 30 04:42:34 PM PDT 24 Jun 30 04:42:36 PM PDT 24 12457153 ps
T82 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3289723589 Jun 30 04:42:43 PM PDT 24 Jun 30 04:42:45 PM PDT 24 81526356 ps
T119 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1777516038 Jun 30 04:42:27 PM PDT 24 Jun 30 04:42:29 PM PDT 24 122724850 ps
T122 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1821569617 Jun 30 04:42:42 PM PDT 24 Jun 30 04:42:46 PM PDT 24 618110248 ps
T123 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.160132730 Jun 30 04:42:40 PM PDT 24 Jun 30 04:42:44 PM PDT 24 159648065 ps
T125 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2262451771 Jun 30 04:42:44 PM PDT 24 Jun 30 04:42:46 PM PDT 24 236209961 ps
T103 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3814092807 Jun 30 04:42:55 PM PDT 24 Jun 30 04:42:56 PM PDT 24 15384886 ps
T955 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.4207726153 Jun 30 04:42:34 PM PDT 24 Jun 30 04:43:11 PM PDT 24 28421513430 ps
T83 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3860359715 Jun 30 04:42:43 PM PDT 24 Jun 30 04:43:10 PM PDT 24 7726215129 ps
T84 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2789521959 Jun 30 04:42:17 PM PDT 24 Jun 30 04:42:18 PM PDT 24 14192596 ps
T956 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2799200665 Jun 30 04:42:48 PM PDT 24 Jun 30 04:42:52 PM PDT 24 382879595 ps
T957 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3527103311 Jun 30 04:42:58 PM PDT 24 Jun 30 04:43:02 PM PDT 24 656938710 ps
T85 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2173248333 Jun 30 04:42:59 PM PDT 24 Jun 30 04:43:55 PM PDT 24 28141017058 ps
T958 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.4081471318 Jun 30 04:42:26 PM PDT 24 Jun 30 04:42:27 PM PDT 24 15425198 ps
T959 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1489227643 Jun 30 04:42:36 PM PDT 24 Jun 30 04:42:37 PM PDT 24 140946372 ps
T87 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3831273337 Jun 30 04:42:18 PM PDT 24 Jun 30 04:43:10 PM PDT 24 7298466987 ps
T960 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.4249425518 Jun 30 04:42:50 PM PDT 24 Jun 30 04:42:52 PM PDT 24 224042339 ps
T961 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.636292613 Jun 30 04:42:35 PM PDT 24 Jun 30 04:42:37 PM PDT 24 19334318 ps
T126 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1302410696 Jun 30 04:42:19 PM PDT 24 Jun 30 04:42:22 PM PDT 24 691952592 ps
T88 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3294942112 Jun 30 04:42:14 PM PDT 24 Jun 30 04:43:10 PM PDT 24 24370923787 ps
T962 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.360900919 Jun 30 04:42:29 PM PDT 24 Jun 30 04:42:32 PM PDT 24 49404510 ps
T963 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2577977565 Jun 30 04:42:19 PM PDT 24 Jun 30 04:42:23 PM PDT 24 200221051 ps
T964 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.313143456 Jun 30 04:42:20 PM PDT 24 Jun 30 04:42:21 PM PDT 24 22508038 ps
T965 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2993673151 Jun 30 04:42:30 PM PDT 24 Jun 30 04:42:33 PM PDT 24 172460644 ps
T966 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2608983545 Jun 30 04:42:55 PM PDT 24 Jun 30 04:43:00 PM PDT 24 370841440 ps
T967 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1422882928 Jun 30 04:42:54 PM PDT 24 Jun 30 04:42:56 PM PDT 24 29269773 ps
T968 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1628951174 Jun 30 04:42:54 PM PDT 24 Jun 30 04:42:57 PM PDT 24 109550831 ps
T969 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3705519872 Jun 30 04:42:19 PM PDT 24 Jun 30 04:42:22 PM PDT 24 163539736 ps
T970 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3939685483 Jun 30 04:42:22 PM PDT 24 Jun 30 04:42:27 PM PDT 24 1350131479 ps
T971 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.267506674 Jun 30 04:42:57 PM PDT 24 Jun 30 04:43:03 PM PDT 24 489549388 ps
T94 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2995371530 Jun 30 04:42:57 PM PDT 24 Jun 30 04:43:24 PM PDT 24 7110130901 ps
T95 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3010276944 Jun 30 04:42:35 PM PDT 24 Jun 30 04:43:23 PM PDT 24 7137045300 ps
T972 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2342856776 Jun 30 04:42:56 PM PDT 24 Jun 30 04:43:01 PM PDT 24 1423176513 ps
T973 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1612346895 Jun 30 04:42:15 PM PDT 24 Jun 30 04:42:16 PM PDT 24 91328451 ps
T96 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1259141932 Jun 30 04:42:35 PM PDT 24 Jun 30 04:43:28 PM PDT 24 7234097057 ps
T974 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3183566652 Jun 30 04:42:35 PM PDT 24 Jun 30 04:42:39 PM PDT 24 931929969 ps
T975 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.169696443 Jun 30 04:42:56 PM PDT 24 Jun 30 04:42:59 PM PDT 24 387042496 ps
T976 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1811291340 Jun 30 04:42:52 PM PDT 24 Jun 30 04:42:56 PM PDT 24 1435288076 ps
T977 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.4017156636 Jun 30 04:42:47 PM PDT 24 Jun 30 04:43:36 PM PDT 24 7057785720 ps
T978 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1114527811 Jun 30 04:42:44 PM PDT 24 Jun 30 04:42:46 PM PDT 24 15802289 ps
T979 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3914231270 Jun 30 04:42:49 PM PDT 24 Jun 30 04:42:50 PM PDT 24 28883211 ps
T980 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1751114323 Jun 30 04:43:00 PM PDT 24 Jun 30 04:43:03 PM PDT 24 733011636 ps
T981 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2224745471 Jun 30 04:42:21 PM PDT 24 Jun 30 04:42:22 PM PDT 24 34749933 ps
T982 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2003875980 Jun 30 04:42:25 PM PDT 24 Jun 30 04:42:27 PM PDT 24 316574483 ps
T983 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2952557871 Jun 30 04:42:28 PM PDT 24 Jun 30 04:42:29 PM PDT 24 15199385 ps
T984 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1108703944 Jun 30 04:42:42 PM PDT 24 Jun 30 04:43:33 PM PDT 24 7475681028 ps
T985 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1248870173 Jun 30 04:42:19 PM PDT 24 Jun 30 04:42:21 PM PDT 24 27119600 ps
T986 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1989378608 Jun 30 04:42:31 PM PDT 24 Jun 30 04:42:34 PM PDT 24 375408408 ps
T987 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3546880768 Jun 30 04:42:56 PM PDT 24 Jun 30 04:42:57 PM PDT 24 32395857 ps
T988 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3042038390 Jun 30 04:42:47 PM PDT 24 Jun 30 04:42:48 PM PDT 24 36542635 ps
T989 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1275912549 Jun 30 04:42:45 PM PDT 24 Jun 30 04:42:50 PM PDT 24 108430435 ps
T990 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.623565674 Jun 30 04:42:15 PM PDT 24 Jun 30 04:42:20 PM PDT 24 359698444 ps
T991 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2038463428 Jun 30 04:42:31 PM PDT 24 Jun 30 04:42:33 PM PDT 24 298569834 ps
T992 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1898034113 Jun 30 04:42:34 PM PDT 24 Jun 30 04:42:37 PM PDT 24 261883941 ps
T993 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1129525283 Jun 30 04:42:48 PM PDT 24 Jun 30 04:42:49 PM PDT 24 24034441 ps
T994 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2095130800 Jun 30 04:42:58 PM PDT 24 Jun 30 04:43:50 PM PDT 24 7816034518 ps
T995 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3652334044 Jun 30 04:42:32 PM PDT 24 Jun 30 04:42:37 PM PDT 24 363693454 ps
T996 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1718584960 Jun 30 04:42:19 PM PDT 24 Jun 30 04:42:21 PM PDT 24 14879496 ps
T997 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.756424427 Jun 30 04:42:57 PM PDT 24 Jun 30 04:42:58 PM PDT 24 26607230 ps
T998 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2695993111 Jun 30 04:42:20 PM PDT 24 Jun 30 04:42:22 PM PDT 24 72463956 ps
T999 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3897082483 Jun 30 04:42:59 PM PDT 24 Jun 30 04:43:03 PM PDT 24 356876643 ps
T1000 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1436949767 Jun 30 04:42:40 PM PDT 24 Jun 30 04:43:07 PM PDT 24 7599193473 ps
T1001 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.391487458 Jun 30 04:42:32 PM PDT 24 Jun 30 04:42:33 PM PDT 24 32764095 ps
T1002 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2924454434 Jun 30 04:42:24 PM PDT 24 Jun 30 04:43:19 PM PDT 24 14175877364 ps
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