Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44


Total test records in report: 1038
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T1003 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.696770242 Jun 30 04:42:38 PM PDT 24 Jun 30 04:43:29 PM PDT 24 15003650642 ps
T1004 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.31324593 Jun 30 04:42:33 PM PDT 24 Jun 30 04:42:38 PM PDT 24 351375921 ps
T1005 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.614722768 Jun 30 04:42:26 PM PDT 24 Jun 30 04:42:31 PM PDT 24 2648373469 ps
T1006 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3305350464 Jun 30 04:42:32 PM PDT 24 Jun 30 04:43:25 PM PDT 24 28438732244 ps
T1007 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2567024237 Jun 30 04:42:23 PM PDT 24 Jun 30 04:42:24 PM PDT 24 15872984 ps
T1008 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2816847538 Jun 30 04:42:57 PM PDT 24 Jun 30 04:42:59 PM PDT 24 53356489 ps
T127 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2552219799 Jun 30 04:42:47 PM PDT 24 Jun 30 04:42:49 PM PDT 24 97334824 ps
T1009 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2316548832 Jun 30 04:42:41 PM PDT 24 Jun 30 04:42:47 PM PDT 24 4907982681 ps
T1010 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1021961971 Jun 30 04:42:48 PM PDT 24 Jun 30 04:43:15 PM PDT 24 15462546820 ps
T1011 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1511252315 Jun 30 04:42:22 PM PDT 24 Jun 30 04:42:24 PM PDT 24 880189483 ps
T1012 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.666762653 Jun 30 04:42:49 PM PDT 24 Jun 30 04:42:50 PM PDT 24 31362225 ps
T1013 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3460145104 Jun 30 04:42:30 PM PDT 24 Jun 30 04:42:31 PM PDT 24 46549531 ps
T1014 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1557020953 Jun 30 04:42:33 PM PDT 24 Jun 30 04:42:36 PM PDT 24 84003223 ps
T124 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1658233407 Jun 30 04:42:26 PM PDT 24 Jun 30 04:42:29 PM PDT 24 503469084 ps
T1015 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3558658871 Jun 30 04:42:47 PM PDT 24 Jun 30 04:42:48 PM PDT 24 17216336 ps
T1016 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2657557485 Jun 30 04:42:28 PM PDT 24 Jun 30 04:42:32 PM PDT 24 48443693 ps
T1017 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3427295275 Jun 30 04:42:27 PM PDT 24 Jun 30 04:42:32 PM PDT 24 83801775 ps
T1018 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.879391687 Jun 30 04:42:44 PM PDT 24 Jun 30 04:42:47 PM PDT 24 37684561 ps
T1019 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3863788934 Jun 30 04:42:22 PM PDT 24 Jun 30 04:42:23 PM PDT 24 94062932 ps
T1020 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2395297656 Jun 30 04:42:47 PM PDT 24 Jun 30 04:42:48 PM PDT 24 24398229 ps
T1021 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2190759654 Jun 30 04:42:09 PM PDT 24 Jun 30 04:42:11 PM PDT 24 306973392 ps
T1022 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2136532416 Jun 30 04:42:42 PM PDT 24 Jun 30 04:42:44 PM PDT 24 13375894 ps
T1023 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.830136642 Jun 30 04:42:36 PM PDT 24 Jun 30 04:42:39 PM PDT 24 37795882 ps
T1024 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2072863320 Jun 30 04:42:40 PM PDT 24 Jun 30 04:42:42 PM PDT 24 13086359 ps
T1025 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3116886557 Jun 30 04:42:43 PM PDT 24 Jun 30 04:42:45 PM PDT 24 26554269 ps
T1026 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3730695125 Jun 30 04:42:41 PM PDT 24 Jun 30 04:42:43 PM PDT 24 18484974 ps
T1027 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1104692625 Jun 30 04:42:32 PM PDT 24 Jun 30 04:42:34 PM PDT 24 24642702 ps
T1028 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.171536457 Jun 30 04:42:47 PM PDT 24 Jun 30 04:42:51 PM PDT 24 78574377 ps
T1029 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3155581897 Jun 30 04:42:44 PM PDT 24 Jun 30 04:42:46 PM PDT 24 15420692 ps
T1030 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3273090064 Jun 30 04:42:42 PM PDT 24 Jun 30 04:42:46 PM PDT 24 1417758205 ps
T1031 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2188164883 Jun 30 04:42:18 PM PDT 24 Jun 30 04:42:19 PM PDT 24 14199729 ps
T1032 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3539143239 Jun 30 04:42:35 PM PDT 24 Jun 30 04:42:37 PM PDT 24 18317693 ps
T1033 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.4124171914 Jun 30 04:42:53 PM PDT 24 Jun 30 04:42:58 PM PDT 24 2500166935 ps
T1034 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2983955399 Jun 30 04:42:56 PM PDT 24 Jun 30 04:43:00 PM PDT 24 705489117 ps
T1035 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1568851294 Jun 30 04:42:31 PM PDT 24 Jun 30 04:42:35 PM PDT 24 3371706985 ps
T1036 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2048487709 Jun 30 04:42:32 PM PDT 24 Jun 30 04:42:33 PM PDT 24 28833690 ps
T1037 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3195722687 Jun 30 04:42:33 PM PDT 24 Jun 30 04:42:34 PM PDT 24 39487029 ps
T1038 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2336963045 Jun 30 04:42:21 PM PDT 24 Jun 30 04:42:22 PM PDT 24 34830743 ps

Test location /workspace/coverage/default/38.sram_ctrl_lc_escalation.1036978029
Short name T6
Test name
Test status
Simulation time 19932157604 ps
CPU time 59.08 seconds
Started Jun 30 04:45:19 PM PDT 24
Finished Jun 30 04:46:19 PM PDT 24
Peak memory 202752 kb
Host smart-c24bf1b8-5cb5-4895-bace-27c1cdf8041a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036978029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es
calation.1036978029
Directory /workspace/38.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.103235438
Short name T58
Test name
Test status
Simulation time 650371793 ps
CPU time 47.47 seconds
Started Jun 30 04:46:25 PM PDT 24
Finished Jun 30 04:47:13 PM PDT 24
Peak memory 291472 kb
Host smart-685ba679-e498-4c1e-a8a2-6fe1e7897046
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=103235438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.103235438
Directory /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_partial_access.3558827457
Short name T41
Test name
Test status
Simulation time 34096515977 ps
CPU time 170.3 seconds
Started Jun 30 04:44:51 PM PDT 24
Finished Jun 30 04:47:41 PM PDT 24
Peak memory 210920 kb
Host smart-e8e16409-9ba4-4d76-80c6-94ed34e41fd4
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558827457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_mem_partial_access.3558827457
Directory /workspace/31.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all.147280329
Short name T47
Test name
Test status
Simulation time 103462909282 ps
CPU time 4053.52 seconds
Started Jun 30 04:44:06 PM PDT 24
Finished Jun 30 05:51:42 PM PDT 24
Peak memory 388776 kb
Host smart-61150ed1-4ed3-4890-aa43-3400d4b653f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147280329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 16.sram_ctrl_stress_all.147280329
Directory /workspace/16.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_partial_access.1999758300
Short name T12
Test name
Test status
Simulation time 1722350624 ps
CPU time 138.92 seconds
Started Jun 30 04:45:21 PM PDT 24
Finished Jun 30 04:47:40 PM PDT 24
Peak memory 218948 kb
Host smart-02633806-c390-4bf3-8b0e-52c5c85b8f94
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999758300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_mem_partial_access.1999758300
Directory /workspace/37.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4229583335
Short name T70
Test name
Test status
Simulation time 1108650119 ps
CPU time 2.3 seconds
Started Jun 30 04:42:39 PM PDT 24
Finished Jun 30 04:42:42 PM PDT 24
Peak memory 213524 kb
Host smart-1fafd78a-99c7-4d49-b530-9896b1740352
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229583335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 8.sram_ctrl_tl_intg_err.4229583335
Directory /workspace/8.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sram_ctrl_sec_cm.73954807
Short name T16
Test name
Test status
Simulation time 1698116900 ps
CPU time 3.51 seconds
Started Jun 30 04:43:28 PM PDT 24
Finished Jun 30 04:43:42 PM PDT 24
Peak memory 221928 kb
Host smart-0ee6efeb-0dab-45c7-ad90-3181cf7b9ee7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73954807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
sram_ctrl_sec_cm.73954807
Directory /workspace/0.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3738776343
Short name T135
Test name
Test status
Simulation time 85047564239 ps
CPU time 455.12 seconds
Started Jun 30 04:44:05 PM PDT 24
Finished Jun 30 04:51:42 PM PDT 24
Peak memory 202744 kb
Host smart-4951b8a1-5066-4545-81ac-e927eb3586b2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738776343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 14.sram_ctrl_partial_access_b2b.3738776343
Directory /workspace/14.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2323310087
Short name T22
Test name
Test status
Simulation time 4035122757 ps
CPU time 24.59 seconds
Started Jun 30 04:44:20 PM PDT 24
Finished Jun 30 04:44:45 PM PDT 24
Peak memory 212024 kb
Host smart-3e02dce0-2b10-43d9-a0c5-38f56b3df7f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2323310087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.2323310087
Directory /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2562356114
Short name T73
Test name
Test status
Simulation time 14762172811 ps
CPU time 29.74 seconds
Started Jun 30 04:42:19 PM PDT 24
Finished Jun 30 04:42:50 PM PDT 24
Peak memory 202092 kb
Host smart-2cf8808e-61e3-42d9-bd7c-add3dbd3557b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562356114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.2562356114
Directory /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/14.sram_ctrl_alert_test.1230971376
Short name T336
Test name
Test status
Simulation time 17535353 ps
CPU time 0.71 seconds
Started Jun 30 04:44:00 PM PDT 24
Finished Jun 30 04:44:02 PM PDT 24
Peak memory 202236 kb
Host smart-7e918fda-5bc4-4cba-89ba-f66e530cf7fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230971376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.sram_ctrl_alert_test.1230971376
Directory /workspace/14.sram_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.160132730
Short name T123
Test name
Test status
Simulation time 159648065 ps
CPU time 2.17 seconds
Started Jun 30 04:42:40 PM PDT 24
Finished Jun 30 04:42:44 PM PDT 24
Peak memory 210972 kb
Host smart-70fa298e-3104-48c0-8398-90d7f84e3a48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160132730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 11.sram_ctrl_tl_intg_err.160132730
Directory /workspace/11.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all.2232711405
Short name T76
Test name
Test status
Simulation time 810261523953 ps
CPU time 3835.49 seconds
Started Jun 30 04:45:31 PM PDT 24
Finished Jun 30 05:49:27 PM PDT 24
Peak memory 380660 kb
Host smart-62620118-d0ce-40c6-861f-a362634ef05d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232711405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 39.sram_ctrl_stress_all.2232711405
Directory /workspace/39.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sram_ctrl_ram_cfg.759513426
Short name T210
Test name
Test status
Simulation time 6718519461 ps
CPU time 5.51 seconds
Started Jun 30 04:43:28 PM PDT 24
Finished Jun 30 04:43:34 PM PDT 24
Peak memory 202784 kb
Host smart-569ca617-b96e-4f21-a885-2cca0136a845
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759513426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.759513426
Directory /workspace/0.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.694318320
Short name T53
Test name
Test status
Simulation time 3205148099 ps
CPU time 30.23 seconds
Started Jun 30 04:45:58 PM PDT 24
Finished Jun 30 04:46:29 PM PDT 24
Peak memory 211060 kb
Host smart-177acbd3-17d8-4e35-a968-fd0bc5fca9ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=694318320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.694318320
Directory /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sram_ctrl_regwen.1808836414
Short name T129
Test name
Test status
Simulation time 8216480840 ps
CPU time 844.24 seconds
Started Jun 30 04:44:07 PM PDT 24
Finished Jun 30 04:58:13 PM PDT 24
Peak memory 375576 kb
Host smart-c93578b9-a045-4d5b-b5fe-e65c7edd7ba7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808836414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.1808836414
Directory /workspace/11.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all.3591266026
Short name T237
Test name
Test status
Simulation time 290873445288 ps
CPU time 4346.91 seconds
Started Jun 30 04:43:59 PM PDT 24
Finished Jun 30 05:56:28 PM PDT 24
Peak memory 378656 kb
Host smart-33f0a1cd-f867-4a0c-acdd-18a1ff3bcf8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591266026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 12.sram_ctrl_stress_all.3591266026
Directory /workspace/12.sram_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.4249425518
Short name T960
Test name
Test status
Simulation time 224042339 ps
CPU time 2.28 seconds
Started Jun 30 04:42:50 PM PDT 24
Finished Jun 30 04:42:52 PM PDT 24
Peak memory 210972 kb
Host smart-64aee3da-7767-42ff-a31a-abf46e05d579
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249425518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 12.sram_ctrl_tl_intg_err.4249425518
Directory /workspace/12.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1658233407
Short name T124
Test name
Test status
Simulation time 503469084 ps
CPU time 2.54 seconds
Started Jun 30 04:42:26 PM PDT 24
Finished Jun 30 04:42:29 PM PDT 24
Peak memory 210948 kb
Host smart-3a7bbb70-ddbe-488d-9f1b-0dfeeec98e39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658233407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.sram_ctrl_tl_intg_err.1658233407
Directory /workspace/3.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_pipeline.1683123779
Short name T104
Test name
Test status
Simulation time 24175553362 ps
CPU time 272.63 seconds
Started Jun 30 04:44:12 PM PDT 24
Finished Jun 30 04:48:46 PM PDT 24
Peak memory 202692 kb
Host smart-98e979da-376d-441b-b4c7-97b5071300ed
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683123779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_stress_pipeline.1683123779
Directory /workspace/12.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2789521959
Short name T84
Test name
Test status
Simulation time 14192596 ps
CPU time 0.66 seconds
Started Jun 30 04:42:17 PM PDT 24
Finished Jun 30 04:42:18 PM PDT 24
Peak memory 202584 kb
Host smart-de72739d-52c9-465e-b3c4-927231fed4b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789521959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_aliasing.2789521959
Directory /workspace/0.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2190759654
Short name T1021
Test name
Test status
Simulation time 306973392 ps
CPU time 1.96 seconds
Started Jun 30 04:42:09 PM PDT 24
Finished Jun 30 04:42:11 PM PDT 24
Peak memory 202744 kb
Host smart-cafee547-a9ea-4763-ada0-5ccc309a4cb2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190759654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_bit_bash.2190759654
Directory /workspace/0.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.4081471318
Short name T958
Test name
Test status
Simulation time 15425198 ps
CPU time 0.65 seconds
Started Jun 30 04:42:26 PM PDT 24
Finished Jun 30 04:42:27 PM PDT 24
Peak memory 202548 kb
Host smart-7dbeffd9-7e4e-44ef-92bf-37c1f64a33c3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081471318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_hw_reset.4081471318
Directory /workspace/0.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.623565674
Short name T990
Test name
Test status
Simulation time 359698444 ps
CPU time 4.22 seconds
Started Jun 30 04:42:15 PM PDT 24
Finished Jun 30 04:42:20 PM PDT 24
Peak memory 211024 kb
Host smart-78f469ce-14c5-4682-9cc3-acb49a4c2b7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623565674 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.623565674
Directory /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3289723589
Short name T82
Test name
Test status
Simulation time 81526356 ps
CPU time 0.69 seconds
Started Jun 30 04:42:43 PM PDT 24
Finished Jun 30 04:42:45 PM PDT 24
Peak memory 202544 kb
Host smart-a6f42b8e-0137-4ccc-80c5-f098f4455f2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289723589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_csr_rw.3289723589
Directory /workspace/0.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3294942112
Short name T88
Test name
Test status
Simulation time 24370923787 ps
CPU time 55.17 seconds
Started Jun 30 04:42:14 PM PDT 24
Finished Jun 30 04:43:10 PM PDT 24
Peak memory 203016 kb
Host smart-bcd78247-bfbd-4a84-b64c-1464896907d3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294942112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.3294942112
Directory /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1248870173
Short name T985
Test name
Test status
Simulation time 27119600 ps
CPU time 0.88 seconds
Started Jun 30 04:42:19 PM PDT 24
Finished Jun 30 04:42:21 PM PDT 24
Peak memory 202540 kb
Host smart-8386b72d-2288-4d77-a346-152e99fa2e41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248870173 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.1248870173
Directory /workspace/0.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2577977565
Short name T963
Test name
Test status
Simulation time 200221051 ps
CPU time 3.93 seconds
Started Jun 30 04:42:19 PM PDT 24
Finished Jun 30 04:42:23 PM PDT 24
Peak memory 211004 kb
Host smart-1e4a98f9-4489-45ef-a86e-319be67583bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577977565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.sram_ctrl_tl_errors.2577977565
Directory /workspace/0.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1612346895
Short name T973
Test name
Test status
Simulation time 91328451 ps
CPU time 1.46 seconds
Started Jun 30 04:42:15 PM PDT 24
Finished Jun 30 04:42:16 PM PDT 24
Peak memory 211032 kb
Host smart-a33dd0f3-3751-4252-8a30-66489b8df9b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612346895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 0.sram_ctrl_tl_intg_err.1612346895
Directory /workspace/0.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1718584960
Short name T996
Test name
Test status
Simulation time 14879496 ps
CPU time 0.77 seconds
Started Jun 30 04:42:19 PM PDT 24
Finished Jun 30 04:42:21 PM PDT 24
Peak memory 202392 kb
Host smart-0b31face-b8df-4711-86b6-2cce3ba86a38
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718584960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_aliasing.1718584960
Directory /workspace/1.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1989378608
Short name T986
Test name
Test status
Simulation time 375408408 ps
CPU time 2.1 seconds
Started Jun 30 04:42:31 PM PDT 24
Finished Jun 30 04:42:34 PM PDT 24
Peak memory 201956 kb
Host smart-5e853cab-50e1-4c8b-8f9a-9f919fe1a94e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989378608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_bit_bash.1989378608
Directory /workspace/1.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.313143456
Short name T964
Test name
Test status
Simulation time 22508038 ps
CPU time 0.7 seconds
Started Jun 30 04:42:20 PM PDT 24
Finished Jun 30 04:42:21 PM PDT 24
Peak memory 202520 kb
Host smart-c2f80d19-2d6e-4f1f-a83a-9a0b7df568cd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313143456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.sram_ctrl_csr_hw_reset.313143456
Directory /workspace/1.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3939685483
Short name T970
Test name
Test status
Simulation time 1350131479 ps
CPU time 3.71 seconds
Started Jun 30 04:42:22 PM PDT 24
Finished Jun 30 04:42:27 PM PDT 24
Peak memory 202584 kb
Host smart-d7ea30a0-33d2-4c6e-a807-9cf4ee5e2aab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939685483 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.3939685483
Directory /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2188164883
Short name T1031
Test name
Test status
Simulation time 14199729 ps
CPU time 0.73 seconds
Started Jun 30 04:42:18 PM PDT 24
Finished Jun 30 04:42:19 PM PDT 24
Peak memory 201648 kb
Host smart-375b6d87-4a98-41a2-bc8d-62f8c0d6be07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188164883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_csr_rw.2188164883
Directory /workspace/1.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2924454434
Short name T1002
Test name
Test status
Simulation time 14175877364 ps
CPU time 55.03 seconds
Started Jun 30 04:42:24 PM PDT 24
Finished Jun 30 04:43:19 PM PDT 24
Peak memory 202956 kb
Host smart-c9f054bb-7e1c-4264-8d7b-5bfb5c1a2e0d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924454434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.2924454434
Directory /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2224745471
Short name T981
Test name
Test status
Simulation time 34749933 ps
CPU time 0.7 seconds
Started Jun 30 04:42:21 PM PDT 24
Finished Jun 30 04:42:22 PM PDT 24
Peak memory 202580 kb
Host smart-7cf0b6eb-eff7-4d94-a1a6-64d118ad2db1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224745471 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.2224745471
Directory /workspace/1.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.360900919
Short name T962
Test name
Test status
Simulation time 49404510 ps
CPU time 2.73 seconds
Started Jun 30 04:42:29 PM PDT 24
Finished Jun 30 04:42:32 PM PDT 24
Peak memory 202780 kb
Host smart-e70af046-de6a-47db-a6ae-64d2941bdcb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360900919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_tl_errors.360900919
Directory /workspace/1.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1302410696
Short name T126
Test name
Test status
Simulation time 691952592 ps
CPU time 2.65 seconds
Started Jun 30 04:42:19 PM PDT 24
Finished Jun 30 04:42:22 PM PDT 24
Peak memory 211048 kb
Host smart-a5ab2108-ceb0-4eb7-9cc6-64dabab9759e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302410696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 1.sram_ctrl_tl_intg_err.1302410696
Directory /workspace/1.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1724341251
Short name T953
Test name
Test status
Simulation time 7055430164 ps
CPU time 5.25 seconds
Started Jun 30 04:42:40 PM PDT 24
Finished Jun 30 04:42:46 PM PDT 24
Peak memory 211068 kb
Host smart-099f4247-b9df-45f3-948c-c27a2bb48100
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724341251 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.1724341251
Directory /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3155581897
Short name T1029
Test name
Test status
Simulation time 15420692 ps
CPU time 0.67 seconds
Started Jun 30 04:42:44 PM PDT 24
Finished Jun 30 04:42:46 PM PDT 24
Peak memory 202540 kb
Host smart-31ec4a82-34c2-4e11-bda7-e7b7aeae9463
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155581897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_csr_rw.3155581897
Directory /workspace/10.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.4258961334
Short name T110
Test name
Test status
Simulation time 73997386073 ps
CPU time 34.81 seconds
Started Jun 30 04:42:40 PM PDT 24
Finished Jun 30 04:43:16 PM PDT 24
Peak memory 202968 kb
Host smart-f4ef1fb2-9785-4232-8dfa-4f2f619ee417
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258961334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.4258961334
Directory /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2072863320
Short name T1024
Test name
Test status
Simulation time 13086359 ps
CPU time 0.72 seconds
Started Jun 30 04:42:40 PM PDT 24
Finished Jun 30 04:42:42 PM PDT 24
Peak memory 202556 kb
Host smart-e859d967-dea2-40fb-9699-fb2f1be9688f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072863320 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.2072863320
Directory /workspace/10.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.879391687
Short name T1018
Test name
Test status
Simulation time 37684561 ps
CPU time 2.08 seconds
Started Jun 30 04:42:44 PM PDT 24
Finished Jun 30 04:42:47 PM PDT 24
Peak memory 202324 kb
Host smart-8fd2cfd3-1e1b-4864-a9f3-c5370d4140c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879391687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
10.sram_ctrl_tl_errors.879391687
Directory /workspace/10.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2262451771
Short name T125
Test name
Test status
Simulation time 236209961 ps
CPU time 1.49 seconds
Started Jun 30 04:42:44 PM PDT 24
Finished Jun 30 04:42:46 PM PDT 24
Peak memory 202816 kb
Host smart-d05d0b5c-bdaa-4ce8-bdf3-792bb2411c95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262451771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 10.sram_ctrl_tl_intg_err.2262451771
Directory /workspace/10.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2316548832
Short name T1009
Test name
Test status
Simulation time 4907982681 ps
CPU time 5.26 seconds
Started Jun 30 04:42:41 PM PDT 24
Finished Jun 30 04:42:47 PM PDT 24
Peak memory 211052 kb
Host smart-f8810a63-cfec-42a2-9f59-90c7c371e26b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316548832 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.2316548832
Directory /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1540096378
Short name T952
Test name
Test status
Simulation time 17446277 ps
CPU time 0.69 seconds
Started Jun 30 04:42:47 PM PDT 24
Finished Jun 30 04:42:48 PM PDT 24
Peak memory 202524 kb
Host smart-5fa72f12-df44-4c8a-975b-efe33270f713
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540096378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_csr_rw.1540096378
Directory /workspace/11.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1108703944
Short name T984
Test name
Test status
Simulation time 7475681028 ps
CPU time 50.47 seconds
Started Jun 30 04:42:42 PM PDT 24
Finished Jun 30 04:43:33 PM PDT 24
Peak memory 202988 kb
Host smart-51c81bc2-9ba0-46e1-89d7-37e4f376d914
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108703944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.1108703944
Directory /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2136532416
Short name T1022
Test name
Test status
Simulation time 13375894 ps
CPU time 0.72 seconds
Started Jun 30 04:42:42 PM PDT 24
Finished Jun 30 04:42:44 PM PDT 24
Peak memory 202528 kb
Host smart-8d8d1a4a-d2b8-43df-956d-7e023e3367d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136532416 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.2136532416
Directory /workspace/11.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.171536457
Short name T1028
Test name
Test status
Simulation time 78574377 ps
CPU time 3.08 seconds
Started Jun 30 04:42:47 PM PDT 24
Finished Jun 30 04:42:51 PM PDT 24
Peak memory 210988 kb
Host smart-3d1b8edf-e5e0-40f2-99ba-492ce0481daf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171536457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
11.sram_ctrl_tl_errors.171536457
Directory /workspace/11.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2799200665
Short name T956
Test name
Test status
Simulation time 382879595 ps
CPU time 3.82 seconds
Started Jun 30 04:42:48 PM PDT 24
Finished Jun 30 04:42:52 PM PDT 24
Peak memory 210688 kb
Host smart-28d7efa0-5e97-46a4-a65c-199e9b105d39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799200665 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.2799200665
Directory /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.149215629
Short name T102
Test name
Test status
Simulation time 22466417 ps
CPU time 0.64 seconds
Started Jun 30 04:42:48 PM PDT 24
Finished Jun 30 04:42:49 PM PDT 24
Peak memory 202404 kb
Host smart-81aa985b-c367-401c-a7be-b2fec8e440cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149215629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 12.sram_ctrl_csr_rw.149215629
Directory /workspace/12.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1436949767
Short name T1000
Test name
Test status
Simulation time 7599193473 ps
CPU time 27.02 seconds
Started Jun 30 04:42:40 PM PDT 24
Finished Jun 30 04:43:07 PM PDT 24
Peak memory 202804 kb
Host smart-4b3ec610-bfbe-4b8a-bb96-48a4f352921d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436949767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.1436949767
Directory /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1417720648
Short name T72
Test name
Test status
Simulation time 73829281 ps
CPU time 0.88 seconds
Started Jun 30 04:42:53 PM PDT 24
Finished Jun 30 04:42:54 PM PDT 24
Peak memory 202556 kb
Host smart-ec7c6cca-b401-494e-9794-193949a1261b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417720648 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.1417720648
Directory /workspace/12.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3147136130
Short name T951
Test name
Test status
Simulation time 112806311 ps
CPU time 3.86 seconds
Started Jun 30 04:42:47 PM PDT 24
Finished Jun 30 04:42:52 PM PDT 24
Peak memory 210996 kb
Host smart-91b66526-f688-406c-a14d-2307ed0f2c49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147136130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.sram_ctrl_tl_errors.3147136130
Directory /workspace/12.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4160184029
Short name T941
Test name
Test status
Simulation time 1391759847 ps
CPU time 4.17 seconds
Started Jun 30 04:42:50 PM PDT 24
Finished Jun 30 04:42:55 PM PDT 24
Peak memory 210792 kb
Host smart-156ce207-1116-4ee0-8ade-d786bacf43dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160184029 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.4160184029
Directory /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2395297656
Short name T1020
Test name
Test status
Simulation time 24398229 ps
CPU time 0.67 seconds
Started Jun 30 04:42:47 PM PDT 24
Finished Jun 30 04:42:48 PM PDT 24
Peak memory 202524 kb
Host smart-f2e7621f-07e0-41c1-90d5-ba59d62658b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395297656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_csr_rw.2395297656
Directory /workspace/13.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.4017156636
Short name T977
Test name
Test status
Simulation time 7057785720 ps
CPU time 48.61 seconds
Started Jun 30 04:42:47 PM PDT 24
Finished Jun 30 04:43:36 PM PDT 24
Peak memory 203012 kb
Host smart-69144602-c18d-4aec-8164-c17c26161ccd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017156636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.4017156636
Directory /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1129525283
Short name T993
Test name
Test status
Simulation time 24034441 ps
CPU time 0.77 seconds
Started Jun 30 04:42:48 PM PDT 24
Finished Jun 30 04:42:49 PM PDT 24
Peak memory 202504 kb
Host smart-beb366dc-5cc2-4756-95fb-9973d4e68580
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129525283 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.1129525283
Directory /workspace/13.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1275912549
Short name T989
Test name
Test status
Simulation time 108430435 ps
CPU time 3.88 seconds
Started Jun 30 04:42:45 PM PDT 24
Finished Jun 30 04:42:50 PM PDT 24
Peak memory 211164 kb
Host smart-319d1aaa-1d5b-477b-8d4d-21f8809bc677
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275912549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.sram_ctrl_tl_errors.1275912549
Directory /workspace/13.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.4121993711
Short name T71
Test name
Test status
Simulation time 227176642 ps
CPU time 1.5 seconds
Started Jun 30 04:42:50 PM PDT 24
Finished Jun 30 04:42:52 PM PDT 24
Peak memory 202760 kb
Host smart-5eed9df2-1ebb-4f66-8d36-f2cbf420668f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121993711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 13.sram_ctrl_tl_intg_err.4121993711
Directory /workspace/13.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.4124171914
Short name T1033
Test name
Test status
Simulation time 2500166935 ps
CPU time 4.41 seconds
Started Jun 30 04:42:53 PM PDT 24
Finished Jun 30 04:42:58 PM PDT 24
Peak memory 210796 kb
Host smart-805526f8-a000-416b-b8e4-e32dec2e26b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124171914 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.4124171914
Directory /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3558658871
Short name T1015
Test name
Test status
Simulation time 17216336 ps
CPU time 0.65 seconds
Started Jun 30 04:42:47 PM PDT 24
Finished Jun 30 04:42:48 PM PDT 24
Peak memory 202600 kb
Host smart-1a659137-ec53-4e93-8525-8ccfc29b6986
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558658871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_csr_rw.3558658871
Directory /workspace/14.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1021961971
Short name T1010
Test name
Test status
Simulation time 15462546820 ps
CPU time 26.27 seconds
Started Jun 30 04:42:48 PM PDT 24
Finished Jun 30 04:43:15 PM PDT 24
Peak memory 202812 kb
Host smart-2aecc29c-55e0-4a92-b331-cc9b4b975505
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021961971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.1021961971
Directory /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.666762653
Short name T1012
Test name
Test status
Simulation time 31362225 ps
CPU time 0.71 seconds
Started Jun 30 04:42:49 PM PDT 24
Finished Jun 30 04:42:50 PM PDT 24
Peak memory 202552 kb
Host smart-bde548ed-0702-490e-b6c7-9999b1f5f650
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666762653 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.666762653
Directory /workspace/14.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.340077529
Short name T948
Test name
Test status
Simulation time 1263179977 ps
CPU time 3.5 seconds
Started Jun 30 04:42:51 PM PDT 24
Finished Jun 30 04:42:54 PM PDT 24
Peak memory 202752 kb
Host smart-c2cdba86-4f9f-42cc-8e3e-294493378443
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340077529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
14.sram_ctrl_tl_errors.340077529
Directory /workspace/14.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.4093154877
Short name T121
Test name
Test status
Simulation time 274674186 ps
CPU time 1.4 seconds
Started Jun 30 04:42:48 PM PDT 24
Finished Jun 30 04:42:50 PM PDT 24
Peak memory 210680 kb
Host smart-43d41d6b-f597-4038-a6a3-025480bc4f17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093154877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 14.sram_ctrl_tl_intg_err.4093154877
Directory /workspace/14.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1811291340
Short name T976
Test name
Test status
Simulation time 1435288076 ps
CPU time 4.03 seconds
Started Jun 30 04:42:52 PM PDT 24
Finished Jun 30 04:42:56 PM PDT 24
Peak memory 210808 kb
Host smart-dbca5200-fb7f-4084-a7e7-cbb2f1660546
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811291340 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.1811291340
Directory /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.585709814
Short name T77
Test name
Test status
Simulation time 16708896 ps
CPU time 0.66 seconds
Started Jun 30 04:42:46 PM PDT 24
Finished Jun 30 04:42:47 PM PDT 24
Peak memory 202560 kb
Host smart-9e9e06b2-318f-440d-95bb-c069e972b944
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585709814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 15.sram_ctrl_csr_rw.585709814
Directory /workspace/15.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1653246564
Short name T100
Test name
Test status
Simulation time 3814160331 ps
CPU time 30.65 seconds
Started Jun 30 04:42:48 PM PDT 24
Finished Jun 30 04:43:19 PM PDT 24
Peak memory 202808 kb
Host smart-4e0af462-86b0-4a10-a28a-75bc8155449a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653246564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.1653246564
Directory /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3914231270
Short name T979
Test name
Test status
Simulation time 28883211 ps
CPU time 0.84 seconds
Started Jun 30 04:42:49 PM PDT 24
Finished Jun 30 04:42:50 PM PDT 24
Peak memory 202496 kb
Host smart-2dc8e8ec-18f3-4719-a746-73edb7a6ba66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914231270 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.3914231270
Directory /workspace/15.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.132731570
Short name T943
Test name
Test status
Simulation time 622096084 ps
CPU time 2.63 seconds
Started Jun 30 04:42:49 PM PDT 24
Finished Jun 30 04:42:52 PM PDT 24
Peak memory 211024 kb
Host smart-3355525b-f291-44c4-b689-3bcae5b6bad4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132731570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
15.sram_ctrl_tl_errors.132731570
Directory /workspace/15.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2552219799
Short name T127
Test name
Test status
Simulation time 97334824 ps
CPU time 1.58 seconds
Started Jun 30 04:42:47 PM PDT 24
Finished Jun 30 04:42:49 PM PDT 24
Peak memory 202820 kb
Host smart-ecc8e152-4cbc-487d-880a-59c2533deddd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552219799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 15.sram_ctrl_tl_intg_err.2552219799
Directory /workspace/15.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2983955399
Short name T1034
Test name
Test status
Simulation time 705489117 ps
CPU time 3.82 seconds
Started Jun 30 04:42:56 PM PDT 24
Finished Jun 30 04:43:00 PM PDT 24
Peak memory 210992 kb
Host smart-132acc30-ca34-4b33-86ad-d380e2c61283
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983955399 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.2983955399
Directory /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3320656499
Short name T79
Test name
Test status
Simulation time 45694519 ps
CPU time 0.69 seconds
Started Jun 30 04:42:55 PM PDT 24
Finished Jun 30 04:42:56 PM PDT 24
Peak memory 202528 kb
Host smart-b2fd2e74-d39a-4e05-add6-1f7820bf4cea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320656499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_csr_rw.3320656499
Directory /workspace/16.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2095130800
Short name T994
Test name
Test status
Simulation time 7816034518 ps
CPU time 51.05 seconds
Started Jun 30 04:42:58 PM PDT 24
Finished Jun 30 04:43:50 PM PDT 24
Peak memory 202992 kb
Host smart-d2723886-86d3-46d8-a91f-b82161a4f585
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095130800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.2095130800
Directory /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2816847538
Short name T1008
Test name
Test status
Simulation time 53356489 ps
CPU time 0.75 seconds
Started Jun 30 04:42:57 PM PDT 24
Finished Jun 30 04:42:59 PM PDT 24
Peak memory 202544 kb
Host smart-895d0939-283b-46bb-8d32-9b14c319cf22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816847538 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.2816847538
Directory /workspace/16.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2334242269
Short name T942
Test name
Test status
Simulation time 87646126 ps
CPU time 4.15 seconds
Started Jun 30 04:42:58 PM PDT 24
Finished Jun 30 04:43:03 PM PDT 24
Peak memory 202780 kb
Host smart-5629ef73-04c7-434d-822c-fc6312f1eeca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334242269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.sram_ctrl_tl_errors.2334242269
Directory /workspace/16.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1934596177
Short name T120
Test name
Test status
Simulation time 143612588 ps
CPU time 1.63 seconds
Started Jun 30 04:42:55 PM PDT 24
Finished Jun 30 04:42:57 PM PDT 24
Peak memory 210992 kb
Host smart-58eca416-c62f-4c0e-88f8-03ca957108c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934596177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 16.sram_ctrl_tl_intg_err.1934596177
Directory /workspace/16.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2608983545
Short name T966
Test name
Test status
Simulation time 370841440 ps
CPU time 4.25 seconds
Started Jun 30 04:42:55 PM PDT 24
Finished Jun 30 04:43:00 PM PDT 24
Peak memory 211340 kb
Host smart-ed0704c7-c378-4d6d-b0b9-5f9b5c69d8f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608983545 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.2608983545
Directory /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4294870024
Short name T128
Test name
Test status
Simulation time 133847189 ps
CPU time 0.72 seconds
Started Jun 30 04:42:55 PM PDT 24
Finished Jun 30 04:42:56 PM PDT 24
Peak memory 202428 kb
Host smart-5b6a4040-dbb1-43a6-84b7-f5f9c854aa80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294870024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_csr_rw.4294870024
Directory /workspace/17.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2995371530
Short name T94
Test name
Test status
Simulation time 7110130901 ps
CPU time 27.17 seconds
Started Jun 30 04:42:57 PM PDT 24
Finished Jun 30 04:43:24 PM PDT 24
Peak memory 202796 kb
Host smart-2a6c4f4e-51b5-4be3-8cc7-66004c5d1f94
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995371530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.2995371530
Directory /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3915874658
Short name T99
Test name
Test status
Simulation time 48362570 ps
CPU time 0.75 seconds
Started Jun 30 04:42:54 PM PDT 24
Finished Jun 30 04:42:56 PM PDT 24
Peak memory 202552 kb
Host smart-5e49397b-f84e-4139-b4e8-db7213a7ca11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915874658 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.3915874658
Directory /workspace/17.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1628951174
Short name T968
Test name
Test status
Simulation time 109550831 ps
CPU time 2.73 seconds
Started Jun 30 04:42:54 PM PDT 24
Finished Jun 30 04:42:57 PM PDT 24
Peak memory 202800 kb
Host smart-e771eb3e-64e1-4dcd-ac19-52a9ef82a664
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628951174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.sram_ctrl_tl_errors.1628951174
Directory /workspace/17.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.169696443
Short name T975
Test name
Test status
Simulation time 387042496 ps
CPU time 2.54 seconds
Started Jun 30 04:42:56 PM PDT 24
Finished Jun 30 04:42:59 PM PDT 24
Peak memory 202848 kb
Host smart-92305d20-0fc9-4e5d-8999-e2805feb7b58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169696443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 17.sram_ctrl_tl_intg_err.169696443
Directory /workspace/17.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2342856776
Short name T972
Test name
Test status
Simulation time 1423176513 ps
CPU time 4.14 seconds
Started Jun 30 04:42:56 PM PDT 24
Finished Jun 30 04:43:01 PM PDT 24
Peak memory 211004 kb
Host smart-87506f47-1fb3-451b-bd6b-f00be030925b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342856776 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.2342856776
Directory /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3546880768
Short name T987
Test name
Test status
Simulation time 32395857 ps
CPU time 0.71 seconds
Started Jun 30 04:42:56 PM PDT 24
Finished Jun 30 04:42:57 PM PDT 24
Peak memory 202556 kb
Host smart-034eda50-6f55-4219-bfe5-6afde389de85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546880768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_csr_rw.3546880768
Directory /workspace/18.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2173248333
Short name T85
Test name
Test status
Simulation time 28141017058 ps
CPU time 55.58 seconds
Started Jun 30 04:42:59 PM PDT 24
Finished Jun 30 04:43:55 PM PDT 24
Peak memory 203024 kb
Host smart-2541a4d8-98e7-45f9-9cfe-65a8a125fa61
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173248333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.2173248333
Directory /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3814092807
Short name T103
Test name
Test status
Simulation time 15384886 ps
CPU time 0.73 seconds
Started Jun 30 04:42:55 PM PDT 24
Finished Jun 30 04:42:56 PM PDT 24
Peak memory 202548 kb
Host smart-fe0cc7b7-5890-45e6-a6ae-69ac07671fa0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814092807 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.3814092807
Directory /workspace/18.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.267506674
Short name T971
Test name
Test status
Simulation time 489549388 ps
CPU time 5.02 seconds
Started Jun 30 04:42:57 PM PDT 24
Finished Jun 30 04:43:03 PM PDT 24
Peak memory 211008 kb
Host smart-4d89da55-ba08-48f1-b324-84acdc938986
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267506674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
18.sram_ctrl_tl_errors.267506674
Directory /workspace/18.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1751114323
Short name T980
Test name
Test status
Simulation time 733011636 ps
CPU time 2.35 seconds
Started Jun 30 04:43:00 PM PDT 24
Finished Jun 30 04:43:03 PM PDT 24
Peak memory 210976 kb
Host smart-0d06b1eb-25c5-41a4-b5e7-e0943b989954
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751114323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 18.sram_ctrl_tl_intg_err.1751114323
Directory /workspace/18.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3897082483
Short name T999
Test name
Test status
Simulation time 356876643 ps
CPU time 3.41 seconds
Started Jun 30 04:42:59 PM PDT 24
Finished Jun 30 04:43:03 PM PDT 24
Peak memory 210776 kb
Host smart-e7f2f331-5dc7-4d22-a8d5-956fd2be82a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897082483 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.3897082483
Directory /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.756424427
Short name T997
Test name
Test status
Simulation time 26607230 ps
CPU time 0.76 seconds
Started Jun 30 04:42:57 PM PDT 24
Finished Jun 30 04:42:58 PM PDT 24
Peak memory 202572 kb
Host smart-bedb3b84-d966-4dcd-ae4d-77c7265bf879
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756424427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 19.sram_ctrl_csr_rw.756424427
Directory /workspace/19.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2008308700
Short name T80
Test name
Test status
Simulation time 28167482321 ps
CPU time 56.77 seconds
Started Jun 30 04:42:57 PM PDT 24
Finished Jun 30 04:43:54 PM PDT 24
Peak memory 202976 kb
Host smart-a796d91c-5ec5-4435-8592-18f2fbcc8213
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008308700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.2008308700
Directory /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1422882928
Short name T967
Test name
Test status
Simulation time 29269773 ps
CPU time 0.72 seconds
Started Jun 30 04:42:54 PM PDT 24
Finished Jun 30 04:42:56 PM PDT 24
Peak memory 202488 kb
Host smart-bef73cba-c88e-48d0-bdac-6799aef2919b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422882928 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.1422882928
Directory /workspace/19.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.531323435
Short name T944
Test name
Test status
Simulation time 318972181 ps
CPU time 2.91 seconds
Started Jun 30 04:42:58 PM PDT 24
Finished Jun 30 04:43:02 PM PDT 24
Peak memory 210976 kb
Host smart-42c90146-635b-491d-87f9-d061e87a7763
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531323435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
19.sram_ctrl_tl_errors.531323435
Directory /workspace/19.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3527103311
Short name T957
Test name
Test status
Simulation time 656938710 ps
CPU time 2.29 seconds
Started Jun 30 04:42:58 PM PDT 24
Finished Jun 30 04:43:02 PM PDT 24
Peak memory 211048 kb
Host smart-f94adeb3-6352-4c35-8184-21be594ed582
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527103311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 19.sram_ctrl_tl_intg_err.3527103311
Directory /workspace/19.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1231796275
Short name T78
Test name
Test status
Simulation time 51549217 ps
CPU time 0.7 seconds
Started Jun 30 04:42:19 PM PDT 24
Finished Jun 30 04:42:21 PM PDT 24
Peak memory 202300 kb
Host smart-af92305f-1e28-400f-bd1c-f9c830b2433b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231796275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_aliasing.1231796275
Directory /workspace/2.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2003875980
Short name T982
Test name
Test status
Simulation time 316574483 ps
CPU time 1.47 seconds
Started Jun 30 04:42:25 PM PDT 24
Finished Jun 30 04:42:27 PM PDT 24
Peak memory 202740 kb
Host smart-4a4be375-cc76-445d-ba23-64e3de192bb0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003875980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_bit_bash.2003875980
Directory /workspace/2.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2952557871
Short name T983
Test name
Test status
Simulation time 15199385 ps
CPU time 0.68 seconds
Started Jun 30 04:42:28 PM PDT 24
Finished Jun 30 04:42:29 PM PDT 24
Peak memory 202576 kb
Host smart-5e3d8544-cff0-45e0-8c48-dca88e4ec531
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952557871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_hw_reset.2952557871
Directory /workspace/2.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1479078975
Short name T945
Test name
Test status
Simulation time 1430280523 ps
CPU time 3.93 seconds
Started Jun 30 04:42:33 PM PDT 24
Finished Jun 30 04:42:38 PM PDT 24
Peak memory 210944 kb
Host smart-ea288995-dbdf-4292-b08c-8166cabdd14c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479078975 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.1479078975
Directory /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3639461989
Short name T111
Test name
Test status
Simulation time 142430747 ps
CPU time 0.73 seconds
Started Jun 30 04:42:39 PM PDT 24
Finished Jun 30 04:42:40 PM PDT 24
Peak memory 202528 kb
Host smart-4d630d32-191d-453e-b18c-0c6996b3db9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639461989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_csr_rw.3639461989
Directory /workspace/2.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3863788934
Short name T1019
Test name
Test status
Simulation time 94062932 ps
CPU time 0.66 seconds
Started Jun 30 04:42:22 PM PDT 24
Finished Jun 30 04:42:23 PM PDT 24
Peak memory 202524 kb
Host smart-be5d9e73-18f8-4305-a372-b41d23ea9065
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863788934 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.3863788934
Directory /workspace/2.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3680525248
Short name T946
Test name
Test status
Simulation time 25260591 ps
CPU time 2.36 seconds
Started Jun 30 04:42:22 PM PDT 24
Finished Jun 30 04:42:25 PM PDT 24
Peak memory 210988 kb
Host smart-b2c2df42-8a85-488d-a1c5-c6a444943d83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680525248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.sram_ctrl_tl_errors.3680525248
Directory /workspace/2.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2038463428
Short name T991
Test name
Test status
Simulation time 298569834 ps
CPU time 1.43 seconds
Started Jun 30 04:42:31 PM PDT 24
Finished Jun 30 04:42:33 PM PDT 24
Peak memory 202792 kb
Host smart-2591a933-5d03-47ae-aba1-e0239eb957fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038463428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 2.sram_ctrl_tl_intg_err.2038463428
Directory /workspace/2.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2336963045
Short name T1038
Test name
Test status
Simulation time 34830743 ps
CPU time 0.74 seconds
Started Jun 30 04:42:21 PM PDT 24
Finished Jun 30 04:42:22 PM PDT 24
Peak memory 202560 kb
Host smart-33435d85-a537-460e-a8b8-8ebe1cc5e981
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336963045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_aliasing.2336963045
Directory /workspace/3.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1511252315
Short name T1011
Test name
Test status
Simulation time 880189483 ps
CPU time 1.44 seconds
Started Jun 30 04:42:22 PM PDT 24
Finished Jun 30 04:42:24 PM PDT 24
Peak memory 202752 kb
Host smart-74b9eed4-6adb-495c-a4c7-2c2b9cf7429c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511252315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_bit_bash.1511252315
Directory /workspace/3.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1371307654
Short name T949
Test name
Test status
Simulation time 52889781 ps
CPU time 0.65 seconds
Started Jun 30 04:42:24 PM PDT 24
Finished Jun 30 04:42:25 PM PDT 24
Peak memory 202552 kb
Host smart-b168825e-4eed-4b5c-99bf-568d69acf758
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371307654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_hw_reset.1371307654
Directory /workspace/3.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1568851294
Short name T1035
Test name
Test status
Simulation time 3371706985 ps
CPU time 4.03 seconds
Started Jun 30 04:42:31 PM PDT 24
Finished Jun 30 04:42:35 PM PDT 24
Peak memory 210628 kb
Host smart-41e5599e-f990-49df-951b-060a174111f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568851294 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.1568851294
Directory /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2567024237
Short name T1007
Test name
Test status
Simulation time 15872984 ps
CPU time 0.66 seconds
Started Jun 30 04:42:23 PM PDT 24
Finished Jun 30 04:42:24 PM PDT 24
Peak memory 202488 kb
Host smart-f3b8e681-43a5-41bd-80b5-5d3d819ece41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567024237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.sram_ctrl_csr_rw.2567024237
Directory /workspace/3.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3831273337
Short name T87
Test name
Test status
Simulation time 7298466987 ps
CPU time 51.41 seconds
Started Jun 30 04:42:18 PM PDT 24
Finished Jun 30 04:43:10 PM PDT 24
Peak memory 202988 kb
Host smart-b78d41b6-7048-411d-80f2-26df4f3674ef
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831273337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.3831273337
Directory /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1872574320
Short name T101
Test name
Test status
Simulation time 29015026 ps
CPU time 0.72 seconds
Started Jun 30 04:42:29 PM PDT 24
Finished Jun 30 04:42:31 PM PDT 24
Peak memory 202520 kb
Host smart-cb669b7b-31a9-48ba-8dc0-859144479293
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872574320 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.1872574320
Directory /workspace/3.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3427295275
Short name T1017
Test name
Test status
Simulation time 83801775 ps
CPU time 4.24 seconds
Started Jun 30 04:42:27 PM PDT 24
Finished Jun 30 04:42:32 PM PDT 24
Peak memory 202748 kb
Host smart-6fb960d8-3036-4d1f-a8c9-9e21c6c702a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427295275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.sram_ctrl_tl_errors.3427295275
Directory /workspace/3.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.636292613
Short name T961
Test name
Test status
Simulation time 19334318 ps
CPU time 0.71 seconds
Started Jun 30 04:42:35 PM PDT 24
Finished Jun 30 04:42:37 PM PDT 24
Peak memory 202588 kb
Host smart-e5f47011-3e91-4e11-8333-f571b5f961aa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636292613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.sram_ctrl_csr_aliasing.636292613
Directory /workspace/4.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3705519872
Short name T969
Test name
Test status
Simulation time 163539736 ps
CPU time 2.09 seconds
Started Jun 30 04:42:19 PM PDT 24
Finished Jun 30 04:42:22 PM PDT 24
Peak memory 202752 kb
Host smart-ba73033f-50f3-49ed-83f7-7f458d57006e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705519872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_bit_bash.3705519872
Directory /workspace/4.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3621257392
Short name T954
Test name
Test status
Simulation time 12457153 ps
CPU time 0.66 seconds
Started Jun 30 04:42:34 PM PDT 24
Finished Jun 30 04:42:36 PM PDT 24
Peak memory 202336 kb
Host smart-20cae254-25ef-458d-95a8-c4a94545318a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621257392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_hw_reset.3621257392
Directory /workspace/4.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.614722768
Short name T1005
Test name
Test status
Simulation time 2648373469 ps
CPU time 3.67 seconds
Started Jun 30 04:42:26 PM PDT 24
Finished Jun 30 04:42:31 PM PDT 24
Peak memory 210888 kb
Host smart-d740d18c-df76-4d8e-b522-3ef92adc5e7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614722768 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.614722768
Directory /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3195722687
Short name T1037
Test name
Test status
Simulation time 39487029 ps
CPU time 0.67 seconds
Started Jun 30 04:42:33 PM PDT 24
Finished Jun 30 04:42:34 PM PDT 24
Peak memory 202588 kb
Host smart-20efdb23-a5bc-44ab-931f-b3b0a484c088
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195722687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_csr_rw.3195722687
Directory /workspace/4.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3010276944
Short name T95
Test name
Test status
Simulation time 7137045300 ps
CPU time 48.44 seconds
Started Jun 30 04:42:35 PM PDT 24
Finished Jun 30 04:43:23 PM PDT 24
Peak memory 203016 kb
Host smart-2252d137-a322-4ea1-9533-09f87c98251e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010276944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.3010276944
Directory /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2048487709
Short name T1036
Test name
Test status
Simulation time 28833690 ps
CPU time 0.7 seconds
Started Jun 30 04:42:32 PM PDT 24
Finished Jun 30 04:42:33 PM PDT 24
Peak memory 202588 kb
Host smart-13e018a1-9bbe-47a2-89ed-e2c8e0626070
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048487709 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.2048487709
Directory /workspace/4.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2695993111
Short name T998
Test name
Test status
Simulation time 72463956 ps
CPU time 2.11 seconds
Started Jun 30 04:42:20 PM PDT 24
Finished Jun 30 04:42:22 PM PDT 24
Peak memory 202776 kb
Host smart-07678200-eaf7-4ba4-8d17-9a00a97ba9bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695993111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.sram_ctrl_tl_errors.2695993111
Directory /workspace/4.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3683464873
Short name T118
Test name
Test status
Simulation time 727234965 ps
CPU time 2.39 seconds
Started Jun 30 04:42:27 PM PDT 24
Finished Jun 30 04:42:30 PM PDT 24
Peak memory 210984 kb
Host smart-2c4d3176-67d2-4f54-a6a7-b45fa46364e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683464873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 4.sram_ctrl_tl_intg_err.3683464873
Directory /workspace/4.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3183566652
Short name T974
Test name
Test status
Simulation time 931929969 ps
CPU time 3.47 seconds
Started Jun 30 04:42:35 PM PDT 24
Finished Jun 30 04:42:39 PM PDT 24
Peak memory 210792 kb
Host smart-bd91d397-24b6-4710-ab36-f8ee5f411b7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183566652 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.3183566652
Directory /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.391487458
Short name T1001
Test name
Test status
Simulation time 32764095 ps
CPU time 0.68 seconds
Started Jun 30 04:42:32 PM PDT 24
Finished Jun 30 04:42:33 PM PDT 24
Peak memory 202476 kb
Host smart-b72b807a-764a-411e-85cb-2b84b2375f6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391487458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 5.sram_ctrl_csr_rw.391487458
Directory /workspace/5.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.4207726153
Short name T955
Test name
Test status
Simulation time 28421513430 ps
CPU time 36.21 seconds
Started Jun 30 04:42:34 PM PDT 24
Finished Jun 30 04:43:11 PM PDT 24
Peak memory 202760 kb
Host smart-14184f72-8f19-490e-a4a8-c820d9316094
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207726153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.4207726153
Directory /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3460145104
Short name T1013
Test name
Test status
Simulation time 46549531 ps
CPU time 0.73 seconds
Started Jun 30 04:42:30 PM PDT 24
Finished Jun 30 04:42:31 PM PDT 24
Peak memory 202560 kb
Host smart-797eaceb-8112-453e-91d3-8d3e5c76bd77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460145104 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.3460145104
Directory /workspace/5.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1557020953
Short name T1014
Test name
Test status
Simulation time 84003223 ps
CPU time 2.61 seconds
Started Jun 30 04:42:33 PM PDT 24
Finished Jun 30 04:42:36 PM PDT 24
Peak memory 210956 kb
Host smart-58cfae99-b9a4-4637-a364-c4d4a929c7b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557020953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.sram_ctrl_tl_errors.1557020953
Directory /workspace/5.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2501437750
Short name T69
Test name
Test status
Simulation time 471922551 ps
CPU time 2.41 seconds
Started Jun 30 04:42:29 PM PDT 24
Finished Jun 30 04:42:32 PM PDT 24
Peak memory 210964 kb
Host smart-83372cba-d61e-4a66-a7f0-eba102aea1ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501437750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 5.sram_ctrl_tl_intg_err.2501437750
Directory /workspace/5.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.31324593
Short name T1004
Test name
Test status
Simulation time 351375921 ps
CPU time 4.34 seconds
Started Jun 30 04:42:33 PM PDT 24
Finished Jun 30 04:42:38 PM PDT 24
Peak memory 211080 kb
Host smart-789b5a1f-f249-478f-a1a4-91ad2c32c4bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31324593 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.31324593
Directory /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3539143239
Short name T1032
Test name
Test status
Simulation time 18317693 ps
CPU time 0.74 seconds
Started Jun 30 04:42:35 PM PDT 24
Finished Jun 30 04:42:37 PM PDT 24
Peak memory 202524 kb
Host smart-2fef2362-d861-410e-add6-5eadc5c780f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539143239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 6.sram_ctrl_csr_rw.3539143239
Directory /workspace/6.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3305350464
Short name T1006
Test name
Test status
Simulation time 28438732244 ps
CPU time 51.84 seconds
Started Jun 30 04:42:32 PM PDT 24
Finished Jun 30 04:43:25 PM PDT 24
Peak memory 202964 kb
Host smart-9301a9c9-8db4-4cd4-9c0f-6ee88fe7b9c7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305350464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.3305350464
Directory /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1943307287
Short name T81
Test name
Test status
Simulation time 17807183 ps
CPU time 0.78 seconds
Started Jun 30 04:42:32 PM PDT 24
Finished Jun 30 04:42:34 PM PDT 24
Peak memory 202552 kb
Host smart-09eb81c3-d35b-4b43-a43e-e94879cd2577
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943307287 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.1943307287
Directory /workspace/6.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2993673151
Short name T965
Test name
Test status
Simulation time 172460644 ps
CPU time 2.85 seconds
Started Jun 30 04:42:30 PM PDT 24
Finished Jun 30 04:42:33 PM PDT 24
Peak memory 202792 kb
Host smart-855b4b75-f77a-4900-ad65-3b543dc06f6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993673151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.sram_ctrl_tl_errors.2993673151
Directory /workspace/6.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1898034113
Short name T992
Test name
Test status
Simulation time 261883941 ps
CPU time 2.38 seconds
Started Jun 30 04:42:34 PM PDT 24
Finished Jun 30 04:42:37 PM PDT 24
Peak memory 210796 kb
Host smart-ecc36461-47d5-4025-a7d2-f524beed669d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898034113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 6.sram_ctrl_tl_intg_err.1898034113
Directory /workspace/6.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3652334044
Short name T995
Test name
Test status
Simulation time 363693454 ps
CPU time 4.2 seconds
Started Jun 30 04:42:32 PM PDT 24
Finished Jun 30 04:42:37 PM PDT 24
Peak memory 210956 kb
Host smart-39c71c5d-d67e-4d4b-a19e-a4042dea388d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652334044 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.3652334044
Directory /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3730695125
Short name T1026
Test name
Test status
Simulation time 18484974 ps
CPU time 0.69 seconds
Started Jun 30 04:42:41 PM PDT 24
Finished Jun 30 04:42:43 PM PDT 24
Peak memory 202476 kb
Host smart-a5b1f568-4160-4423-9c0e-4ceb08eed7ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730695125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_csr_rw.3730695125
Directory /workspace/7.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1259141932
Short name T96
Test name
Test status
Simulation time 7234097057 ps
CPU time 52.54 seconds
Started Jun 30 04:42:35 PM PDT 24
Finished Jun 30 04:43:28 PM PDT 24
Peak memory 202952 kb
Host smart-e0759600-d925-4037-a8cc-4d97b6add90f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259141932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.1259141932
Directory /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1104692625
Short name T1027
Test name
Test status
Simulation time 24642702 ps
CPU time 0.78 seconds
Started Jun 30 04:42:32 PM PDT 24
Finished Jun 30 04:42:34 PM PDT 24
Peak memory 202512 kb
Host smart-f002e1b9-ec59-4864-b5aa-92a3731a9e15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104692625 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.1104692625
Directory /workspace/7.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2657557485
Short name T1016
Test name
Test status
Simulation time 48443693 ps
CPU time 3.85 seconds
Started Jun 30 04:42:28 PM PDT 24
Finished Jun 30 04:42:32 PM PDT 24
Peak memory 210992 kb
Host smart-4cf2271e-64a4-4cf8-b2f0-b9a10b859b3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657557485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.sram_ctrl_tl_errors.2657557485
Directory /workspace/7.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1777516038
Short name T119
Test name
Test status
Simulation time 122724850 ps
CPU time 1.59 seconds
Started Jun 30 04:42:27 PM PDT 24
Finished Jun 30 04:42:29 PM PDT 24
Peak memory 202820 kb
Host smart-e2275f9b-5faf-44a6-a701-348dae6c008a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777516038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 7.sram_ctrl_tl_intg_err.1777516038
Directory /workspace/7.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3273090064
Short name T1030
Test name
Test status
Simulation time 1417758205 ps
CPU time 3.37 seconds
Started Jun 30 04:42:42 PM PDT 24
Finished Jun 30 04:42:46 PM PDT 24
Peak memory 202544 kb
Host smart-7a384464-30a7-4d22-ad7c-c2757f119e58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273090064 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.3273090064
Directory /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3042038390
Short name T988
Test name
Test status
Simulation time 36542635 ps
CPU time 0.7 seconds
Started Jun 30 04:42:47 PM PDT 24
Finished Jun 30 04:42:48 PM PDT 24
Peak memory 202552 kb
Host smart-0e065a0e-1a2c-4267-96e4-2af86fe200fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042038390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_csr_rw.3042038390
Directory /workspace/8.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3860359715
Short name T83
Test name
Test status
Simulation time 7726215129 ps
CPU time 25.97 seconds
Started Jun 30 04:42:43 PM PDT 24
Finished Jun 30 04:43:10 PM PDT 24
Peak memory 202852 kb
Host smart-471584a3-5c1f-41a9-95b9-0b8957e4d451
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860359715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.3860359715
Directory /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1489227643
Short name T959
Test name
Test status
Simulation time 140946372 ps
CPU time 0.8 seconds
Started Jun 30 04:42:36 PM PDT 24
Finished Jun 30 04:42:37 PM PDT 24
Peak memory 202560 kb
Host smart-c39b4f7f-a1dd-4f28-a5d6-28858ba2cb94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489227643 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.1489227643
Directory /workspace/8.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.830136642
Short name T1023
Test name
Test status
Simulation time 37795882 ps
CPU time 2.07 seconds
Started Jun 30 04:42:36 PM PDT 24
Finished Jun 30 04:42:39 PM PDT 24
Peak memory 202020 kb
Host smart-f4d68323-5bc6-4f46-8045-7f86baf5a01f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830136642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
8.sram_ctrl_tl_errors.830136642
Directory /workspace/8.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3239213187
Short name T947
Test name
Test status
Simulation time 722907560 ps
CPU time 4.7 seconds
Started Jun 30 04:42:39 PM PDT 24
Finished Jun 30 04:42:44 PM PDT 24
Peak memory 212048 kb
Host smart-799720fb-2ec9-4f02-87d7-9ec81ebbf951
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239213187 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.3239213187
Directory /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1114527811
Short name T978
Test name
Test status
Simulation time 15802289 ps
CPU time 0.7 seconds
Started Jun 30 04:42:44 PM PDT 24
Finished Jun 30 04:42:46 PM PDT 24
Peak memory 202044 kb
Host smart-57e82c7f-677c-439c-a459-1f4f7ffcc60d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114527811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 9.sram_ctrl_csr_rw.1114527811
Directory /workspace/9.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.696770242
Short name T1003
Test name
Test status
Simulation time 15003650642 ps
CPU time 50.66 seconds
Started Jun 30 04:42:38 PM PDT 24
Finished Jun 30 04:43:29 PM PDT 24
Peak memory 202964 kb
Host smart-e10a34f8-34c7-44e7-88df-4ac9e7a91730
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696770242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.696770242
Directory /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3116886557
Short name T1025
Test name
Test status
Simulation time 26554269 ps
CPU time 0.73 seconds
Started Jun 30 04:42:43 PM PDT 24
Finished Jun 30 04:42:45 PM PDT 24
Peak memory 202552 kb
Host smart-6daad282-1d55-41d7-b42d-f54192206043
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116886557 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.3116886557
Directory /workspace/9.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1991072051
Short name T950
Test name
Test status
Simulation time 118549541 ps
CPU time 2.2 seconds
Started Jun 30 04:42:37 PM PDT 24
Finished Jun 30 04:42:40 PM PDT 24
Peak memory 202760 kb
Host smart-37914e85-8adb-4523-9144-78a988e2e371
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991072051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.sram_ctrl_tl_errors.1991072051
Directory /workspace/9.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1821569617
Short name T122
Test name
Test status
Simulation time 618110248 ps
CPU time 3.05 seconds
Started Jun 30 04:42:42 PM PDT 24
Finished Jun 30 04:42:46 PM PDT 24
Peak memory 202780 kb
Host smart-082edd70-80c6-4e68-b0bc-43fb9caa296d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821569617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 9.sram_ctrl_tl_intg_err.1821569617
Directory /workspace/9.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sram_ctrl_access_during_key_req.1657200910
Short name T274
Test name
Test status
Simulation time 8063147768 ps
CPU time 159.59 seconds
Started Jun 30 04:43:31 PM PDT 24
Finished Jun 30 04:46:11 PM PDT 24
Peak memory 372352 kb
Host smart-28034b3b-f892-4095-b6cf-930fd141bb33
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657200910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_access_during_key_req.1657200910
Directory /workspace/0.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/0.sram_ctrl_alert_test.212067117
Short name T852
Test name
Test status
Simulation time 13426693 ps
CPU time 0.67 seconds
Started Jun 30 04:43:28 PM PDT 24
Finished Jun 30 04:43:29 PM PDT 24
Peak memory 202316 kb
Host smart-7f7f608a-c261-4836-97c3-557910d20bbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212067117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_alert_test.212067117
Directory /workspace/0.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sram_ctrl_bijection.124398256
Short name T851
Test name
Test status
Simulation time 144823216049 ps
CPU time 1329.93 seconds
Started Jun 30 04:43:30 PM PDT 24
Finished Jun 30 05:05:40 PM PDT 24
Peak memory 203352 kb
Host smart-f7c28fd5-aa36-48a8-a2e6-dd0d787f3626
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124398256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.124398256
Directory /workspace/0.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/0.sram_ctrl_executable.2898917331
Short name T622
Test name
Test status
Simulation time 85174400755 ps
CPU time 1147.96 seconds
Started Jun 30 04:43:31 PM PDT 24
Finished Jun 30 05:02:40 PM PDT 24
Peak memory 380172 kb
Host smart-43d0259b-c365-4daf-abdd-95afc14c5f8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898917331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executabl
e.2898917331
Directory /workspace/0.sram_ctrl_executable/latest

Test location /workspace/coverage/default/0.sram_ctrl_lc_escalation.1266991718
Short name T280
Test name
Test status
Simulation time 3618120468 ps
CPU time 23.59 seconds
Started Jun 30 04:43:24 PM PDT 24
Finished Jun 30 04:43:49 PM PDT 24
Peak memory 214932 kb
Host smart-cb477b18-01e5-497f-82d0-f6aa0e57bc59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266991718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esc
alation.1266991718
Directory /workspace/0.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/0.sram_ctrl_max_throughput.888866190
Short name T510
Test name
Test status
Simulation time 1464382850 ps
CPU time 20.31 seconds
Started Jun 30 04:43:24 PM PDT 24
Finished Jun 30 04:43:45 PM PDT 24
Peak memory 259476 kb
Host smart-bd28b12c-e3c6-4441-baf7-fe0e3194d13b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888866190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.sram_ctrl_max_throughput.888866190
Directory /workspace/0.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_partial_access.1489978957
Short name T546
Test name
Test status
Simulation time 2735730736 ps
CPU time 64.47 seconds
Started Jun 30 04:43:42 PM PDT 24
Finished Jun 30 04:44:47 PM PDT 24
Peak memory 219020 kb
Host smart-886fcd06-29fb-45a8-a1d7-18e7ba049be0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489978957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_mem_partial_access.1489978957
Directory /workspace/0.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_walk.486731094
Short name T620
Test name
Test status
Simulation time 14388224644 ps
CPU time 158.57 seconds
Started Jun 30 04:43:29 PM PDT 24
Finished Jun 30 04:46:08 PM PDT 24
Peak memory 211680 kb
Host smart-0c9e9489-b730-4625-a01e-e10c7dbb9e99
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486731094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_
mem_walk.486731094
Directory /workspace/0.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/0.sram_ctrl_multiple_keys.3936888436
Short name T292
Test name
Test status
Simulation time 29880291366 ps
CPU time 539.93 seconds
Started Jun 30 04:43:28 PM PDT 24
Finished Jun 30 04:52:29 PM PDT 24
Peak memory 364344 kb
Host smart-e04805bf-0946-41f4-bb3c-b16c09bf3656
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936888436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip
le_keys.3936888436
Directory /workspace/0.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access.3253821992
Short name T315
Test name
Test status
Simulation time 1408347648 ps
CPU time 8.41 seconds
Started Jun 30 04:43:31 PM PDT 24
Finished Jun 30 04:43:40 PM PDT 24
Peak memory 202600 kb
Host smart-41538b03-0a5c-4bc3-8976-979576833b04
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253821992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s
ram_ctrl_partial_access.3253821992
Directory /workspace/0.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1969126901
Short name T695
Test name
Test status
Simulation time 70589498806 ps
CPU time 432.46 seconds
Started Jun 30 04:43:28 PM PDT 24
Finished Jun 30 04:50:41 PM PDT 24
Peak memory 202784 kb
Host smart-bce6fcba-38ac-4bb6-bd65-3e4bcf4b80c6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969126901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.sram_ctrl_partial_access_b2b.1969126901
Directory /workspace/0.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/0.sram_ctrl_regwen.2486622810
Short name T686
Test name
Test status
Simulation time 4068172013 ps
CPU time 1258.84 seconds
Started Jun 30 04:43:25 PM PDT 24
Finished Jun 30 05:04:25 PM PDT 24
Peak memory 381720 kb
Host smart-c5d81b7b-9ba0-4893-9ff5-b125578497d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486622810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.2486622810
Directory /workspace/0.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/0.sram_ctrl_smoke.1865374533
Short name T872
Test name
Test status
Simulation time 3634005571 ps
CPU time 20.79 seconds
Started Jun 30 04:43:24 PM PDT 24
Finished Jun 30 04:43:46 PM PDT 24
Peak memory 202724 kb
Host smart-3084f046-b2db-417f-a7ca-d840bb795d31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865374533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.1865374533
Directory /workspace/0.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all.3110562652
Short name T382
Test name
Test status
Simulation time 181510615636 ps
CPU time 3483.8 seconds
Started Jun 30 04:43:30 PM PDT 24
Finished Jun 30 05:41:34 PM PDT 24
Peak memory 378580 kb
Host smart-67f232aa-04c8-4c37-9ab3-5add3819d62d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110562652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 0.sram_ctrl_stress_all.3110562652
Directory /workspace/0.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_pipeline.2708324314
Short name T340
Test name
Test status
Simulation time 5058162408 ps
CPU time 280.99 seconds
Started Jun 30 04:43:36 PM PDT 24
Finished Jun 30 04:48:18 PM PDT 24
Peak memory 202732 kb
Host smart-107413ee-543c-41d8-8853-78a5c8c80289
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708324314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_stress_pipeline.2708324314
Directory /workspace/0.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1995814148
Short name T683
Test name
Test status
Simulation time 2872006977 ps
CPU time 33.41 seconds
Started Jun 30 04:43:26 PM PDT 24
Finished Jun 30 04:44:00 PM PDT 24
Peak memory 278372 kb
Host smart-f57953cc-52cc-47f3-8add-e3f87aec636e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995814148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.1995814148
Directory /workspace/0.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/1.sram_ctrl_access_during_key_req.1941165339
Short name T172
Test name
Test status
Simulation time 7536206875 ps
CPU time 851.13 seconds
Started Jun 30 04:43:56 PM PDT 24
Finished Jun 30 04:58:08 PM PDT 24
Peak memory 359172 kb
Host smart-4d999ef3-dd85-4eee-ac18-dad317b1a7ad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941165339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_access_during_key_req.1941165339
Directory /workspace/1.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/1.sram_ctrl_alert_test.4201592782
Short name T759
Test name
Test status
Simulation time 16077803 ps
CPU time 0.67 seconds
Started Jun 30 04:43:39 PM PDT 24
Finished Jun 30 04:43:40 PM PDT 24
Peak memory 202568 kb
Host smart-7fc19b34-1881-4c6a-b2ac-75c8522f4afa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201592782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_alert_test.4201592782
Directory /workspace/1.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sram_ctrl_bijection.2310064539
Short name T719
Test name
Test status
Simulation time 197704711731 ps
CPU time 902.41 seconds
Started Jun 30 04:43:33 PM PDT 24
Finished Jun 30 04:58:41 PM PDT 24
Peak memory 203324 kb
Host smart-e1dda37e-3a0d-43c8-b272-934a4139eda4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310064539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.
2310064539
Directory /workspace/1.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/1.sram_ctrl_executable.3858718478
Short name T130
Test name
Test status
Simulation time 10839765012 ps
CPU time 643.3 seconds
Started Jun 30 04:43:51 PM PDT 24
Finished Jun 30 04:54:35 PM PDT 24
Peak memory 343820 kb
Host smart-1301ee8f-a588-4d98-8e4f-04b48ab4c978
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858718478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executabl
e.3858718478
Directory /workspace/1.sram_ctrl_executable/latest

Test location /workspace/coverage/default/1.sram_ctrl_lc_escalation.1890027338
Short name T460
Test name
Test status
Simulation time 1442122533 ps
CPU time 10.63 seconds
Started Jun 30 04:43:40 PM PDT 24
Finished Jun 30 04:43:51 PM PDT 24
Peak memory 210828 kb
Host smart-8c3c5e7c-1b05-4283-bb1a-3b6e69d70f39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890027338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esc
alation.1890027338
Directory /workspace/1.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/1.sram_ctrl_max_throughput.1599851186
Short name T141
Test name
Test status
Simulation time 3137132127 ps
CPU time 95.86 seconds
Started Jun 30 04:43:29 PM PDT 24
Finished Jun 30 04:45:06 PM PDT 24
Peak memory 353932 kb
Host smart-bf7b26cc-ba08-4d1e-88c2-2821d4e8c739
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599851186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.sram_ctrl_max_throughput.1599851186
Directory /workspace/1.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_partial_access.4027773393
Short name T64
Test name
Test status
Simulation time 30651489753 ps
CPU time 86.3 seconds
Started Jun 30 04:43:32 PM PDT 24
Finished Jun 30 04:44:59 PM PDT 24
Peak memory 211452 kb
Host smart-beadf117-754e-4025-953f-2ede902124d1
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027773393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_mem_partial_access.4027773393
Directory /workspace/1.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_walk.4130081082
Short name T59
Test name
Test status
Simulation time 5257283004 ps
CPU time 291.87 seconds
Started Jun 30 04:43:36 PM PDT 24
Finished Jun 30 04:48:34 PM PDT 24
Peak memory 210832 kb
Host smart-f66e2ad3-d21f-4b9d-b53f-22d3dfec8025
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130081082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl
_mem_walk.4130081082
Directory /workspace/1.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/1.sram_ctrl_multiple_keys.1003858702
Short name T617
Test name
Test status
Simulation time 11737012856 ps
CPU time 653.38 seconds
Started Jun 30 04:43:24 PM PDT 24
Finished Jun 30 04:54:19 PM PDT 24
Peak memory 379940 kb
Host smart-51f651c9-6527-4fc2-87cb-f7d33d45061b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003858702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip
le_keys.1003858702
Directory /workspace/1.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access.2400295829
Short name T167
Test name
Test status
Simulation time 1782860871 ps
CPU time 34.22 seconds
Started Jun 30 04:43:30 PM PDT 24
Finished Jun 30 04:44:05 PM PDT 24
Peak memory 291860 kb
Host smart-68f5edea-4ff7-443f-8d2b-5996cbc2f85a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400295829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s
ram_ctrl_partial_access.2400295829
Directory /workspace/1.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1643250962
Short name T348
Test name
Test status
Simulation time 91973591565 ps
CPU time 639.45 seconds
Started Jun 30 04:43:24 PM PDT 24
Finished Jun 30 04:54:05 PM PDT 24
Peak memory 202692 kb
Host smart-51c60f56-9606-4a4e-b806-208bec01c89e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643250962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.sram_ctrl_partial_access_b2b.1643250962
Directory /workspace/1.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/1.sram_ctrl_ram_cfg.241232307
Short name T383
Test name
Test status
Simulation time 1493138452 ps
CPU time 3.35 seconds
Started Jun 30 04:43:40 PM PDT 24
Finished Jun 30 04:43:49 PM PDT 24
Peak memory 202768 kb
Host smart-2d74d4f9-6caf-48e1-9f95-3a57657ff8d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241232307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.241232307
Directory /workspace/1.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/1.sram_ctrl_regwen.1358729385
Short name T24
Test name
Test status
Simulation time 3847094355 ps
CPU time 380.83 seconds
Started Jun 30 04:43:40 PM PDT 24
Finished Jun 30 04:50:02 PM PDT 24
Peak memory 350996 kb
Host smart-3a6e36d0-c291-4778-9e63-23d9b489a8d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358729385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.1358729385
Directory /workspace/1.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/1.sram_ctrl_sec_cm.3842148179
Short name T28
Test name
Test status
Simulation time 860232706 ps
CPU time 3.02 seconds
Started Jun 30 04:43:36 PM PDT 24
Finished Jun 30 04:43:40 PM PDT 24
Peak memory 222152 kb
Host smart-bf58fe0a-e55b-4c8e-8ae4-93dcc82a2d6c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842148179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_sec_cm.3842148179
Directory /workspace/1.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sram_ctrl_smoke.3995645212
Short name T346
Test name
Test status
Simulation time 1694155956 ps
CPU time 100.52 seconds
Started Jun 30 04:43:33 PM PDT 24
Finished Jun 30 04:45:14 PM PDT 24
Peak memory 345740 kb
Host smart-96c0f371-1a8e-4edc-996a-a7b86ba911dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995645212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.3995645212
Directory /workspace/1.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all.3876058047
Short name T807
Test name
Test status
Simulation time 270589095675 ps
CPU time 5413.2 seconds
Started Jun 30 04:43:42 PM PDT 24
Finished Jun 30 06:13:56 PM PDT 24
Peak memory 380676 kb
Host smart-bd3080e5-d7b6-499f-bde5-17a016a8fdb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876058047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.sram_ctrl_stress_all.3876058047
Directory /workspace/1.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2266740579
Short name T498
Test name
Test status
Simulation time 1532727279 ps
CPU time 71.46 seconds
Started Jun 30 04:43:54 PM PDT 24
Finished Jun 30 04:45:06 PM PDT 24
Peak memory 210980 kb
Host smart-f07f6d2f-51a7-4361-8190-aa2173258f9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2266740579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.2266740579
Directory /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_pipeline.1248770616
Short name T286
Test name
Test status
Simulation time 8743746273 ps
CPU time 339.56 seconds
Started Jun 30 04:43:25 PM PDT 24
Finished Jun 30 04:49:05 PM PDT 24
Peak memory 202720 kb
Host smart-52314c9c-e966-4001-af97-1210ff86ed8e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248770616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_stress_pipeline.1248770616
Directory /workspace/1.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3742467110
Short name T760
Test name
Test status
Simulation time 801885588 ps
CPU time 105.16 seconds
Started Jun 30 04:43:28 PM PDT 24
Finished Jun 30 04:45:14 PM PDT 24
Peak memory 349788 kb
Host smart-527cd260-b7b1-4cbf-995b-42281e269284
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742467110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.sram_ctrl_throughput_w_partial_write.3742467110
Directory /workspace/1.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/10.sram_ctrl_access_during_key_req.896814185
Short name T486
Test name
Test status
Simulation time 32815647879 ps
CPU time 1319.56 seconds
Started Jun 30 04:43:52 PM PDT 24
Finished Jun 30 05:05:53 PM PDT 24
Peak memory 372504 kb
Host smart-443f3596-2a70-4f95-8781-548386b58698
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896814185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 10.sram_ctrl_access_during_key_req.896814185
Directory /workspace/10.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/10.sram_ctrl_alert_test.3442499613
Short name T581
Test name
Test status
Simulation time 82533996 ps
CPU time 0.67 seconds
Started Jun 30 04:43:49 PM PDT 24
Finished Jun 30 04:43:51 PM PDT 24
Peak memory 202264 kb
Host smart-d057eed1-db00-496c-ab5c-342b803b543d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442499613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.sram_ctrl_alert_test.3442499613
Directory /workspace/10.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sram_ctrl_bijection.656866450
Short name T770
Test name
Test status
Simulation time 411711662989 ps
CPU time 1382.64 seconds
Started Jun 30 04:43:57 PM PDT 24
Finished Jun 30 05:07:00 PM PDT 24
Peak memory 202848 kb
Host smart-092bd861-9334-4dab-9e29-d1ec44111217
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656866450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection.
656866450
Directory /workspace/10.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/10.sram_ctrl_executable.3442561603
Short name T213
Test name
Test status
Simulation time 13091573901 ps
CPU time 1892.42 seconds
Started Jun 30 04:43:51 PM PDT 24
Finished Jun 30 05:15:25 PM PDT 24
Peak memory 381700 kb
Host smart-3fabb3a3-8a92-40b6-9e25-a8a3ff2528d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442561603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executab
le.3442561603
Directory /workspace/10.sram_ctrl_executable/latest

Test location /workspace/coverage/default/10.sram_ctrl_lc_escalation.1835062141
Short name T464
Test name
Test status
Simulation time 37057267341 ps
CPU time 78.76 seconds
Started Jun 30 04:43:57 PM PDT 24
Finished Jun 30 04:45:17 PM PDT 24
Peak memory 202776 kb
Host smart-27eb11dd-03cd-44bc-8e6d-966bb90e5fea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835062141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es
calation.1835062141
Directory /workspace/10.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/10.sram_ctrl_max_throughput.1054354642
Short name T638
Test name
Test status
Simulation time 716654688 ps
CPU time 25.95 seconds
Started Jun 30 04:43:53 PM PDT 24
Finished Jun 30 04:44:19 PM PDT 24
Peak memory 275580 kb
Host smart-a7f1d170-e8ef-4a73-b0a0-f3d8134d0c32
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054354642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.sram_ctrl_max_throughput.1054354642
Directory /workspace/10.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_partial_access.1080439451
Short name T284
Test name
Test status
Simulation time 20396413715 ps
CPU time 163.8 seconds
Started Jun 30 04:43:57 PM PDT 24
Finished Jun 30 04:46:47 PM PDT 24
Peak memory 210928 kb
Host smart-38201a19-aa86-479f-8b62-5ebffe336deb
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080439451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_mem_partial_access.1080439451
Directory /workspace/10.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_walk.824680924
Short name T424
Test name
Test status
Simulation time 8084568218 ps
CPU time 307.25 seconds
Started Jun 30 04:43:52 PM PDT 24
Finished Jun 30 04:49:05 PM PDT 24
Peak memory 210908 kb
Host smart-fd6442ad-29b1-4860-98cc-3f360d3074a4
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824680924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl
_mem_walk.824680924
Directory /workspace/10.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/10.sram_ctrl_multiple_keys.1561573163
Short name T10
Test name
Test status
Simulation time 46202339185 ps
CPU time 970.81 seconds
Started Jun 30 04:43:51 PM PDT 24
Finished Jun 30 05:00:03 PM PDT 24
Peak memory 360428 kb
Host smart-15b0ae4b-caee-4418-b162-588ef880c35d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561573163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi
ple_keys.1561573163
Directory /workspace/10.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access.3340002351
Short name T151
Test name
Test status
Simulation time 5344543592 ps
CPU time 21.19 seconds
Started Jun 30 04:44:03 PM PDT 24
Finished Jun 30 04:44:26 PM PDT 24
Peak memory 202672 kb
Host smart-7a4ecb43-5a4f-4f60-987c-c71a32afb555
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340002351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
sram_ctrl_partial_access.3340002351
Directory /workspace/10.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.4069001895
Short name T671
Test name
Test status
Simulation time 40967306858 ps
CPU time 513.2 seconds
Started Jun 30 04:44:01 PM PDT 24
Finished Jun 30 04:52:35 PM PDT 24
Peak memory 202700 kb
Host smart-b54a9c22-e731-42e5-a6d9-affd0dd710b0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069001895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 10.sram_ctrl_partial_access_b2b.4069001895
Directory /workspace/10.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/10.sram_ctrl_ram_cfg.1983674688
Short name T557
Test name
Test status
Simulation time 918398107 ps
CPU time 3.34 seconds
Started Jun 30 04:43:53 PM PDT 24
Finished Jun 30 04:43:57 PM PDT 24
Peak memory 202668 kb
Host smart-840332ea-c054-43a4-9f6c-d3ed4f708a2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983674688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.1983674688
Directory /workspace/10.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/10.sram_ctrl_regwen.1778904776
Short name T197
Test name
Test status
Simulation time 6836273399 ps
CPU time 1097.31 seconds
Started Jun 30 04:44:03 PM PDT 24
Finished Jun 30 05:02:22 PM PDT 24
Peak memory 380656 kb
Host smart-e433e38c-13d8-4218-919f-e8225c17ea59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778904776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.1778904776
Directory /workspace/10.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/10.sram_ctrl_smoke.1166399554
Short name T927
Test name
Test status
Simulation time 12246198704 ps
CPU time 60.3 seconds
Started Jun 30 04:44:00 PM PDT 24
Finished Jun 30 04:45:02 PM PDT 24
Peak memory 326480 kb
Host smart-fe95a6e1-4882-4578-b4e7-2a482388be6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166399554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.1166399554
Directory /workspace/10.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all.2202199155
Short name T132
Test name
Test status
Simulation time 105155755830 ps
CPU time 3537.16 seconds
Started Jun 30 04:43:54 PM PDT 24
Finished Jun 30 05:42:53 PM PDT 24
Peak memory 381768 kb
Host smart-1f5deea3-3b79-47f9-a988-545e83fbc21d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202199155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 10.sram_ctrl_stress_all.2202199155
Directory /workspace/10.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2214916072
Short name T878
Test name
Test status
Simulation time 156592712 ps
CPU time 5.96 seconds
Started Jun 30 04:43:56 PM PDT 24
Finished Jun 30 04:44:03 PM PDT 24
Peak memory 210912 kb
Host smart-024b891c-e77c-4930-859d-0f9a71fb4e7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2214916072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.2214916072
Directory /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_pipeline.924449358
Short name T833
Test name
Test status
Simulation time 9511420553 ps
CPU time 148.69 seconds
Started Jun 30 04:43:57 PM PDT 24
Finished Jun 30 04:46:26 PM PDT 24
Peak memory 202672 kb
Host smart-77f5806e-0cdc-47fb-80f3-efe492116a14
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924449358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.sram_ctrl_stress_pipeline.924449358
Directory /workspace/10.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3225394159
Short name T229
Test name
Test status
Simulation time 2770943180 ps
CPU time 6.78 seconds
Started Jun 30 04:44:07 PM PDT 24
Finished Jun 30 04:44:15 PM PDT 24
Peak memory 210772 kb
Host smart-354fcb71-2505-435e-95ae-28d4d8702a88
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225394159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.3225394159
Directory /workspace/10.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/11.sram_ctrl_access_during_key_req.789221027
Short name T754
Test name
Test status
Simulation time 15370867999 ps
CPU time 1130.83 seconds
Started Jun 30 04:43:58 PM PDT 24
Finished Jun 30 05:02:49 PM PDT 24
Peak memory 379620 kb
Host smart-76052e0f-136e-4988-ba3e-fe6847f60db0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789221027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 11.sram_ctrl_access_during_key_req.789221027
Directory /workspace/11.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/11.sram_ctrl_alert_test.584020897
Short name T813
Test name
Test status
Simulation time 15707244 ps
CPU time 0.69 seconds
Started Jun 30 04:44:01 PM PDT 24
Finished Jun 30 04:44:03 PM PDT 24
Peak memory 202608 kb
Host smart-9cabc5b9-4483-4d79-9d05-ad4b8f30ef63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584020897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.sram_ctrl_alert_test.584020897
Directory /workspace/11.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sram_ctrl_bijection.987545107
Short name T137
Test name
Test status
Simulation time 158918197642 ps
CPU time 1502.05 seconds
Started Jun 30 04:43:58 PM PDT 24
Finished Jun 30 05:09:02 PM PDT 24
Peak memory 203444 kb
Host smart-719b3148-d013-4721-bf3d-fc6632050a6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987545107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection.
987545107
Directory /workspace/11.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/11.sram_ctrl_executable.1299180669
Short name T435
Test name
Test status
Simulation time 2789827809 ps
CPU time 376.04 seconds
Started Jun 30 04:43:59 PM PDT 24
Finished Jun 30 04:50:16 PM PDT 24
Peak memory 363188 kb
Host smart-921a84d8-d856-4113-981c-b70a858ca773
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299180669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executab
le.1299180669
Directory /workspace/11.sram_ctrl_executable/latest

Test location /workspace/coverage/default/11.sram_ctrl_lc_escalation.2172551498
Short name T810
Test name
Test status
Simulation time 23111393253 ps
CPU time 44.77 seconds
Started Jun 30 04:43:59 PM PDT 24
Finished Jun 30 04:44:44 PM PDT 24
Peak memory 210956 kb
Host smart-292750ef-5941-4e21-b459-43c299bee705
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172551498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_es
calation.2172551498
Directory /workspace/11.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/11.sram_ctrl_max_throughput.1582867949
Short name T450
Test name
Test status
Simulation time 2741729121 ps
CPU time 12.6 seconds
Started Jun 30 04:44:15 PM PDT 24
Finished Jun 30 04:44:28 PM PDT 24
Peak memory 235424 kb
Host smart-6bbd3739-1e18-4923-b16e-536dd1d23c8e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582867949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.sram_ctrl_max_throughput.1582867949
Directory /workspace/11.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_partial_access.1870790053
Short name T365
Test name
Test status
Simulation time 8703828308 ps
CPU time 66.29 seconds
Started Jun 30 04:44:07 PM PDT 24
Finished Jun 30 04:45:15 PM PDT 24
Peak memory 213340 kb
Host smart-d76da1a6-2b7f-416e-bc5f-528d861a22cc
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870790053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_mem_partial_access.1870790053
Directory /workspace/11.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_walk.1385154559
Short name T328
Test name
Test status
Simulation time 2745774493 ps
CPU time 154.32 seconds
Started Jun 30 04:44:08 PM PDT 24
Finished Jun 30 04:46:43 PM PDT 24
Peak memory 210824 kb
Host smart-b1d160c5-2264-44da-8c85-378992fb0037
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385154559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctr
l_mem_walk.1385154559
Directory /workspace/11.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/11.sram_ctrl_multiple_keys.1967978112
Short name T322
Test name
Test status
Simulation time 40366784682 ps
CPU time 1451.76 seconds
Started Jun 30 04:43:44 PM PDT 24
Finished Jun 30 05:07:57 PM PDT 24
Peak memory 375524 kb
Host smart-2f981ed2-9356-4334-80b2-9e86f801d61f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967978112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi
ple_keys.1967978112
Directory /workspace/11.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access.2617304766
Short name T217
Test name
Test status
Simulation time 1293045841 ps
CPU time 9.89 seconds
Started Jun 30 04:43:57 PM PDT 24
Finished Jun 30 04:44:08 PM PDT 24
Peak memory 202584 kb
Host smart-3abdf506-3999-4806-a5ad-bcdc679def20
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617304766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
sram_ctrl_partial_access.2617304766
Directory /workspace/11.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.4005258972
Short name T311
Test name
Test status
Simulation time 54777673768 ps
CPU time 333.72 seconds
Started Jun 30 04:43:48 PM PDT 24
Finished Jun 30 04:49:24 PM PDT 24
Peak memory 202760 kb
Host smart-caded15a-329e-4793-8ee9-0c527d30b97b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005258972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 11.sram_ctrl_partial_access_b2b.4005258972
Directory /workspace/11.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/11.sram_ctrl_ram_cfg.1308708990
Short name T35
Test name
Test status
Simulation time 362641012 ps
CPU time 3.4 seconds
Started Jun 30 04:44:10 PM PDT 24
Finished Jun 30 04:44:15 PM PDT 24
Peak memory 202632 kb
Host smart-c449ab32-23c2-4279-b398-147dd23fa42e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308708990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.1308708990
Directory /workspace/11.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/11.sram_ctrl_smoke.1126602481
Short name T366
Test name
Test status
Simulation time 794638799 ps
CPU time 56.27 seconds
Started Jun 30 04:44:09 PM PDT 24
Finished Jun 30 04:45:05 PM PDT 24
Peak memory 315316 kb
Host smart-3e08309d-38b0-4b44-b101-500d305e422a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126602481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.1126602481
Directory /workspace/11.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all.1602861422
Short name T437
Test name
Test status
Simulation time 319953200776 ps
CPU time 3995.72 seconds
Started Jun 30 04:44:14 PM PDT 24
Finished Jun 30 05:50:51 PM PDT 24
Peak memory 383736 kb
Host smart-3b3afea6-e6c3-4156-a73a-e84215dff779
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602861422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.sram_ctrl_stress_all.1602861422
Directory /workspace/11.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2743946752
Short name T75
Test name
Test status
Simulation time 891036137 ps
CPU time 8.01 seconds
Started Jun 30 04:44:01 PM PDT 24
Finished Jun 30 04:44:10 PM PDT 24
Peak memory 212940 kb
Host smart-812e18d9-2d1a-4827-b363-545100714e58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2743946752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.2743946752
Directory /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_pipeline.687737467
Short name T595
Test name
Test status
Simulation time 17160155588 ps
CPU time 213.41 seconds
Started Jun 30 04:43:57 PM PDT 24
Finished Jun 30 04:47:31 PM PDT 24
Peak memory 202724 kb
Host smart-f76fb20f-a75b-4dcc-845a-c0cae71a7a64
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687737467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.sram_ctrl_stress_pipeline.687737467
Directory /workspace/11.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3241704998
Short name T829
Test name
Test status
Simulation time 1486935308 ps
CPU time 21.61 seconds
Started Jun 30 04:43:54 PM PDT 24
Finished Jun 30 04:44:16 PM PDT 24
Peak memory 268020 kb
Host smart-f3ed92a7-eb62-4dd5-a786-30f0fb9c9aab
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241704998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.3241704998
Directory /workspace/11.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/12.sram_ctrl_access_during_key_req.1473672958
Short name T482
Test name
Test status
Simulation time 1397432758 ps
CPU time 28.12 seconds
Started Jun 30 04:43:57 PM PDT 24
Finished Jun 30 04:44:26 PM PDT 24
Peak memory 204632 kb
Host smart-3c5c6dc6-05f1-41ad-aaf0-5cbce57a992e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473672958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_access_during_key_req.1473672958
Directory /workspace/12.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/12.sram_ctrl_alert_test.3126759280
Short name T609
Test name
Test status
Simulation time 20521899 ps
CPU time 0.67 seconds
Started Jun 30 04:44:04 PM PDT 24
Finished Jun 30 04:44:07 PM PDT 24
Peak memory 202424 kb
Host smart-2ea29f60-5bf6-4c98-973a-5afc66cfcd46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126759280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.sram_ctrl_alert_test.3126759280
Directory /workspace/12.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sram_ctrl_bijection.1332627797
Short name T523
Test name
Test status
Simulation time 8553283646 ps
CPU time 581.65 seconds
Started Jun 30 04:44:13 PM PDT 24
Finished Jun 30 04:53:56 PM PDT 24
Peak memory 203504 kb
Host smart-23bafbc7-70aa-4237-95bb-1f5e1d278da2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332627797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection
.1332627797
Directory /workspace/12.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/12.sram_ctrl_executable.3176632441
Short name T316
Test name
Test status
Simulation time 49415355796 ps
CPU time 1230.72 seconds
Started Jun 30 04:44:11 PM PDT 24
Finished Jun 30 05:04:43 PM PDT 24
Peak memory 379648 kb
Host smart-12a6d2cb-4135-4bfa-9f56-bdafa6875f02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176632441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executab
le.3176632441
Directory /workspace/12.sram_ctrl_executable/latest

Test location /workspace/coverage/default/12.sram_ctrl_lc_escalation.2438511136
Short name T258
Test name
Test status
Simulation time 3893196891 ps
CPU time 24.27 seconds
Started Jun 30 04:44:03 PM PDT 24
Finished Jun 30 04:44:30 PM PDT 24
Peak memory 202784 kb
Host smart-9441b39d-3282-4ee2-a52e-b4a2c7db0e16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438511136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es
calation.2438511136
Directory /workspace/12.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/12.sram_ctrl_max_throughput.2164030921
Short name T847
Test name
Test status
Simulation time 790890757 ps
CPU time 101.73 seconds
Started Jun 30 04:44:13 PM PDT 24
Finished Jun 30 04:45:56 PM PDT 24
Peak memory 363128 kb
Host smart-b943c8c3-9e9f-4052-996e-37a38ed10f13
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164030921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.sram_ctrl_max_throughput.2164030921
Directory /workspace/12.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_partial_access.1843849505
Short name T93
Test name
Test status
Simulation time 23160355882 ps
CPU time 194.77 seconds
Started Jun 30 04:44:06 PM PDT 24
Finished Jun 30 04:47:22 PM PDT 24
Peak memory 210916 kb
Host smart-f9396c83-4d59-4388-b4cf-34cf92a08520
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843849505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_mem_partial_access.1843849505
Directory /workspace/12.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_walk.1071250542
Short name T556
Test name
Test status
Simulation time 28846995459 ps
CPU time 158.02 seconds
Started Jun 30 04:44:05 PM PDT 24
Finished Jun 30 04:46:45 PM PDT 24
Peak memory 210832 kb
Host smart-fdf39115-4ecf-4a1d-9892-a2dce1599196
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071250542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr
l_mem_walk.1071250542
Directory /workspace/12.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/12.sram_ctrl_multiple_keys.2258513617
Short name T391
Test name
Test status
Simulation time 15773633475 ps
CPU time 588.71 seconds
Started Jun 30 04:44:02 PM PDT 24
Finished Jun 30 04:53:52 PM PDT 24
Peak memory 375768 kb
Host smart-0a917b86-dfdb-4cc6-9a5f-4ed16e2fd823
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258513617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi
ple_keys.2258513617
Directory /workspace/12.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access.2647572339
Short name T369
Test name
Test status
Simulation time 1019455105 ps
CPU time 99.77 seconds
Started Jun 30 04:44:03 PM PDT 24
Finished Jun 30 04:45:44 PM PDT 24
Peak memory 361056 kb
Host smart-b0ad5913-0c00-4896-9e93-41c646a7478c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647572339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
sram_ctrl_partial_access.2647572339
Directory /workspace/12.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.242088197
Short name T248
Test name
Test status
Simulation time 14743026669 ps
CPU time 343.81 seconds
Started Jun 30 04:44:12 PM PDT 24
Finished Jun 30 04:49:57 PM PDT 24
Peak memory 202700 kb
Host smart-97c3da97-33aa-412b-aca9-b33e6d919b8c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242088197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.sram_ctrl_partial_access_b2b.242088197
Directory /workspace/12.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/12.sram_ctrl_ram_cfg.3214721143
Short name T26
Test name
Test status
Simulation time 1349833202 ps
CPU time 3.4 seconds
Started Jun 30 04:43:58 PM PDT 24
Finished Jun 30 04:44:02 PM PDT 24
Peak memory 202636 kb
Host smart-03321592-7cf6-4512-a37d-46e97983dfd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214721143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.3214721143
Directory /workspace/12.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/12.sram_ctrl_regwen.1593163101
Short name T218
Test name
Test status
Simulation time 48428119559 ps
CPU time 774.62 seconds
Started Jun 30 04:44:03 PM PDT 24
Finished Jun 30 04:57:00 PM PDT 24
Peak memory 372084 kb
Host smart-f13f2620-fc6a-40d9-8d32-ccbb4f1310fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593163101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.1593163101
Directory /workspace/12.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/12.sram_ctrl_smoke.3639533684
Short name T698
Test name
Test status
Simulation time 783087929 ps
CPU time 98.71 seconds
Started Jun 30 04:43:50 PM PDT 24
Finished Jun 30 04:45:30 PM PDT 24
Peak memory 341676 kb
Host smart-7aa1384e-9b16-40b9-9f81-528d7505bc6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639533684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.3639533684
Directory /workspace/12.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2375129894
Short name T412
Test name
Test status
Simulation time 11501666970 ps
CPU time 169.06 seconds
Started Jun 30 04:44:05 PM PDT 24
Finished Jun 30 04:46:56 PM PDT 24
Peak memory 327604 kb
Host smart-0d9ea8b1-ab53-45ec-91c3-a3bbf6fab077
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2375129894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.2375129894
Directory /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2158900610
Short name T889
Test name
Test status
Simulation time 5596735152 ps
CPU time 121.53 seconds
Started Jun 30 04:44:09 PM PDT 24
Finished Jun 30 04:46:11 PM PDT 24
Peak memory 370896 kb
Host smart-9f40af48-a512-48e7-8e70-8eeb883c082e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158900610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.2158900610
Directory /workspace/12.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/13.sram_ctrl_access_during_key_req.2355206261
Short name T559
Test name
Test status
Simulation time 26289371245 ps
CPU time 630.78 seconds
Started Jun 30 04:44:03 PM PDT 24
Finished Jun 30 04:54:36 PM PDT 24
Peak memory 378948 kb
Host smart-9913d5d0-d344-4c16-b720-0159b8bdb4df
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355206261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_access_during_key_req.2355206261
Directory /workspace/13.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/13.sram_ctrl_alert_test.775131183
Short name T781
Test name
Test status
Simulation time 21975821 ps
CPU time 0.69 seconds
Started Jun 30 04:44:02 PM PDT 24
Finished Jun 30 04:44:04 PM PDT 24
Peak memory 202264 kb
Host smart-d7dfe7f7-ef99-410c-90d1-8637eb5ec1f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775131183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.sram_ctrl_alert_test.775131183
Directory /workspace/13.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sram_ctrl_bijection.79197736
Short name T271
Test name
Test status
Simulation time 130335269418 ps
CPU time 1933.62 seconds
Started Jun 30 04:44:00 PM PDT 24
Finished Jun 30 05:16:15 PM PDT 24
Peak memory 203344 kb
Host smart-0dbf009a-d532-4571-9a7b-68482f178b94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79197736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject
ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection.79197736
Directory /workspace/13.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/13.sram_ctrl_executable.2492168122
Short name T193
Test name
Test status
Simulation time 38696491154 ps
CPU time 407.86 seconds
Started Jun 30 04:44:06 PM PDT 24
Finished Jun 30 04:50:55 PM PDT 24
Peak memory 345824 kb
Host smart-e7368b13-9c52-4011-a6d4-db1f70345fb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492168122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executab
le.2492168122
Directory /workspace/13.sram_ctrl_executable/latest

Test location /workspace/coverage/default/13.sram_ctrl_lc_escalation.2815199880
Short name T117
Test name
Test status
Simulation time 18013504844 ps
CPU time 33.07 seconds
Started Jun 30 04:44:05 PM PDT 24
Finished Jun 30 04:44:40 PM PDT 24
Peak memory 202756 kb
Host smart-fb6f1cfe-2d08-48fc-b84f-80e8eb4149b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815199880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es
calation.2815199880
Directory /workspace/13.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/13.sram_ctrl_max_throughput.161029431
Short name T445
Test name
Test status
Simulation time 3513329448 ps
CPU time 147.6 seconds
Started Jun 30 04:44:04 PM PDT 24
Finished Jun 30 04:46:34 PM PDT 24
Peak memory 370992 kb
Host smart-049f0175-21f9-47ae-9178-5a1ad5a910a0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161029431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.sram_ctrl_max_throughput.161029431
Directory /workspace/13.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_partial_access.3997233994
Short name T522
Test name
Test status
Simulation time 20102106520 ps
CPU time 164.98 seconds
Started Jun 30 04:43:59 PM PDT 24
Finished Jun 30 04:46:45 PM PDT 24
Peak memory 210900 kb
Host smart-ef537f48-2ac8-43b1-8cd7-0878e87139e6
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997233994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_mem_partial_access.3997233994
Directory /workspace/13.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_walk.4173800619
Short name T939
Test name
Test status
Simulation time 5269087679 ps
CPU time 149.4 seconds
Started Jun 30 04:44:02 PM PDT 24
Finished Jun 30 04:46:33 PM PDT 24
Peak memory 210952 kb
Host smart-7a8aab24-d22e-4ac4-ba25-b6f59070e9bb
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173800619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctr
l_mem_walk.4173800619
Directory /workspace/13.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/13.sram_ctrl_multiple_keys.3633323186
Short name T411
Test name
Test status
Simulation time 56621104089 ps
CPU time 789.93 seconds
Started Jun 30 04:44:21 PM PDT 24
Finished Jun 30 04:57:32 PM PDT 24
Peak memory 376720 kb
Host smart-4d3c3ec6-ce37-4c71-bc73-659db03c2835
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633323186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multi
ple_keys.3633323186
Directory /workspace/13.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access.1328386077
Short name T606
Test name
Test status
Simulation time 3249974776 ps
CPU time 18.17 seconds
Started Jun 30 04:44:05 PM PDT 24
Finished Jun 30 04:44:29 PM PDT 24
Peak memory 246588 kb
Host smart-b4d1207b-851d-4c97-b4ca-5656d29b2b64
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328386077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
sram_ctrl_partial_access.1328386077
Directory /workspace/13.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.4071076039
Short name T301
Test name
Test status
Simulation time 59650640880 ps
CPU time 383.31 seconds
Started Jun 30 04:44:07 PM PDT 24
Finished Jun 30 04:50:32 PM PDT 24
Peak memory 202676 kb
Host smart-f276486f-a9db-4c25-a77c-940fa0c22b25
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071076039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 13.sram_ctrl_partial_access_b2b.4071076039
Directory /workspace/13.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/13.sram_ctrl_ram_cfg.2792195607
Short name T805
Test name
Test status
Simulation time 803903623 ps
CPU time 3.36 seconds
Started Jun 30 04:44:07 PM PDT 24
Finished Jun 30 04:44:11 PM PDT 24
Peak memory 202668 kb
Host smart-0aeae1cf-d854-4e65-8d81-3a97e991db21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792195607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.2792195607
Directory /workspace/13.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/13.sram_ctrl_regwen.2261320327
Short name T817
Test name
Test status
Simulation time 11773065779 ps
CPU time 1146.34 seconds
Started Jun 30 04:44:02 PM PDT 24
Finished Jun 30 05:03:10 PM PDT 24
Peak memory 374524 kb
Host smart-775c61f1-2fdb-4aa8-9a8e-d0f47cb63642
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261320327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.2261320327
Directory /workspace/13.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/13.sram_ctrl_smoke.1370909222
Short name T752
Test name
Test status
Simulation time 3215221945 ps
CPU time 21.8 seconds
Started Jun 30 04:44:06 PM PDT 24
Finished Jun 30 04:44:29 PM PDT 24
Peak memory 203096 kb
Host smart-a51e0572-6b3f-4cfd-b11e-4ca91516ea60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370909222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.1370909222
Directory /workspace/13.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all.3863285695
Short name T692
Test name
Test status
Simulation time 211888445265 ps
CPU time 5099.37 seconds
Started Jun 30 04:44:15 PM PDT 24
Finished Jun 30 06:09:15 PM PDT 24
Peak memory 387952 kb
Host smart-b6ca904b-b1d4-46fa-a1cf-2c9ca32e1a2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863285695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.sram_ctrl_stress_all.3863285695
Directory /workspace/13.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2243306690
Short name T914
Test name
Test status
Simulation time 424258423 ps
CPU time 15.32 seconds
Started Jun 30 04:43:59 PM PDT 24
Finished Jun 30 04:44:15 PM PDT 24
Peak memory 210888 kb
Host smart-eca24e96-1376-4cbb-8938-22f14dd8b68d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2243306690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.2243306690
Directory /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_pipeline.1801815919
Short name T838
Test name
Test status
Simulation time 4554902407 ps
CPU time 340.97 seconds
Started Jun 30 04:44:03 PM PDT 24
Finished Jun 30 04:49:45 PM PDT 24
Peak memory 202772 kb
Host smart-ed2cface-ab75-47e3-8c30-1874dab94887
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801815919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_stress_pipeline.1801815919
Directory /workspace/13.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3811590187
Short name T434
Test name
Test status
Simulation time 723417996 ps
CPU time 12.03 seconds
Started Jun 30 04:44:04 PM PDT 24
Finished Jun 30 04:44:19 PM PDT 24
Peak memory 235332 kb
Host smart-9c1a2315-12a0-4729-80ff-1aa16b0365bb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811590187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.3811590187
Directory /workspace/13.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/14.sram_ctrl_access_during_key_req.1163112371
Short name T381
Test name
Test status
Simulation time 64627930858 ps
CPU time 1263.34 seconds
Started Jun 30 04:44:04 PM PDT 24
Finished Jun 30 05:05:10 PM PDT 24
Peak memory 375556 kb
Host smart-0fda4be8-2854-4a89-93c7-c8fbe18c6547
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163112371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_access_during_key_req.1163112371
Directory /workspace/14.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/14.sram_ctrl_bijection.3305755963
Short name T195
Test name
Test status
Simulation time 254669678220 ps
CPU time 2343.38 seconds
Started Jun 30 04:44:00 PM PDT 24
Finished Jun 30 05:23:05 PM PDT 24
Peak memory 203272 kb
Host smart-4e369a18-0c07-473b-a00e-65011a57e630
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305755963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection
.3305755963
Directory /workspace/14.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/14.sram_ctrl_executable.3692989582
Short name T240
Test name
Test status
Simulation time 146128336786 ps
CPU time 1702.27 seconds
Started Jun 30 04:44:14 PM PDT 24
Finished Jun 30 05:12:37 PM PDT 24
Peak memory 379660 kb
Host smart-15674802-247c-4021-8c79-f9d8eff5e6aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692989582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executab
le.3692989582
Directory /workspace/14.sram_ctrl_executable/latest

Test location /workspace/coverage/default/14.sram_ctrl_lc_escalation.1556265822
Short name T767
Test name
Test status
Simulation time 58030356599 ps
CPU time 100.95 seconds
Started Jun 30 04:44:12 PM PDT 24
Finished Jun 30 04:45:54 PM PDT 24
Peak memory 202760 kb
Host smart-cea8214c-33df-4801-b68b-f3ebdbf31378
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556265822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es
calation.1556265822
Directory /workspace/14.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/14.sram_ctrl_max_throughput.3330672951
Short name T537
Test name
Test status
Simulation time 857226764 ps
CPU time 58.77 seconds
Started Jun 30 04:44:04 PM PDT 24
Finished Jun 30 04:45:05 PM PDT 24
Peak memory 315396 kb
Host smart-22c36f5b-321d-42da-9af6-04c8aba41f3b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330672951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.sram_ctrl_max_throughput.3330672951
Directory /workspace/14.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_partial_access.942524378
Short name T98
Test name
Test status
Simulation time 10209400964 ps
CPU time 162.83 seconds
Started Jun 30 04:44:03 PM PDT 24
Finished Jun 30 04:46:48 PM PDT 24
Peak memory 219092 kb
Host smart-3c89886c-e115-416c-b021-982ddda44e28
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942524378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.sram_ctrl_mem_partial_access.942524378
Directory /workspace/14.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_walk.3971798002
Short name T923
Test name
Test status
Simulation time 14423517278 ps
CPU time 296.84 seconds
Started Jun 30 04:44:08 PM PDT 24
Finished Jun 30 04:49:05 PM PDT 24
Peak memory 210840 kb
Host smart-d3cb1345-2e81-4e72-914f-b9fca2b152c1
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971798002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr
l_mem_walk.3971798002
Directory /workspace/14.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/14.sram_ctrl_multiple_keys.3459717868
Short name T797
Test name
Test status
Simulation time 35013056379 ps
CPU time 385.78 seconds
Started Jun 30 04:44:06 PM PDT 24
Finished Jun 30 04:50:33 PM PDT 24
Peak memory 376692 kb
Host smart-669798ce-07fd-47de-8344-e7c8a4334d8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459717868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi
ple_keys.3459717868
Directory /workspace/14.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access.1013906140
Short name T268
Test name
Test status
Simulation time 962530382 ps
CPU time 22.91 seconds
Started Jun 30 04:44:00 PM PDT 24
Finished Jun 30 04:44:24 PM PDT 24
Peak memory 202592 kb
Host smart-257cf54c-d62a-4f28-a8f4-4e56499c20e0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013906140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
sram_ctrl_partial_access.1013906140
Directory /workspace/14.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_ram_cfg.573204577
Short name T618
Test name
Test status
Simulation time 5612333726 ps
CPU time 3.74 seconds
Started Jun 30 04:44:05 PM PDT 24
Finished Jun 30 04:44:11 PM PDT 24
Peak memory 202712 kb
Host smart-72ca2a87-f777-4125-960d-bf6d4afb8939
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573204577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.573204577
Directory /workspace/14.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/14.sram_ctrl_regwen.593476499
Short name T651
Test name
Test status
Simulation time 59677708741 ps
CPU time 844.81 seconds
Started Jun 30 04:44:09 PM PDT 24
Finished Jun 30 04:58:14 PM PDT 24
Peak memory 380668 kb
Host smart-0fb25d4e-e011-403c-acf2-871d3a2e2296
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593476499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.593476499
Directory /workspace/14.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/14.sram_ctrl_smoke.3863088005
Short name T9
Test name
Test status
Simulation time 2938045309 ps
CPU time 9.32 seconds
Started Jun 30 04:44:05 PM PDT 24
Finished Jun 30 04:44:16 PM PDT 24
Peak memory 202744 kb
Host smart-ee7ad170-576e-41f3-b132-b6ce83dd095d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863088005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.3863088005
Directory /workspace/14.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all.4039865919
Short name T220
Test name
Test status
Simulation time 279697953652 ps
CPU time 2702.31 seconds
Started Jun 30 04:44:04 PM PDT 24
Finished Jun 30 05:29:09 PM PDT 24
Peak memory 305268 kb
Host smart-04fbdc94-8af1-4bd3-9862-04b0236e6df0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039865919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 14.sram_ctrl_stress_all.4039865919
Directory /workspace/14.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.200078391
Short name T2
Test name
Test status
Simulation time 1074155209 ps
CPU time 10.9 seconds
Started Jun 30 04:44:03 PM PDT 24
Finished Jun 30 04:44:16 PM PDT 24
Peak memory 210904 kb
Host smart-023c7b2a-b718-4200-ab02-4dcd482dd8c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=200078391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.200078391
Directory /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_pipeline.2685063601
Short name T323
Test name
Test status
Simulation time 39834551517 ps
CPU time 208.05 seconds
Started Jun 30 04:43:56 PM PDT 24
Finished Jun 30 04:47:25 PM PDT 24
Peak memory 202744 kb
Host smart-72921423-3b91-4d2e-b0f7-4ef3f65db8a7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685063601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_stress_pipeline.2685063601
Directory /workspace/14.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3427859773
Short name T806
Test name
Test status
Simulation time 1426936280 ps
CPU time 8.55 seconds
Started Jun 30 04:43:56 PM PDT 24
Finished Jun 30 04:44:05 PM PDT 24
Peak memory 220900 kb
Host smart-753dcd08-3a48-4591-b006-1a44f8f850ae
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427859773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.3427859773
Directory /workspace/14.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/15.sram_ctrl_access_during_key_req.2609512918
Short name T714
Test name
Test status
Simulation time 11540667795 ps
CPU time 1367.71 seconds
Started Jun 30 04:43:53 PM PDT 24
Finished Jun 30 05:06:42 PM PDT 24
Peak memory 373488 kb
Host smart-57e3744c-1fcd-4f01-a051-7dda2aa0c8f5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609512918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_access_during_key_req.2609512918
Directory /workspace/15.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/15.sram_ctrl_alert_test.967707806
Short name T257
Test name
Test status
Simulation time 35685735 ps
CPU time 0.65 seconds
Started Jun 30 04:44:22 PM PDT 24
Finished Jun 30 04:44:24 PM PDT 24
Peak memory 202320 kb
Host smart-d1255499-0c42-4a03-b341-e108c91798b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967707806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.sram_ctrl_alert_test.967707806
Directory /workspace/15.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sram_ctrl_bijection.1686236677
Short name T266
Test name
Test status
Simulation time 73424625565 ps
CPU time 1399.79 seconds
Started Jun 30 04:44:07 PM PDT 24
Finished Jun 30 05:07:28 PM PDT 24
Peak memory 203576 kb
Host smart-d74731c4-4e85-4f49-a923-393d915dd8f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686236677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection
.1686236677
Directory /workspace/15.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/15.sram_ctrl_executable.1672502110
Short name T932
Test name
Test status
Simulation time 36068783560 ps
CPU time 1888.49 seconds
Started Jun 30 04:44:14 PM PDT 24
Finished Jun 30 05:15:44 PM PDT 24
Peak memory 379800 kb
Host smart-065e2f94-edb8-47e8-94d9-cd7f2a13be28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672502110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executab
le.1672502110
Directory /workspace/15.sram_ctrl_executable/latest

Test location /workspace/coverage/default/15.sram_ctrl_lc_escalation.4172728172
Short name T582
Test name
Test status
Simulation time 2627466010 ps
CPU time 6.4 seconds
Started Jun 30 04:44:10 PM PDT 24
Finished Jun 30 04:44:17 PM PDT 24
Peak memory 213204 kb
Host smart-73d90c0b-2984-40d0-9285-a71bd35d722e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172728172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es
calation.4172728172
Directory /workspace/15.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/15.sram_ctrl_max_throughput.4136533378
Short name T717
Test name
Test status
Simulation time 773668091 ps
CPU time 36.66 seconds
Started Jun 30 04:43:59 PM PDT 24
Finished Jun 30 04:44:37 PM PDT 24
Peak memory 286436 kb
Host smart-3eaa1cce-f1bb-4271-9399-7fb93d0de4cd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136533378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.sram_ctrl_max_throughput.4136533378
Directory /workspace/15.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_partial_access.3383322475
Short name T672
Test name
Test status
Simulation time 2689138389 ps
CPU time 87.69 seconds
Started Jun 30 04:44:19 PM PDT 24
Finished Jun 30 04:45:48 PM PDT 24
Peak memory 218964 kb
Host smart-12a15083-9d55-4475-b89c-37ae62b7c9c4
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383322475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_mem_partial_access.3383322475
Directory /workspace/15.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_walk.909146878
Short name T509
Test name
Test status
Simulation time 21963484435 ps
CPU time 326.13 seconds
Started Jun 30 04:44:17 PM PDT 24
Finished Jun 30 04:49:44 PM PDT 24
Peak memory 210860 kb
Host smart-757ed108-364d-4116-bef1-e3bda699bcbd
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909146878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl
_mem_walk.909146878
Directory /workspace/15.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/15.sram_ctrl_multiple_keys.4235611688
Short name T341
Test name
Test status
Simulation time 10314478224 ps
CPU time 739.17 seconds
Started Jun 30 04:44:04 PM PDT 24
Finished Jun 30 04:56:25 PM PDT 24
Peak memory 371500 kb
Host smart-bafc254a-7f9a-4d01-8a5e-8c7d97e39189
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235611688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multi
ple_keys.4235611688
Directory /workspace/15.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access.2536718882
Short name T219
Test name
Test status
Simulation time 2005524409 ps
CPU time 6.74 seconds
Started Jun 30 04:44:11 PM PDT 24
Finished Jun 30 04:44:18 PM PDT 24
Peak memory 202640 kb
Host smart-18bad66c-64f6-4228-b27e-0525190ca671
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536718882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
sram_ctrl_partial_access.2536718882
Directory /workspace/15.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.545187057
Short name T776
Test name
Test status
Simulation time 95346190229 ps
CPU time 408.59 seconds
Started Jun 30 04:44:08 PM PDT 24
Finished Jun 30 04:50:57 PM PDT 24
Peak memory 202688 kb
Host smart-9fabe026-b01b-4153-a9a3-76b683599d68
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545187057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.sram_ctrl_partial_access_b2b.545187057
Directory /workspace/15.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/15.sram_ctrl_ram_cfg.880281151
Short name T25
Test name
Test status
Simulation time 369891838 ps
CPU time 3.57 seconds
Started Jun 30 04:44:23 PM PDT 24
Finished Jun 30 04:44:28 PM PDT 24
Peak memory 202792 kb
Host smart-8e237c0f-318a-4be2-b314-de9cf7d0ddc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880281151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.880281151
Directory /workspace/15.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/15.sram_ctrl_regwen.895547024
Short name T261
Test name
Test status
Simulation time 5070885509 ps
CPU time 498.03 seconds
Started Jun 30 04:44:26 PM PDT 24
Finished Jun 30 04:52:44 PM PDT 24
Peak memory 367404 kb
Host smart-3146e5d0-f4d4-4579-9b39-6d2c2f80e55d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895547024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.895547024
Directory /workspace/15.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/15.sram_ctrl_smoke.3399002812
Short name T331
Test name
Test status
Simulation time 1119909318 ps
CPU time 16.39 seconds
Started Jun 30 04:44:10 PM PDT 24
Finished Jun 30 04:44:28 PM PDT 24
Peak memory 202632 kb
Host smart-9314611a-b32c-464f-b9eb-be85b7cfc6c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399002812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.3399002812
Directory /workspace/15.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all.1815382741
Short name T19
Test name
Test status
Simulation time 173057064763 ps
CPU time 6855.36 seconds
Started Jun 30 04:44:21 PM PDT 24
Finished Jun 30 06:38:38 PM PDT 24
Peak memory 377628 kb
Host smart-d7ec5912-f4f6-43fa-a954-cf8032653a53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815382741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 15.sram_ctrl_stress_all.1815382741
Directory /workspace/15.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.429586036
Short name T302
Test name
Test status
Simulation time 1551201097 ps
CPU time 12.33 seconds
Started Jun 30 04:44:19 PM PDT 24
Finished Jun 30 04:44:32 PM PDT 24
Peak memory 210864 kb
Host smart-0e6e70c3-0557-4945-ac5e-eee133876099
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=429586036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.429586036
Directory /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_pipeline.3089648976
Short name T758
Test name
Test status
Simulation time 26163631239 ps
CPU time 204.43 seconds
Started Jun 30 04:44:10 PM PDT 24
Finished Jun 30 04:47:35 PM PDT 24
Peak memory 202748 kb
Host smart-ad05805b-a747-4a0f-9ced-641813cf2e71
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089648976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_stress_pipeline.3089648976
Directory /workspace/15.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.1979804493
Short name T773
Test name
Test status
Simulation time 2996530656 ps
CPU time 69.43 seconds
Started Jun 30 04:44:07 PM PDT 24
Finished Jun 30 04:45:17 PM PDT 24
Peak memory 321556 kb
Host smart-18c4a8c2-e30f-4fea-a58c-7ac505323efd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979804493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.1979804493
Directory /workspace/15.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/16.sram_ctrl_access_during_key_req.587642304
Short name T678
Test name
Test status
Simulation time 22247276717 ps
CPU time 1269.24 seconds
Started Jun 30 04:44:29 PM PDT 24
Finished Jun 30 05:05:39 PM PDT 24
Peak memory 376572 kb
Host smart-dc8625e8-530f-4ca1-b41a-472823de8cd8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587642304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 16.sram_ctrl_access_during_key_req.587642304
Directory /workspace/16.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/16.sram_ctrl_alert_test.1223986344
Short name T463
Test name
Test status
Simulation time 29008043 ps
CPU time 0.62 seconds
Started Jun 30 04:44:18 PM PDT 24
Finished Jun 30 04:44:20 PM PDT 24
Peak memory 202268 kb
Host smart-ac60ae0d-fb36-4451-a197-cb30ce4d529a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223986344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.sram_ctrl_alert_test.1223986344
Directory /workspace/16.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sram_ctrl_bijection.285310812
Short name T479
Test name
Test status
Simulation time 24702004883 ps
CPU time 1736.1 seconds
Started Jun 30 04:44:14 PM PDT 24
Finished Jun 30 05:13:11 PM PDT 24
Peak memory 203520 kb
Host smart-8e902853-b51b-4bf3-99f1-26e45dd4bd34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285310812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection.
285310812
Directory /workspace/16.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/16.sram_ctrl_executable.937037176
Short name T211
Test name
Test status
Simulation time 188816938692 ps
CPU time 1245.36 seconds
Started Jun 30 04:44:21 PM PDT 24
Finished Jun 30 05:05:07 PM PDT 24
Peak memory 379220 kb
Host smart-56ec5bd4-fe6a-48ee-8576-c76f97d70733
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937037176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executabl
e.937037176
Directory /workspace/16.sram_ctrl_executable/latest

Test location /workspace/coverage/default/16.sram_ctrl_lc_escalation.2119710852
Short name T343
Test name
Test status
Simulation time 55794262433 ps
CPU time 95.55 seconds
Started Jun 30 04:44:19 PM PDT 24
Finished Jun 30 04:45:56 PM PDT 24
Peak memory 202788 kb
Host smart-5559012c-695a-4ec4-8bc8-cfb4ad338234
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119710852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_es
calation.2119710852
Directory /workspace/16.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/16.sram_ctrl_max_throughput.4032400259
Short name T231
Test name
Test status
Simulation time 705063869 ps
CPU time 10.08 seconds
Started Jun 30 04:44:23 PM PDT 24
Finished Jun 30 04:44:34 PM PDT 24
Peak memory 235316 kb
Host smart-c3df6e05-b569-4510-ace7-0f8a9b7c6bfa
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032400259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.sram_ctrl_max_throughput.4032400259
Directory /workspace/16.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_partial_access.4109053454
Short name T825
Test name
Test status
Simulation time 12420063000 ps
CPU time 80.2 seconds
Started Jun 30 04:44:22 PM PDT 24
Finished Jun 30 04:45:44 PM PDT 24
Peak memory 219052 kb
Host smart-d487ad0d-f0fa-4127-9247-e72371fc851e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109053454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_mem_partial_access.4109053454
Directory /workspace/16.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_walk.2170520297
Short name T738
Test name
Test status
Simulation time 28171545495 ps
CPU time 143.54 seconds
Started Jun 30 04:44:13 PM PDT 24
Finished Jun 30 04:46:38 PM PDT 24
Peak memory 210852 kb
Host smart-a56cb157-67f4-4eb6-9ab3-68d4a181571f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170520297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr
l_mem_walk.2170520297
Directory /workspace/16.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/16.sram_ctrl_multiple_keys.3029658248
Short name T205
Test name
Test status
Simulation time 32040309144 ps
CPU time 855.15 seconds
Started Jun 30 04:44:21 PM PDT 24
Finished Jun 30 04:58:37 PM PDT 24
Peak memory 372468 kb
Host smart-74463cec-08c9-4f19-8fbe-9d7f98c66cf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029658248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi
ple_keys.3029658248
Directory /workspace/16.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access.2005199519
Short name T44
Test name
Test status
Simulation time 562840239 ps
CPU time 15.59 seconds
Started Jun 30 04:44:23 PM PDT 24
Finished Jun 30 04:44:40 PM PDT 24
Peak memory 202568 kb
Host smart-d918ac9c-20b8-4235-8d98-fc86171aa303
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005199519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
sram_ctrl_partial_access.2005199519
Directory /workspace/16.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.2482977341
Short name T170
Test name
Test status
Simulation time 7480545315 ps
CPU time 478.94 seconds
Started Jun 30 04:44:03 PM PDT 24
Finished Jun 30 04:52:04 PM PDT 24
Peak memory 202720 kb
Host smart-a94b73d3-45c0-4406-88b4-4000bad18b2a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482977341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 16.sram_ctrl_partial_access_b2b.2482977341
Directory /workspace/16.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/16.sram_ctrl_ram_cfg.1083530406
Short name T800
Test name
Test status
Simulation time 691651671 ps
CPU time 3.65 seconds
Started Jun 30 04:44:00 PM PDT 24
Finished Jun 30 04:44:04 PM PDT 24
Peak memory 202840 kb
Host smart-bb8af8af-0d8b-4990-9df3-146c24d6f7da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083530406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.1083530406
Directory /workspace/16.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/16.sram_ctrl_regwen.2331215255
Short name T538
Test name
Test status
Simulation time 6623822418 ps
CPU time 29.25 seconds
Started Jun 30 04:44:07 PM PDT 24
Finished Jun 30 04:44:37 PM PDT 24
Peak memory 215784 kb
Host smart-e6402f10-1f1e-4ac3-949e-1cbf9af2fac4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331215255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.2331215255
Directory /workspace/16.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/16.sram_ctrl_smoke.3105161883
Short name T367
Test name
Test status
Simulation time 961865316 ps
CPU time 13.23 seconds
Started Jun 30 04:44:22 PM PDT 24
Finished Jun 30 04:44:36 PM PDT 24
Peak memory 202576 kb
Host smart-91d0c75c-4992-4993-8cda-075fbb438292
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105161883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.3105161883
Directory /workspace/16.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1177982539
Short name T694
Test name
Test status
Simulation time 1270753717 ps
CPU time 12.19 seconds
Started Jun 30 04:44:12 PM PDT 24
Finished Jun 30 04:44:25 PM PDT 24
Peak memory 212712 kb
Host smart-5def1be1-7a2b-4c77-8f7f-d23e815c77f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1177982539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.1177982539
Directory /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_pipeline.4121329798
Short name T223
Test name
Test status
Simulation time 9867809330 ps
CPU time 177.2 seconds
Started Jun 30 04:44:13 PM PDT 24
Finished Jun 30 04:47:11 PM PDT 24
Peak memory 202736 kb
Host smart-05def7cc-f3e2-4fbf-b59d-12c7f4a37e31
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121329798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_stress_pipeline.4121329798
Directory /workspace/16.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.3902266682
Short name T480
Test name
Test status
Simulation time 684707989 ps
CPU time 7.47 seconds
Started Jun 30 04:44:08 PM PDT 24
Finished Jun 30 04:44:16 PM PDT 24
Peak memory 218136 kb
Host smart-a109b43f-048b-427a-b343-2b706d528a78
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902266682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.3902266682
Directory /workspace/16.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/17.sram_ctrl_access_during_key_req.1486977463
Short name T525
Test name
Test status
Simulation time 29143895468 ps
CPU time 1015.54 seconds
Started Jun 30 04:44:18 PM PDT 24
Finished Jun 30 05:01:14 PM PDT 24
Peak memory 379620 kb
Host smart-ee2727d9-2f21-423d-bdcd-44e8e784b274
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486977463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_access_during_key_req.1486977463
Directory /workspace/17.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/17.sram_ctrl_alert_test.1040842349
Short name T308
Test name
Test status
Simulation time 51246499 ps
CPU time 0.68 seconds
Started Jun 30 04:44:13 PM PDT 24
Finished Jun 30 04:44:14 PM PDT 24
Peak memory 202424 kb
Host smart-50001a76-22c6-4512-a4e9-1563011371bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040842349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.sram_ctrl_alert_test.1040842349
Directory /workspace/17.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sram_ctrl_bijection.2473172073
Short name T922
Test name
Test status
Simulation time 132924488364 ps
CPU time 2291.29 seconds
Started Jun 30 04:44:14 PM PDT 24
Finished Jun 30 05:22:26 PM PDT 24
Peak memory 202916 kb
Host smart-7244101b-1b9e-4cd5-9d3b-beb933be9249
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473172073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection
.2473172073
Directory /workspace/17.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/17.sram_ctrl_executable.3904100944
Short name T158
Test name
Test status
Simulation time 22115903580 ps
CPU time 304.96 seconds
Started Jun 30 04:44:18 PM PDT 24
Finished Jun 30 04:49:24 PM PDT 24
Peak memory 362216 kb
Host smart-1ee8e768-7cf0-4210-afda-45aeea9e798d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904100944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executab
le.3904100944
Directory /workspace/17.sram_ctrl_executable/latest

Test location /workspace/coverage/default/17.sram_ctrl_lc_escalation.2740986872
Short name T421
Test name
Test status
Simulation time 5817848630 ps
CPU time 32.62 seconds
Started Jun 30 04:44:18 PM PDT 24
Finished Jun 30 04:44:51 PM PDT 24
Peak memory 202736 kb
Host smart-328dbdc0-a06b-42ab-ae26-9f31f702b1ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740986872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_es
calation.2740986872
Directory /workspace/17.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/17.sram_ctrl_max_throughput.219985753
Short name T277
Test name
Test status
Simulation time 2395600105 ps
CPU time 124.6 seconds
Started Jun 30 04:44:11 PM PDT 24
Finished Jun 30 04:46:16 PM PDT 24
Peak memory 369280 kb
Host smart-b01692e8-0e54-433a-b5e3-17a8d48cd346
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219985753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.sram_ctrl_max_throughput.219985753
Directory /workspace/17.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_partial_access.1921124144
Short name T870
Test name
Test status
Simulation time 20473490167 ps
CPU time 166.93 seconds
Started Jun 30 04:44:07 PM PDT 24
Finished Jun 30 04:46:55 PM PDT 24
Peak memory 210972 kb
Host smart-90bffa90-6552-41f8-9753-14ecc1052355
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921124144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_mem_partial_access.1921124144
Directory /workspace/17.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_walk.1745224354
Short name T818
Test name
Test status
Simulation time 4583800891 ps
CPU time 252.15 seconds
Started Jun 30 04:44:22 PM PDT 24
Finished Jun 30 04:48:35 PM PDT 24
Peak memory 210900 kb
Host smart-86325073-ef25-4123-8a57-90a9198e5f53
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745224354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr
l_mem_walk.1745224354
Directory /workspace/17.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/17.sram_ctrl_multiple_keys.146586144
Short name T142
Test name
Test status
Simulation time 17621402702 ps
CPU time 613.13 seconds
Started Jun 30 04:44:18 PM PDT 24
Finished Jun 30 04:54:32 PM PDT 24
Peak memory 378496 kb
Host smart-77d69eea-d9f6-459e-8383-76cccbc5dd83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146586144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multip
le_keys.146586144
Directory /workspace/17.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access.1135090549
Short name T364
Test name
Test status
Simulation time 1158065070 ps
CPU time 5.9 seconds
Started Jun 30 04:44:13 PM PDT 24
Finished Jun 30 04:44:20 PM PDT 24
Peak memory 202460 kb
Host smart-0283bbdf-b95b-4e78-be7d-c2a8c07b41c8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135090549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
sram_ctrl_partial_access.1135090549
Directory /workspace/17.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.970015810
Short name T842
Test name
Test status
Simulation time 29602326511 ps
CPU time 435.64 seconds
Started Jun 30 04:44:12 PM PDT 24
Finished Jun 30 04:51:28 PM PDT 24
Peak memory 202716 kb
Host smart-b86ad29d-5046-4347-9d08-a958374f9984
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970015810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.sram_ctrl_partial_access_b2b.970015810
Directory /workspace/17.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/17.sram_ctrl_ram_cfg.1451845605
Short name T574
Test name
Test status
Simulation time 369539829 ps
CPU time 3.2 seconds
Started Jun 30 04:43:59 PM PDT 24
Finished Jun 30 04:44:04 PM PDT 24
Peak memory 202768 kb
Host smart-cbfb1e5d-d475-44da-bce6-e1f3c8b17ec3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451845605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.1451845605
Directory /workspace/17.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/17.sram_ctrl_regwen.2936789316
Short name T188
Test name
Test status
Simulation time 9063575524 ps
CPU time 848.98 seconds
Started Jun 30 04:44:22 PM PDT 24
Finished Jun 30 04:58:32 PM PDT 24
Peak memory 379680 kb
Host smart-ce1b7d8b-8cc9-4744-a494-a27cba4a56d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936789316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.2936789316
Directory /workspace/17.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/17.sram_ctrl_smoke.2435313392
Short name T880
Test name
Test status
Simulation time 4131580205 ps
CPU time 14.56 seconds
Started Jun 30 04:44:15 PM PDT 24
Finished Jun 30 04:44:30 PM PDT 24
Peak memory 202736 kb
Host smart-05bf26f7-a1fa-4b04-8b6c-e0f59d8292ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435313392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.2435313392
Directory /workspace/17.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all.4216450132
Short name T181
Test name
Test status
Simulation time 35101247054 ps
CPU time 2538.99 seconds
Started Jun 30 04:44:14 PM PDT 24
Finished Jun 30 05:26:34 PM PDT 24
Peak memory 382732 kb
Host smart-43d83544-0368-4156-ae37-609eda6a8647
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216450132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 17.sram_ctrl_stress_all.4216450132
Directory /workspace/17.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2863427202
Short name T23
Test name
Test status
Simulation time 4672300960 ps
CPU time 30.14 seconds
Started Jun 30 04:44:11 PM PDT 24
Finished Jun 30 04:44:42 PM PDT 24
Peak memory 218216 kb
Host smart-2736598e-f643-4999-bf4c-efdffa7c27ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2863427202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.2863427202
Directory /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_pipeline.1619241561
Short name T420
Test name
Test status
Simulation time 12579562955 ps
CPU time 254.02 seconds
Started Jun 30 04:44:19 PM PDT 24
Finished Jun 30 04:48:34 PM PDT 24
Peak memory 202676 kb
Host smart-71560044-50ff-4a14-8528-516630256cb7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619241561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_stress_pipeline.1619241561
Directory /workspace/17.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.1300708467
Short name T478
Test name
Test status
Simulation time 735852782 ps
CPU time 15.72 seconds
Started Jun 30 04:44:19 PM PDT 24
Finished Jun 30 04:44:36 PM PDT 24
Peak memory 240908 kb
Host smart-748ac867-d649-4f74-9227-662949dc9ee9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300708467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.1300708467
Directory /workspace/17.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/18.sram_ctrl_access_during_key_req.2641266717
Short name T392
Test name
Test status
Simulation time 81343092311 ps
CPU time 695.47 seconds
Started Jun 30 04:44:13 PM PDT 24
Finished Jun 30 04:55:49 PM PDT 24
Peak memory 371940 kb
Host smart-80f983b3-7607-482f-98d5-cbd4494e9936
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641266717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_access_during_key_req.2641266717
Directory /workspace/18.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/18.sram_ctrl_alert_test.2893972312
Short name T221
Test name
Test status
Simulation time 82951555 ps
CPU time 0.67 seconds
Started Jun 30 04:44:11 PM PDT 24
Finished Jun 30 04:44:13 PM PDT 24
Peak memory 202388 kb
Host smart-06a4c2aa-f284-4758-bea8-fd21fe82b613
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893972312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.sram_ctrl_alert_test.2893972312
Directory /workspace/18.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sram_ctrl_bijection.309496413
Short name T657
Test name
Test status
Simulation time 45092111321 ps
CPU time 750.17 seconds
Started Jun 30 04:44:13 PM PDT 24
Finished Jun 30 04:56:44 PM PDT 24
Peak memory 203336 kb
Host smart-1d97cdf2-8f05-4c46-bd83-9c962e88af76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309496413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection.
309496413
Directory /workspace/18.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/18.sram_ctrl_executable.1505763477
Short name T377
Test name
Test status
Simulation time 24507149020 ps
CPU time 858.02 seconds
Started Jun 30 04:44:13 PM PDT 24
Finished Jun 30 04:58:32 PM PDT 24
Peak memory 379628 kb
Host smart-195673b7-f751-4bdc-b502-a47df7aeebde
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505763477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executab
le.1505763477
Directory /workspace/18.sram_ctrl_executable/latest

Test location /workspace/coverage/default/18.sram_ctrl_lc_escalation.3459716783
Short name T169
Test name
Test status
Simulation time 44238258100 ps
CPU time 71.54 seconds
Started Jun 30 04:44:03 PM PDT 24
Finished Jun 30 04:45:17 PM PDT 24
Peak memory 202752 kb
Host smart-b8603efc-5446-461c-ada1-ef73d3dc9d9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459716783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_es
calation.3459716783
Directory /workspace/18.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/18.sram_ctrl_max_throughput.1872949719
Short name T624
Test name
Test status
Simulation time 8286282858 ps
CPU time 72.64 seconds
Started Jun 30 04:44:20 PM PDT 24
Finished Jun 30 04:45:33 PM PDT 24
Peak memory 344920 kb
Host smart-9a880db4-edc0-4197-a4f8-1acbc571a7dc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872949719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.sram_ctrl_max_throughput.1872949719
Directory /workspace/18.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_partial_access.1621166826
Short name T267
Test name
Test status
Simulation time 6405431673 ps
CPU time 148.89 seconds
Started Jun 30 04:44:11 PM PDT 24
Finished Jun 30 04:46:41 PM PDT 24
Peak memory 210904 kb
Host smart-a53a579c-f855-446a-99a2-2110b532153a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621166826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_mem_partial_access.1621166826
Directory /workspace/18.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_walk.798086375
Short name T809
Test name
Test status
Simulation time 104975450266 ps
CPU time 318.3 seconds
Started Jun 30 04:44:24 PM PDT 24
Finished Jun 30 04:49:43 PM PDT 24
Peak memory 210936 kb
Host smart-1c894726-dbad-4f52-9d6a-a36881311740
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798086375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl
_mem_walk.798086375
Directory /workspace/18.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/18.sram_ctrl_multiple_keys.3573041183
Short name T42
Test name
Test status
Simulation time 87365108056 ps
CPU time 1399.07 seconds
Started Jun 30 04:44:01 PM PDT 24
Finished Jun 30 05:07:21 PM PDT 24
Peak memory 380708 kb
Host smart-096578d5-2621-4387-85f0-c7da517ecda9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573041183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multi
ple_keys.3573041183
Directory /workspace/18.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access.1650985738
Short name T150
Test name
Test status
Simulation time 350705100 ps
CPU time 3.82 seconds
Started Jun 30 04:44:14 PM PDT 24
Finished Jun 30 04:44:19 PM PDT 24
Peak memory 202460 kb
Host smart-f217c714-8962-45db-9680-251f8ee637ff
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650985738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
sram_ctrl_partial_access.1650985738
Directory /workspace/18.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1656340810
Short name T746
Test name
Test status
Simulation time 7817287778 ps
CPU time 422.17 seconds
Started Jun 30 04:44:17 PM PDT 24
Finished Jun 30 04:51:20 PM PDT 24
Peak memory 202732 kb
Host smart-e6187ddb-6fbc-43bc-8520-eb1a9b394b89
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656340810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 18.sram_ctrl_partial_access_b2b.1656340810
Directory /workspace/18.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/18.sram_ctrl_ram_cfg.1075156363
Short name T388
Test name
Test status
Simulation time 1483892181 ps
CPU time 3.35 seconds
Started Jun 30 04:44:22 PM PDT 24
Finished Jun 30 04:44:26 PM PDT 24
Peak memory 202608 kb
Host smart-939f92ab-3f6c-4388-80f5-60293b501374
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075156363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.1075156363
Directory /workspace/18.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/18.sram_ctrl_regwen.2232016001
Short name T675
Test name
Test status
Simulation time 1823637867 ps
CPU time 18.52 seconds
Started Jun 30 04:44:14 PM PDT 24
Finished Jun 30 04:44:34 PM PDT 24
Peak memory 219060 kb
Host smart-926c3729-f0d5-4cb2-8ed9-b3d25324570f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232016001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.2232016001
Directory /workspace/18.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/18.sram_ctrl_smoke.1115175330
Short name T481
Test name
Test status
Simulation time 808510125 ps
CPU time 37.66 seconds
Started Jun 30 04:44:18 PM PDT 24
Finished Jun 30 04:44:57 PM PDT 24
Peak memory 299768 kb
Host smart-21499514-fc84-4677-a6e2-9f5e2f64dba5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115175330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.1115175330
Directory /workspace/18.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all.3936498335
Short name T676
Test name
Test status
Simulation time 322291635293 ps
CPU time 7635.08 seconds
Started Jun 30 04:44:14 PM PDT 24
Finished Jun 30 06:51:31 PM PDT 24
Peak memory 377544 kb
Host smart-fb5728c0-5569-4926-9936-e1e4de7de4e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936498335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 18.sram_ctrl_stress_all.3936498335
Directory /workspace/18.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.199000002
Short name T821
Test name
Test status
Simulation time 1757101329 ps
CPU time 62.53 seconds
Started Jun 30 04:44:17 PM PDT 24
Finished Jun 30 04:45:20 PM PDT 24
Peak memory 245168 kb
Host smart-320f7374-6ab3-4376-ae57-eb15adf37541
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=199000002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.199000002
Directory /workspace/18.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_pipeline.3298968610
Short name T233
Test name
Test status
Simulation time 3798591245 ps
CPU time 260.78 seconds
Started Jun 30 04:44:22 PM PDT 24
Finished Jun 30 04:48:44 PM PDT 24
Peak memory 202592 kb
Host smart-6a6cc3ac-52b4-44de-955a-087339c82ef5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298968610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_stress_pipeline.3298968610
Directory /workspace/18.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.3150803787
Short name T399
Test name
Test status
Simulation time 790268106 ps
CPU time 63.6 seconds
Started Jun 30 04:44:17 PM PDT 24
Finished Jun 30 04:45:21 PM PDT 24
Peak memory 326312 kb
Host smart-38124720-0e5c-4e4f-993e-4a8a272dea07
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150803787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.3150803787
Directory /workspace/18.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/19.sram_ctrl_access_during_key_req.3535962962
Short name T97
Test name
Test status
Simulation time 9419033597 ps
CPU time 1149.69 seconds
Started Jun 30 04:44:33 PM PDT 24
Finished Jun 30 05:03:44 PM PDT 24
Peak memory 379316 kb
Host smart-29022200-7cfc-4ca9-88cd-0e52b7d75f1e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535962962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_access_during_key_req.3535962962
Directory /workspace/19.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/19.sram_ctrl_alert_test.2531992347
Short name T214
Test name
Test status
Simulation time 55700887 ps
CPU time 0.64 seconds
Started Jun 30 04:44:22 PM PDT 24
Finished Jun 30 04:44:24 PM PDT 24
Peak memory 202252 kb
Host smart-eeb9f82c-4e15-451e-9a1a-6efc0ff11c2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531992347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.sram_ctrl_alert_test.2531992347
Directory /workspace/19.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sram_ctrl_bijection.3753899202
Short name T814
Test name
Test status
Simulation time 47980276199 ps
CPU time 1735.85 seconds
Started Jun 30 04:44:12 PM PDT 24
Finished Jun 30 05:13:09 PM PDT 24
Peak memory 203340 kb
Host smart-d14aa281-e87b-4074-8830-6598037734bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753899202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection
.3753899202
Directory /workspace/19.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/19.sram_ctrl_executable.1854884092
Short name T362
Test name
Test status
Simulation time 22196895336 ps
CPU time 524.88 seconds
Started Jun 30 04:44:26 PM PDT 24
Finished Jun 30 04:53:11 PM PDT 24
Peak memory 368344 kb
Host smart-00fe2d9d-275a-43ba-9ade-6f32004ae111
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854884092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executab
le.1854884092
Directory /workspace/19.sram_ctrl_executable/latest

Test location /workspace/coverage/default/19.sram_ctrl_lc_escalation.3282518948
Short name T788
Test name
Test status
Simulation time 115235084327 ps
CPU time 94.44 seconds
Started Jun 30 04:44:26 PM PDT 24
Finished Jun 30 04:46:01 PM PDT 24
Peak memory 210908 kb
Host smart-8d485194-fe12-42a4-ba85-40a2b082e5b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282518948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es
calation.3282518948
Directory /workspace/19.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/19.sram_ctrl_max_throughput.797389933
Short name T641
Test name
Test status
Simulation time 1591851729 ps
CPU time 157.69 seconds
Started Jun 30 04:44:17 PM PDT 24
Finished Jun 30 04:46:56 PM PDT 24
Peak memory 371288 kb
Host smart-a80738ec-3cae-470e-b45d-da6e88da5105
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797389933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.sram_ctrl_max_throughput.797389933
Directory /workspace/19.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_partial_access.3140578869
Short name T598
Test name
Test status
Simulation time 3330586059 ps
CPU time 131.94 seconds
Started Jun 30 04:44:18 PM PDT 24
Finished Jun 30 04:46:31 PM PDT 24
Peak memory 210936 kb
Host smart-5cc0095f-3762-4e17-af65-7f207a3d0398
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140578869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.sram_ctrl_mem_partial_access.3140578869
Directory /workspace/19.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_walk.2492091447
Short name T447
Test name
Test status
Simulation time 26257014896 ps
CPU time 264.43 seconds
Started Jun 30 04:44:17 PM PDT 24
Finished Jun 30 04:48:42 PM PDT 24
Peak memory 210960 kb
Host smart-691144cb-2ed9-4cb3-89f0-ab390436b812
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492091447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr
l_mem_walk.2492091447
Directory /workspace/19.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/19.sram_ctrl_multiple_keys.771067737
Short name T244
Test name
Test status
Simulation time 24516486043 ps
CPU time 1286.06 seconds
Started Jun 30 04:44:12 PM PDT 24
Finished Jun 30 05:05:39 PM PDT 24
Peak memory 376540 kb
Host smart-b2f0565a-2774-4ba6-9deb-1c02f96961d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771067737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multip
le_keys.771067737
Directory /workspace/19.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access.3572242686
Short name T705
Test name
Test status
Simulation time 7896410166 ps
CPU time 19.45 seconds
Started Jun 30 04:44:14 PM PDT 24
Finished Jun 30 04:44:34 PM PDT 24
Peak memory 202680 kb
Host smart-9924ffb2-7f8a-49a8-9ab2-4492c6e0e16b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572242686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
sram_ctrl_partial_access.3572242686
Directory /workspace/19.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.1911752248
Short name T106
Test name
Test status
Simulation time 15162686316 ps
CPU time 311.93 seconds
Started Jun 30 04:44:30 PM PDT 24
Finished Jun 30 04:49:43 PM PDT 24
Peak memory 202068 kb
Host smart-a25a8592-3c04-4e5b-adc3-fb544d710c96
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911752248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 19.sram_ctrl_partial_access_b2b.1911752248
Directory /workspace/19.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/19.sram_ctrl_ram_cfg.68860991
Short name T174
Test name
Test status
Simulation time 607810883 ps
CPU time 3.54 seconds
Started Jun 30 04:44:13 PM PDT 24
Finished Jun 30 04:44:17 PM PDT 24
Peak memory 202680 kb
Host smart-fd541f4f-7536-485d-9b13-8a77bc926465
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68860991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf
g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.68860991
Directory /workspace/19.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/19.sram_ctrl_regwen.3588338507
Short name T655
Test name
Test status
Simulation time 12221422856 ps
CPU time 970.96 seconds
Started Jun 30 04:44:16 PM PDT 24
Finished Jun 30 05:00:28 PM PDT 24
Peak memory 377636 kb
Host smart-c9b4ac11-4361-4809-8fe4-7e5fc32a62da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588338507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.3588338507
Directory /workspace/19.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/19.sram_ctrl_smoke.920502744
Short name T899
Test name
Test status
Simulation time 4288594442 ps
CPU time 160.27 seconds
Started Jun 30 04:44:13 PM PDT 24
Finished Jun 30 04:46:54 PM PDT 24
Peak memory 370204 kb
Host smart-0ca213ac-3b86-49db-a752-1299a13cba52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920502744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.920502744
Directory /workspace/19.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all.4150307653
Short name T793
Test name
Test status
Simulation time 335494308579 ps
CPU time 5778.86 seconds
Started Jun 30 04:44:16 PM PDT 24
Finished Jun 30 06:20:36 PM PDT 24
Peak memory 381752 kb
Host smart-7350c6bd-fd79-463a-bcb7-833c8a6df023
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150307653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 19.sram_ctrl_stress_all.4150307653
Directory /workspace/19.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_pipeline.4020250011
Short name T665
Test name
Test status
Simulation time 26684973515 ps
CPU time 293.08 seconds
Started Jun 30 04:44:14 PM PDT 24
Finished Jun 30 04:49:08 PM PDT 24
Peak memory 202688 kb
Host smart-20c7fadd-a5ac-4725-aa22-c91c35aabc35
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020250011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.sram_ctrl_stress_pipeline.4020250011
Directory /workspace/19.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.539156366
Short name T326
Test name
Test status
Simulation time 888336735 ps
CPU time 159.1 seconds
Started Jun 30 04:44:21 PM PDT 24
Finished Jun 30 04:47:01 PM PDT 24
Peak memory 370228 kb
Host smart-60818eed-b878-4cde-9380-4299e642a8ac
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539156366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.sram_ctrl_throughput_w_partial_write.539156366
Directory /workspace/19.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/2.sram_ctrl_access_during_key_req.930904660
Short name T390
Test name
Test status
Simulation time 9342571123 ps
CPU time 580.31 seconds
Started Jun 30 04:43:35 PM PDT 24
Finished Jun 30 04:53:16 PM PDT 24
Peak memory 357120 kb
Host smart-c9e47059-f501-42b5-869c-b66e6bb1bd72
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930904660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.sram_ctrl_access_during_key_req.930904660
Directory /workspace/2.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/2.sram_ctrl_alert_test.219334749
Short name T575
Test name
Test status
Simulation time 14764426 ps
CPU time 0.65 seconds
Started Jun 30 04:43:41 PM PDT 24
Finished Jun 30 04:43:43 PM PDT 24
Peak memory 202312 kb
Host smart-2a3ca3d9-a6df-447a-9273-e99c26bdfa92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219334749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_alert_test.219334749
Directory /workspace/2.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sram_ctrl_bijection.432939039
Short name T507
Test name
Test status
Simulation time 23985621654 ps
CPU time 531.7 seconds
Started Jun 30 04:43:36 PM PDT 24
Finished Jun 30 04:52:28 PM PDT 24
Peak memory 203480 kb
Host smart-2a92a5e6-b24c-4e7d-8b24-3289a2756283
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432939039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.432939039
Directory /workspace/2.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/2.sram_ctrl_executable.1892686481
Short name T562
Test name
Test status
Simulation time 102815140966 ps
CPU time 463.85 seconds
Started Jun 30 04:43:33 PM PDT 24
Finished Jun 30 04:51:18 PM PDT 24
Peak memory 354100 kb
Host smart-dffcb4d7-cc4f-4002-9050-cef7ea79fbb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892686481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executabl
e.1892686481
Directory /workspace/2.sram_ctrl_executable/latest

Test location /workspace/coverage/default/2.sram_ctrl_lc_escalation.3746179305
Short name T457
Test name
Test status
Simulation time 5261898589 ps
CPU time 20.87 seconds
Started Jun 30 04:43:37 PM PDT 24
Finished Jun 30 04:43:58 PM PDT 24
Peak memory 210964 kb
Host smart-41930265-922d-4906-87f3-f890f3454b3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746179305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc
alation.3746179305
Directory /workspace/2.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/2.sram_ctrl_max_throughput.3722275744
Short name T740
Test name
Test status
Simulation time 7681505522 ps
CPU time 16.89 seconds
Started Jun 30 04:43:43 PM PDT 24
Finished Jun 30 04:44:00 PM PDT 24
Peak memory 250824 kb
Host smart-4e438e7d-eb67-445f-a364-acc528883ad4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722275744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.sram_ctrl_max_throughput.3722275744
Directory /workspace/2.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_partial_access.3141857785
Short name T610
Test name
Test status
Simulation time 5441998562 ps
CPU time 95.76 seconds
Started Jun 30 04:43:36 PM PDT 24
Finished Jun 30 04:45:12 PM PDT 24
Peak memory 219048 kb
Host smart-9f320df4-f86d-4df6-9d18-06a13131b428
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141857785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_mem_partial_access.3141857785
Directory /workspace/2.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_walk.248408837
Short name T370
Test name
Test status
Simulation time 28136534994 ps
CPU time 261.27 seconds
Started Jun 30 04:43:38 PM PDT 24
Finished Jun 30 04:48:00 PM PDT 24
Peak memory 210888 kb
Host smart-2d282f67-fe67-4d20-8fbe-4e67bed02ebc
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248408837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_
mem_walk.248408837
Directory /workspace/2.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/2.sram_ctrl_multiple_keys.4143304939
Short name T446
Test name
Test status
Simulation time 5620090511 ps
CPU time 152.49 seconds
Started Jun 30 04:43:32 PM PDT 24
Finished Jun 30 04:46:06 PM PDT 24
Peak memory 336588 kb
Host smart-0f7ee0a8-99c0-45c0-b3f5-03fbd21b0244
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143304939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip
le_keys.4143304939
Directory /workspace/2.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access.2240599541
Short name T3
Test name
Test status
Simulation time 6585620092 ps
CPU time 23.52 seconds
Started Jun 30 04:43:38 PM PDT 24
Finished Jun 30 04:44:03 PM PDT 24
Peak memory 202760 kb
Host smart-886780c0-2281-4c64-bc14-c0387f726eb2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240599541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s
ram_ctrl_partial_access.2240599541
Directory /workspace/2.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.3282058168
Short name T228
Test name
Test status
Simulation time 7855740784 ps
CPU time 492.02 seconds
Started Jun 30 04:43:34 PM PDT 24
Finished Jun 30 04:51:47 PM PDT 24
Peak memory 202672 kb
Host smart-2725cbc2-b850-4b5e-9d25-c805fe7e46c2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282058168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.sram_ctrl_partial_access_b2b.3282058168
Directory /workspace/2.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/2.sram_ctrl_ram_cfg.1837632705
Short name T374
Test name
Test status
Simulation time 1358333250 ps
CPU time 3.1 seconds
Started Jun 30 04:43:40 PM PDT 24
Finished Jun 30 04:43:44 PM PDT 24
Peak memory 202076 kb
Host smart-d647768a-bfc7-4f41-9daa-f8a31b4f5a1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837632705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.1837632705
Directory /workspace/2.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/2.sram_ctrl_regwen.1426166639
Short name T583
Test name
Test status
Simulation time 6009309466 ps
CPU time 480.17 seconds
Started Jun 30 04:43:48 PM PDT 24
Finished Jun 30 04:51:50 PM PDT 24
Peak memory 378556 kb
Host smart-d8c436a7-f529-4efd-b79b-8d58dda028ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426166639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.1426166639
Directory /workspace/2.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/2.sram_ctrl_sec_cm.3809544853
Short name T18
Test name
Test status
Simulation time 609872727 ps
CPU time 2.13 seconds
Started Jun 30 04:43:39 PM PDT 24
Finished Jun 30 04:43:42 PM PDT 24
Peak memory 222364 kb
Host smart-b77bb5a0-9306-4ed3-beba-b4eb97d50407
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809544853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_sec_cm.3809544853
Directory /workspace/2.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sram_ctrl_smoke.476254097
Short name T568
Test name
Test status
Simulation time 765832850 ps
CPU time 41.89 seconds
Started Jun 30 04:43:53 PM PDT 24
Finished Jun 30 04:44:35 PM PDT 24
Peak memory 291844 kb
Host smart-0df87878-2869-4efe-a32d-153e0e2b3682
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476254097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.476254097
Directory /workspace/2.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all.2466166135
Short name T247
Test name
Test status
Simulation time 51103372782 ps
CPU time 2812.01 seconds
Started Jun 30 04:43:50 PM PDT 24
Finished Jun 30 05:30:43 PM PDT 24
Peak memory 387820 kb
Host smart-6cae3336-96ce-4ad9-80d9-20c94b187ce7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466166135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.sram_ctrl_stress_all.2466166135
Directory /workspace/2.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2180975662
Short name T631
Test name
Test status
Simulation time 7151018300 ps
CPU time 57.44 seconds
Started Jun 30 04:43:41 PM PDT 24
Finished Jun 30 04:44:39 PM PDT 24
Peak memory 274736 kb
Host smart-cf14292b-049c-4a9b-9f61-6f5875c04589
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2180975662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.2180975662
Directory /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_pipeline.679218700
Short name T722
Test name
Test status
Simulation time 17840338211 ps
CPU time 251.15 seconds
Started Jun 30 04:43:48 PM PDT 24
Finished Jun 30 04:48:00 PM PDT 24
Peak memory 202740 kb
Host smart-21f27835-2c66-4b83-b6cc-d7842492af7d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679218700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
sram_ctrl_stress_pipeline.679218700
Directory /workspace/2.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.709424023
Short name T616
Test name
Test status
Simulation time 2884004921 ps
CPU time 11.43 seconds
Started Jun 30 04:43:37 PM PDT 24
Finished Jun 30 04:43:49 PM PDT 24
Peak memory 235428 kb
Host smart-67a03726-5eae-4963-af39-de093ef9651e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709424023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.sram_ctrl_throughput_w_partial_write.709424023
Directory /workspace/2.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/20.sram_ctrl_access_during_key_req.2461046037
Short name T335
Test name
Test status
Simulation time 14460206697 ps
CPU time 1562.92 seconds
Started Jun 30 04:44:24 PM PDT 24
Finished Jun 30 05:10:27 PM PDT 24
Peak memory 375912 kb
Host smart-80e36b27-7fea-4a69-bfe7-dccc96c5cfa0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461046037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.sram_ctrl_access_during_key_req.2461046037
Directory /workspace/20.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/20.sram_ctrl_alert_test.2400787561
Short name T890
Test name
Test status
Simulation time 40471398 ps
CPU time 0.64 seconds
Started Jun 30 04:44:21 PM PDT 24
Finished Jun 30 04:44:22 PM PDT 24
Peak memory 202440 kb
Host smart-dcf1b56a-66ab-472a-89d6-53b1cb0e6d90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400787561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.sram_ctrl_alert_test.2400787561
Directory /workspace/20.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sram_ctrl_bijection.3569866800
Short name T492
Test name
Test status
Simulation time 87297143587 ps
CPU time 1931.84 seconds
Started Jun 30 04:44:15 PM PDT 24
Finished Jun 30 05:16:28 PM PDT 24
Peak memory 203344 kb
Host smart-c1d4854e-0130-4d83-b3ce-3a63f6d5278c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569866800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection
.3569866800
Directory /workspace/20.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/20.sram_ctrl_executable.475909252
Short name T133
Test name
Test status
Simulation time 26553032992 ps
CPU time 889.26 seconds
Started Jun 30 04:44:17 PM PDT 24
Finished Jun 30 04:59:07 PM PDT 24
Peak memory 373520 kb
Host smart-f23d888b-6178-47da-9736-2a1b5565a0ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475909252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executabl
e.475909252
Directory /workspace/20.sram_ctrl_executable/latest

Test location /workspace/coverage/default/20.sram_ctrl_lc_escalation.295664016
Short name T718
Test name
Test status
Simulation time 62187976914 ps
CPU time 97.22 seconds
Started Jun 30 04:44:12 PM PDT 24
Finished Jun 30 04:45:50 PM PDT 24
Peak memory 202784 kb
Host smart-c89f0604-2daa-4e1c-98fb-8c3a9aa4a804
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295664016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_esc
alation.295664016
Directory /workspace/20.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/20.sram_ctrl_max_throughput.1527882194
Short name T189
Test name
Test status
Simulation time 699112890 ps
CPU time 16.62 seconds
Started Jun 30 04:44:17 PM PDT 24
Finished Jun 30 04:44:35 PM PDT 24
Peak memory 251684 kb
Host smart-cf810ba4-fd75-441a-9c5b-2637ccf40f50
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527882194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.sram_ctrl_max_throughput.1527882194
Directory /workspace/20.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_partial_access.3394395598
Short name T885
Test name
Test status
Simulation time 1648335330 ps
CPU time 125.16 seconds
Started Jun 30 04:44:28 PM PDT 24
Finished Jun 30 04:46:33 PM PDT 24
Peak memory 210840 kb
Host smart-58159b23-96b5-49e6-aa1f-31983b9b5cd3
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394395598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_mem_partial_access.3394395598
Directory /workspace/20.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_walk.2710790973
Short name T56
Test name
Test status
Simulation time 35866069645 ps
CPU time 357.33 seconds
Started Jun 30 04:44:27 PM PDT 24
Finished Jun 30 04:50:25 PM PDT 24
Peak memory 203340 kb
Host smart-05e9d84f-a65e-4397-9ef5-4509a8a9b83c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710790973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr
l_mem_walk.2710790973
Directory /workspace/20.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/20.sram_ctrl_multiple_keys.3038581196
Short name T416
Test name
Test status
Simulation time 67796073820 ps
CPU time 1002.59 seconds
Started Jun 30 04:44:24 PM PDT 24
Finished Jun 30 05:01:08 PM PDT 24
Peak memory 378644 kb
Host smart-76f52630-4d2b-499b-9aff-07377422ea37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038581196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multi
ple_keys.3038581196
Directory /workspace/20.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access.874336298
Short name T812
Test name
Test status
Simulation time 6386564083 ps
CPU time 12.51 seconds
Started Jun 30 04:44:27 PM PDT 24
Finished Jun 30 04:44:40 PM PDT 24
Peak memory 231404 kb
Host smart-555518aa-f8a1-4c44-9d92-f4598089fc82
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874336298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.s
ram_ctrl_partial_access.874336298
Directory /workspace/20.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.2752688694
Short name T212
Test name
Test status
Simulation time 56414479661 ps
CPU time 347.08 seconds
Started Jun 30 04:44:22 PM PDT 24
Finished Jun 30 04:50:11 PM PDT 24
Peak memory 202668 kb
Host smart-82f93fde-c5a8-44f6-bc0b-d4ef570cda89
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752688694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 20.sram_ctrl_partial_access_b2b.2752688694
Directory /workspace/20.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/20.sram_ctrl_ram_cfg.2499842296
Short name T252
Test name
Test status
Simulation time 360747755 ps
CPU time 3.28 seconds
Started Jun 30 04:44:26 PM PDT 24
Finished Jun 30 04:44:29 PM PDT 24
Peak memory 202780 kb
Host smart-de766801-e516-4960-82db-3ba00572f92d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499842296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.2499842296
Directory /workspace/20.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/20.sram_ctrl_regwen.3066620
Short name T743
Test name
Test status
Simulation time 36635810848 ps
CPU time 1454.53 seconds
Started Jun 30 04:44:21 PM PDT 24
Finished Jun 30 05:08:37 PM PDT 24
Peak memory 376524 kb
Host smart-16a3607d-549b-4658-a6aa-0d6801f12eea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.3066620
Directory /workspace/20.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/20.sram_ctrl_smoke.3169062762
Short name T930
Test name
Test status
Simulation time 12088020497 ps
CPU time 8.61 seconds
Started Jun 30 04:44:12 PM PDT 24
Finished Jun 30 04:44:21 PM PDT 24
Peak memory 202764 kb
Host smart-194c26ee-9b71-432d-a347-8c5555d3f3c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169062762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.3169062762
Directory /workspace/20.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all.787406011
Short name T359
Test name
Test status
Simulation time 372002554063 ps
CPU time 2168.39 seconds
Started Jun 30 04:44:19 PM PDT 24
Finished Jun 30 05:20:28 PM PDT 24
Peak memory 380632 kb
Host smart-5305c327-6a90-409f-a74d-0accffe68523
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787406011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 20.sram_ctrl_stress_all.787406011
Directory /workspace/20.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3954496852
Short name T115
Test name
Test status
Simulation time 2985499691 ps
CPU time 22.82 seconds
Started Jun 30 04:44:32 PM PDT 24
Finished Jun 30 04:44:57 PM PDT 24
Peak memory 211032 kb
Host smart-699e1bc0-30a3-4851-abc3-3445d11c3616
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3954496852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.3954496852
Directory /workspace/20.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_pipeline.1671923072
Short name T368
Test name
Test status
Simulation time 4629714047 ps
CPU time 326.36 seconds
Started Jun 30 04:44:26 PM PDT 24
Finished Jun 30 04:49:53 PM PDT 24
Peak memory 202756 kb
Host smart-ef449a56-3540-4d43-9aeb-87c0eb7b9f28
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671923072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_stress_pipeline.1671923072
Directory /workspace/20.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.301968694
Short name T204
Test name
Test status
Simulation time 1581702613 ps
CPU time 94.1 seconds
Started Jun 30 04:44:30 PM PDT 24
Finished Jun 30 04:46:05 PM PDT 24
Peak memory 333856 kb
Host smart-308c6799-e8a1-4ca5-9810-31c6f01e49da
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301968694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.sram_ctrl_throughput_w_partial_write.301968694
Directory /workspace/20.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/21.sram_ctrl_access_during_key_req.3137243275
Short name T628
Test name
Test status
Simulation time 17792195646 ps
CPU time 1184.15 seconds
Started Jun 30 04:44:30 PM PDT 24
Finished Jun 30 05:04:15 PM PDT 24
Peak memory 377716 kb
Host smart-2c5e220a-44d9-4044-a65a-3e41075b16d5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137243275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.sram_ctrl_access_during_key_req.3137243275
Directory /workspace/21.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/21.sram_ctrl_alert_test.401640010
Short name T397
Test name
Test status
Simulation time 39098020 ps
CPU time 0.67 seconds
Started Jun 30 04:44:26 PM PDT 24
Finished Jun 30 04:44:27 PM PDT 24
Peak memory 202464 kb
Host smart-cfff7b8d-9ab1-4fda-a221-b14b5c9b25a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401640010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.sram_ctrl_alert_test.401640010
Directory /workspace/21.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sram_ctrl_bijection.1747864311
Short name T39
Test name
Test status
Simulation time 21645168755 ps
CPU time 768 seconds
Started Jun 30 04:44:23 PM PDT 24
Finished Jun 30 04:57:12 PM PDT 24
Peak memory 202936 kb
Host smart-33e72f5a-73de-46f2-94b0-9cfdee6a4d4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747864311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection
.1747864311
Directory /workspace/21.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/21.sram_ctrl_executable.1185395402
Short name T299
Test name
Test status
Simulation time 27026905984 ps
CPU time 636.94 seconds
Started Jun 30 04:44:24 PM PDT 24
Finished Jun 30 04:55:02 PM PDT 24
Peak memory 367348 kb
Host smart-15b0c124-06d0-41c9-bc08-32aaa3799f17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185395402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executab
le.1185395402
Directory /workspace/21.sram_ctrl_executable/latest

Test location /workspace/coverage/default/21.sram_ctrl_lc_escalation.3683730519
Short name T874
Test name
Test status
Simulation time 26614049201 ps
CPU time 42.81 seconds
Started Jun 30 04:44:16 PM PDT 24
Finished Jun 30 04:44:59 PM PDT 24
Peak memory 202780 kb
Host smart-417f5ad8-4857-46a7-9e13-1648ef21d76c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683730519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_es
calation.3683730519
Directory /workspace/21.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/21.sram_ctrl_max_throughput.4311943
Short name T144
Test name
Test status
Simulation time 756157575 ps
CPU time 28.12 seconds
Started Jun 30 04:44:24 PM PDT 24
Finished Jun 30 04:44:53 PM PDT 24
Peak memory 284428 kb
Host smart-d7b91054-e900-4b1d-a601-7aaa654f0704
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4311943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base
_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 21.sram_ctrl_max_throughput.4311943
Directory /workspace/21.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_partial_access.1188385542
Short name T674
Test name
Test status
Simulation time 10391264525 ps
CPU time 162.08 seconds
Started Jun 30 04:44:29 PM PDT 24
Finished Jun 30 04:47:12 PM PDT 24
Peak memory 219096 kb
Host smart-8eaea2ce-e643-4709-a72f-cca66bb28dc2
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188385542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_mem_partial_access.1188385542
Directory /workspace/21.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_walk.1674702402
Short name T245
Test name
Test status
Simulation time 360028782879 ps
CPU time 457.04 seconds
Started Jun 30 04:44:33 PM PDT 24
Finished Jun 30 04:52:13 PM PDT 24
Peak memory 210964 kb
Host smart-a893f2fe-5242-4800-bdc3-cce20db0cb73
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674702402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctr
l_mem_walk.1674702402
Directory /workspace/21.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/21.sram_ctrl_multiple_keys.402867146
Short name T527
Test name
Test status
Simulation time 97140324290 ps
CPU time 2218.85 seconds
Started Jun 30 04:44:23 PM PDT 24
Finished Jun 30 05:21:23 PM PDT 24
Peak memory 377572 kb
Host smart-977f56e6-8aa1-4299-875a-b2ef88bf274f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402867146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multip
le_keys.402867146
Directory /workspace/21.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access.1701960824
Short name T401
Test name
Test status
Simulation time 509379177 ps
CPU time 5.42 seconds
Started Jun 30 04:44:27 PM PDT 24
Finished Jun 30 04:44:33 PM PDT 24
Peak memory 202568 kb
Host smart-5fda8739-a3d9-4c08-bea0-6dc2871973f8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701960824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
sram_ctrl_partial_access.1701960824
Directory /workspace/21.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2222554154
Short name T449
Test name
Test status
Simulation time 7375821549 ps
CPU time 400.34 seconds
Started Jun 30 04:44:19 PM PDT 24
Finished Jun 30 04:51:00 PM PDT 24
Peak memory 202700 kb
Host smart-e7f89d41-9a4a-4c87-b8da-73ec0682cdfd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222554154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 21.sram_ctrl_partial_access_b2b.2222554154
Directory /workspace/21.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/21.sram_ctrl_ram_cfg.77461137
Short name T430
Test name
Test status
Simulation time 3369066582 ps
CPU time 3.73 seconds
Started Jun 30 04:44:31 PM PDT 24
Finished Jun 30 04:44:36 PM PDT 24
Peak memory 202732 kb
Host smart-a62f6dc0-2580-4550-917a-058e0ed7bd2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77461137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf
g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.77461137
Directory /workspace/21.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/21.sram_ctrl_regwen.3981251764
Short name T4
Test name
Test status
Simulation time 2435159403 ps
CPU time 305.8 seconds
Started Jun 30 04:44:22 PM PDT 24
Finished Jun 30 04:49:29 PM PDT 24
Peak memory 368340 kb
Host smart-f0ba958d-c440-4080-b586-54170155176c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981251764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.3981251764
Directory /workspace/21.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/21.sram_ctrl_smoke.3219976491
Short name T894
Test name
Test status
Simulation time 7631656424 ps
CPU time 8.79 seconds
Started Jun 30 04:44:32 PM PDT 24
Finished Jun 30 04:44:42 PM PDT 24
Peak memory 202756 kb
Host smart-e29fcd6d-eb83-4eb6-8bff-724672dfb6d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219976491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.3219976491
Directory /workspace/21.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_all.1435832349
Short name T673
Test name
Test status
Simulation time 150093220146 ps
CPU time 4857.78 seconds
Started Jun 30 04:44:21 PM PDT 24
Finished Jun 30 06:05:20 PM PDT 24
Peak memory 380676 kb
Host smart-c6bcbad5-b900-4fe8-a585-d32a18a50eaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435832349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 21.sram_ctrl_stress_all.1435832349
Directory /workspace/21.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2380579588
Short name T907
Test name
Test status
Simulation time 975077415 ps
CPU time 19.83 seconds
Started Jun 30 04:44:19 PM PDT 24
Finished Jun 30 04:44:40 PM PDT 24
Peak memory 211276 kb
Host smart-d02d1d53-e112-4d2d-9c1a-33f999ab3857
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2380579588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.2380579588
Directory /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_pipeline.3827218471
Short name T934
Test name
Test status
Simulation time 21200083826 ps
CPU time 315.32 seconds
Started Jun 30 04:44:19 PM PDT 24
Finished Jun 30 04:49:35 PM PDT 24
Peak memory 202748 kb
Host smart-dc5d3a13-6fa7-4005-99f5-8c82139dc373
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827218471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_stress_pipeline.3827218471
Directory /workspace/21.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.3189464941
Short name T526
Test name
Test status
Simulation time 9473789862 ps
CPU time 74.84 seconds
Started Jun 30 04:44:26 PM PDT 24
Finished Jun 30 04:45:41 PM PDT 24
Peak memory 333572 kb
Host smart-93248d79-caeb-4648-a696-4354563d7814
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189464941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.3189464941
Directory /workspace/21.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/22.sram_ctrl_access_during_key_req.2653019569
Short name T750
Test name
Test status
Simulation time 20113630467 ps
CPU time 446.61 seconds
Started Jun 30 04:44:29 PM PDT 24
Finished Jun 30 04:51:57 PM PDT 24
Peak memory 333380 kb
Host smart-980b97aa-6cb8-4c01-ab13-11fa29f80926
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653019569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.sram_ctrl_access_during_key_req.2653019569
Directory /workspace/22.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/22.sram_ctrl_alert_test.2378509051
Short name T372
Test name
Test status
Simulation time 35126659 ps
CPU time 0.69 seconds
Started Jun 30 04:44:24 PM PDT 24
Finished Jun 30 04:44:25 PM PDT 24
Peak memory 202480 kb
Host smart-4ca007e7-c4c1-40d5-8b5e-6bd3cb0db793
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378509051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.sram_ctrl_alert_test.2378509051
Directory /workspace/22.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sram_ctrl_bijection.3201785760
Short name T502
Test name
Test status
Simulation time 62527465811 ps
CPU time 1357.42 seconds
Started Jun 30 04:44:21 PM PDT 24
Finished Jun 30 05:06:59 PM PDT 24
Peak memory 202996 kb
Host smart-68ecfb74-3e0e-4cc6-85d1-db493ab42b51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201785760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection
.3201785760
Directory /workspace/22.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/22.sram_ctrl_executable.1999745680
Short name T725
Test name
Test status
Simulation time 21855987651 ps
CPU time 887.76 seconds
Started Jun 30 04:44:23 PM PDT 24
Finished Jun 30 04:59:12 PM PDT 24
Peak memory 379676 kb
Host smart-ec50d00c-939c-4509-9529-2e859b04d6ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999745680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executab
le.1999745680
Directory /workspace/22.sram_ctrl_executable/latest

Test location /workspace/coverage/default/22.sram_ctrl_lc_escalation.3170266018
Short name T183
Test name
Test status
Simulation time 5137395976 ps
CPU time 32.44 seconds
Started Jun 30 04:44:26 PM PDT 24
Finished Jun 30 04:44:59 PM PDT 24
Peak memory 210920 kb
Host smart-183e2cac-5ee4-4d0e-9d06-73beb133d439
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170266018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_es
calation.3170266018
Directory /workspace/22.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/22.sram_ctrl_max_throughput.975064491
Short name T139
Test name
Test status
Simulation time 744501185 ps
CPU time 43.38 seconds
Started Jun 30 04:44:22 PM PDT 24
Finished Jun 30 04:45:07 PM PDT 24
Peak memory 291940 kb
Host smart-d1c76142-b145-4694-9232-5a9feb3557c3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975064491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.sram_ctrl_max_throughput.975064491
Directory /workspace/22.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_partial_access.3468569541
Short name T731
Test name
Test status
Simulation time 6133934175 ps
CPU time 89.78 seconds
Started Jun 30 04:44:28 PM PDT 24
Finished Jun 30 04:45:58 PM PDT 24
Peak memory 210956 kb
Host smart-6e112171-bf3c-4101-82ec-01e8feb31f02
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468569541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.sram_ctrl_mem_partial_access.3468569541
Directory /workspace/22.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_walk.3338938544
Short name T844
Test name
Test status
Simulation time 44935673215 ps
CPU time 335.91 seconds
Started Jun 30 04:44:25 PM PDT 24
Finished Jun 30 04:50:02 PM PDT 24
Peak memory 210848 kb
Host smart-2efa4907-3f2c-4d03-b59f-10a2b5da23d6
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338938544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr
l_mem_walk.3338938544
Directory /workspace/22.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/22.sram_ctrl_multiple_keys.3060815051
Short name T269
Test name
Test status
Simulation time 12477909574 ps
CPU time 299.4 seconds
Started Jun 30 04:44:29 PM PDT 24
Finished Jun 30 04:49:30 PM PDT 24
Peak memory 338720 kb
Host smart-5545161a-6aac-4f12-a5db-0be8d86ce166
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060815051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi
ple_keys.3060815051
Directory /workspace/22.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access.1145445427
Short name T882
Test name
Test status
Simulation time 842884210 ps
CPU time 99.55 seconds
Started Jun 30 04:44:32 PM PDT 24
Finished Jun 30 04:46:14 PM PDT 24
Peak memory 340612 kb
Host smart-33b5d3af-4c68-4bbc-86bb-0da68d028301
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145445427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
sram_ctrl_partial_access.1145445427
Directory /workspace/22.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.2896867307
Short name T461
Test name
Test status
Simulation time 18515970901 ps
CPU time 466.15 seconds
Started Jun 30 04:44:18 PM PDT 24
Finished Jun 30 04:52:05 PM PDT 24
Peak memory 202716 kb
Host smart-3569deb9-9957-4f81-9d9f-270305d91b78
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896867307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 22.sram_ctrl_partial_access_b2b.2896867307
Directory /workspace/22.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/22.sram_ctrl_ram_cfg.4063270848
Short name T410
Test name
Test status
Simulation time 831345738 ps
CPU time 3.66 seconds
Started Jun 30 04:44:29 PM PDT 24
Finished Jun 30 04:44:34 PM PDT 24
Peak memory 202692 kb
Host smart-18477faa-07f9-4744-a7ab-2651c8c4efbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063270848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.4063270848
Directory /workspace/22.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/22.sram_ctrl_regwen.2268583535
Short name T468
Test name
Test status
Simulation time 14475490781 ps
CPU time 84.93 seconds
Started Jun 30 04:44:27 PM PDT 24
Finished Jun 30 04:45:52 PM PDT 24
Peak memory 290924 kb
Host smart-0e1eb261-3003-46fe-8544-0b3bf206f1d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268583535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.2268583535
Directory /workspace/22.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/22.sram_ctrl_smoke.242216456
Short name T614
Test name
Test status
Simulation time 1321331783 ps
CPU time 18.85 seconds
Started Jun 30 04:44:21 PM PDT 24
Finished Jun 30 04:44:41 PM PDT 24
Peak memory 202624 kb
Host smart-75160d4d-8b1f-44c9-b651-613d7d857bb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242216456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.242216456
Directory /workspace/22.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all.489649319
Short name T658
Test name
Test status
Simulation time 136204855081 ps
CPU time 4057.24 seconds
Started Jun 30 04:44:21 PM PDT 24
Finished Jun 30 05:51:59 PM PDT 24
Peak memory 380604 kb
Host smart-b7ce9df7-c28d-46a2-b061-dd5dc76e9845
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489649319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 22.sram_ctrl_stress_all.489649319
Directory /workspace/22.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.2154701335
Short name T485
Test name
Test status
Simulation time 1580959872 ps
CPU time 179.01 seconds
Started Jun 30 04:44:28 PM PDT 24
Finished Jun 30 04:47:27 PM PDT 24
Peak memory 362476 kb
Host smart-4ba007c9-217f-440e-a676-eabbecf086ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2154701335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.2154701335
Directory /workspace/22.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_pipeline.1374255644
Short name T919
Test name
Test status
Simulation time 13182225012 ps
CPU time 271.87 seconds
Started Jun 30 04:44:13 PM PDT 24
Finished Jun 30 04:48:46 PM PDT 24
Peak memory 202696 kb
Host smart-cf5fe1a4-6ff3-4cb7-acca-5bb751514bb5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374255644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.sram_ctrl_stress_pipeline.1374255644
Directory /workspace/22.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.3567174454
Short name T243
Test name
Test status
Simulation time 3294564005 ps
CPU time 97.26 seconds
Started Jun 30 04:44:27 PM PDT 24
Finished Jun 30 04:46:05 PM PDT 24
Peak memory 335512 kb
Host smart-499eecb8-d200-4443-821e-2020aa18d44c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567174454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.3567174454
Directory /workspace/22.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/23.sram_ctrl_access_during_key_req.3619839632
Short name T90
Test name
Test status
Simulation time 21331806278 ps
CPU time 2082.7 seconds
Started Jun 30 04:44:25 PM PDT 24
Finished Jun 30 05:19:09 PM PDT 24
Peak memory 379604 kb
Host smart-5e510347-0667-4aee-b4bc-5edc08672259
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619839632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.sram_ctrl_access_during_key_req.3619839632
Directory /workspace/23.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/23.sram_ctrl_alert_test.1711872061
Short name T642
Test name
Test status
Simulation time 20851785 ps
CPU time 0.67 seconds
Started Jun 30 04:44:38 PM PDT 24
Finished Jun 30 04:44:40 PM PDT 24
Peak memory 202204 kb
Host smart-edb6c4a8-768a-4577-88a6-ba655314719b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711872061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.sram_ctrl_alert_test.1711872061
Directory /workspace/23.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sram_ctrl_bijection.8826971
Short name T837
Test name
Test status
Simulation time 88362781826 ps
CPU time 2020.63 seconds
Started Jun 30 04:44:21 PM PDT 24
Finished Jun 30 05:18:03 PM PDT 24
Peak memory 203288 kb
Host smart-4d0950dc-ebb8-4322-9cb6-dfb69bb67e96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8826971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijecti
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection.8826971
Directory /workspace/23.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/23.sram_ctrl_executable.3794749945
Short name T828
Test name
Test status
Simulation time 21728731347 ps
CPU time 1017.96 seconds
Started Jun 30 04:44:33 PM PDT 24
Finished Jun 30 05:01:33 PM PDT 24
Peak memory 367308 kb
Host smart-0bc5554a-6e6f-483d-81cc-11b2e0aa0ff1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794749945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab
le.3794749945
Directory /workspace/23.sram_ctrl_executable/latest

Test location /workspace/coverage/default/23.sram_ctrl_lc_escalation.1890501658
Short name T691
Test name
Test status
Simulation time 28914385693 ps
CPU time 77.56 seconds
Started Jun 30 04:44:29 PM PDT 24
Finished Jun 30 04:45:47 PM PDT 24
Peak memory 202768 kb
Host smart-e02b2b00-2533-44dc-b088-a3e21a2e8dda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890501658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_es
calation.1890501658
Directory /workspace/23.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/23.sram_ctrl_max_throughput.3005213544
Short name T633
Test name
Test status
Simulation time 756486881 ps
CPU time 44.99 seconds
Started Jun 30 04:44:25 PM PDT 24
Finished Jun 30 04:45:10 PM PDT 24
Peak memory 289876 kb
Host smart-370c8adb-660c-4b21-9f11-952e6850d746
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005213544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.sram_ctrl_max_throughput.3005213544
Directory /workspace/23.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_partial_access.2083308577
Short name T816
Test name
Test status
Simulation time 5584398902 ps
CPU time 90.84 seconds
Started Jun 30 04:44:30 PM PDT 24
Finished Jun 30 04:46:01 PM PDT 24
Peak memory 210908 kb
Host smart-817b71be-d7ad-4faf-a55b-f7da75cef8c4
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083308577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_mem_partial_access.2083308577
Directory /workspace/23.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_walk.2035396716
Short name T57
Test name
Test status
Simulation time 41317293541 ps
CPU time 182.75 seconds
Started Jun 30 04:44:31 PM PDT 24
Finished Jun 30 04:47:35 PM PDT 24
Peak memory 210860 kb
Host smart-4cc54934-9669-49c4-9aa5-b0c394e362c5
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035396716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr
l_mem_walk.2035396716
Directory /workspace/23.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/23.sram_ctrl_multiple_keys.2966388236
Short name T134
Test name
Test status
Simulation time 15785140747 ps
CPU time 999.78 seconds
Started Jun 30 04:44:30 PM PDT 24
Finished Jun 30 05:01:11 PM PDT 24
Peak memory 381692 kb
Host smart-d57d337f-ea58-4d88-b344-a96670e65eaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966388236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi
ple_keys.2966388236
Directory /workspace/23.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access.2585636735
Short name T298
Test name
Test status
Simulation time 1056497409 ps
CPU time 143.39 seconds
Started Jun 30 04:44:32 PM PDT 24
Finished Jun 30 04:46:58 PM PDT 24
Peak memory 356104 kb
Host smart-7980eb09-857c-4913-8093-db0eaa973a9f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585636735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
sram_ctrl_partial_access.2585636735
Directory /workspace/23.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.2989229228
Short name T349
Test name
Test status
Simulation time 90528819642 ps
CPU time 316.21 seconds
Started Jun 30 04:44:29 PM PDT 24
Finished Jun 30 04:49:46 PM PDT 24
Peak memory 203072 kb
Host smart-6c9b4114-e2b1-46ab-934c-60f2e6572034
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989229228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 23.sram_ctrl_partial_access_b2b.2989229228
Directory /workspace/23.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/23.sram_ctrl_ram_cfg.2386819916
Short name T207
Test name
Test status
Simulation time 910638101 ps
CPU time 3.42 seconds
Started Jun 30 04:44:31 PM PDT 24
Finished Jun 30 04:44:36 PM PDT 24
Peak memory 202656 kb
Host smart-5cb4ad1b-1e7a-4c59-a313-33af8802f995
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386819916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.2386819916
Directory /workspace/23.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/23.sram_ctrl_regwen.1030698730
Short name T504
Test name
Test status
Simulation time 11172885828 ps
CPU time 594.28 seconds
Started Jun 30 04:44:31 PM PDT 24
Finished Jun 30 04:54:27 PM PDT 24
Peak memory 377592 kb
Host smart-cfd5837d-08d0-48d1-9704-f5a02fb138a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030698730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.1030698730
Directory /workspace/23.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/23.sram_ctrl_smoke.2734354710
Short name T165
Test name
Test status
Simulation time 3190224246 ps
CPU time 112.71 seconds
Started Jun 30 04:44:29 PM PDT 24
Finished Jun 30 04:46:23 PM PDT 24
Peak memory 348812 kb
Host smart-2f504c74-3580-4bf3-8892-4560ec6289bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734354710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.2734354710
Directory /workspace/23.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_all.3012329946
Short name T737
Test name
Test status
Simulation time 86694461960 ps
CPU time 7225.51 seconds
Started Jun 30 04:44:31 PM PDT 24
Finished Jun 30 06:44:58 PM PDT 24
Peak memory 380696 kb
Host smart-19b44120-5f87-412a-aba6-75900479f7bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012329946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 23.sram_ctrl_stress_all.3012329946
Directory /workspace/23.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.520976795
Short name T113
Test name
Test status
Simulation time 2008855677 ps
CPU time 15.57 seconds
Started Jun 30 04:44:32 PM PDT 24
Finished Jun 30 04:44:49 PM PDT 24
Peak memory 210900 kb
Host smart-085cd7a7-d6b2-4a4b-8302-4ac214955f4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=520976795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.520976795
Directory /workspace/23.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_pipeline.2499404115
Short name T179
Test name
Test status
Simulation time 14421232245 ps
CPU time 273.39 seconds
Started Jun 30 04:44:26 PM PDT 24
Finished Jun 30 04:49:00 PM PDT 24
Peak memory 202708 kb
Host smart-01121835-e27b-4dd8-881a-832377cfef36
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499404115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_stress_pipeline.2499404115
Directory /workspace/23.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.2803999083
Short name T906
Test name
Test status
Simulation time 5686394445 ps
CPU time 54.88 seconds
Started Jun 30 04:44:26 PM PDT 24
Finished Jun 30 04:45:21 PM PDT 24
Peak memory 307708 kb
Host smart-5eac9885-96aa-4e5e-a0d9-f7207569ee50
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803999083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.2803999083
Directory /workspace/23.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/24.sram_ctrl_access_during_key_req.433977383
Short name T440
Test name
Test status
Simulation time 9237220443 ps
CPU time 460.46 seconds
Started Jun 30 04:44:34 PM PDT 24
Finished Jun 30 04:52:16 PM PDT 24
Peak memory 376460 kb
Host smart-22678eba-852c-458d-914b-60c36fa080b8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433977383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 24.sram_ctrl_access_during_key_req.433977383
Directory /workspace/24.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/24.sram_ctrl_alert_test.2552817309
Short name T834
Test name
Test status
Simulation time 46849563 ps
CPU time 0.68 seconds
Started Jun 30 04:44:25 PM PDT 24
Finished Jun 30 04:44:26 PM PDT 24
Peak memory 202440 kb
Host smart-44bcbe28-237b-4e46-9a90-0fddd505e284
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552817309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.sram_ctrl_alert_test.2552817309
Directory /workspace/24.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sram_ctrl_bijection.1392909200
Short name T777
Test name
Test status
Simulation time 265236110422 ps
CPU time 2164.16 seconds
Started Jun 30 04:44:31 PM PDT 24
Finished Jun 30 05:20:37 PM PDT 24
Peak memory 203368 kb
Host smart-0419526f-e8e2-4de0-9d5a-e92ceeb6ca48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392909200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection
.1392909200
Directory /workspace/24.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/24.sram_ctrl_executable.2263117401
Short name T592
Test name
Test status
Simulation time 9546651784 ps
CPU time 494.16 seconds
Started Jun 30 04:44:37 PM PDT 24
Finished Jun 30 04:52:52 PM PDT 24
Peak memory 368424 kb
Host smart-bc15bfb5-533e-49d1-aa02-a0d80aeb694f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263117401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executab
le.2263117401
Directory /workspace/24.sram_ctrl_executable/latest

Test location /workspace/coverage/default/24.sram_ctrl_lc_escalation.2571247934
Short name T887
Test name
Test status
Simulation time 2523396100 ps
CPU time 18.87 seconds
Started Jun 30 04:44:36 PM PDT 24
Finished Jun 30 04:44:56 PM PDT 24
Peak memory 202720 kb
Host smart-002440fb-913b-475d-8d9d-4ca0a424c88b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571247934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_es
calation.2571247934
Directory /workspace/24.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/24.sram_ctrl_max_throughput.2783711429
Short name T403
Test name
Test status
Simulation time 12734628491 ps
CPU time 163.81 seconds
Started Jun 30 04:44:35 PM PDT 24
Finished Jun 30 04:47:20 PM PDT 24
Peak memory 370748 kb
Host smart-5342dddd-0ac8-44db-b57f-e49b86ddbc15
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783711429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.sram_ctrl_max_throughput.2783711429
Directory /workspace/24.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_partial_access.3427517260
Short name T236
Test name
Test status
Simulation time 12780678198 ps
CPU time 152.34 seconds
Started Jun 30 04:44:32 PM PDT 24
Finished Jun 30 04:47:05 PM PDT 24
Peak memory 210972 kb
Host smart-f70b0b61-bbac-4c46-84bd-b509d5385fc2
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427517260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.sram_ctrl_mem_partial_access.3427517260
Directory /workspace/24.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_walk.532246631
Short name T830
Test name
Test status
Simulation time 276768929914 ps
CPU time 350.22 seconds
Started Jun 30 04:44:33 PM PDT 24
Finished Jun 30 04:50:26 PM PDT 24
Peak memory 203756 kb
Host smart-e46eea9c-d147-43fe-b6eb-90aa176d044e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532246631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl
_mem_walk.532246631
Directory /workspace/24.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/24.sram_ctrl_multiple_keys.3856790510
Short name T319
Test name
Test status
Simulation time 31463072213 ps
CPU time 338.46 seconds
Started Jun 30 04:44:26 PM PDT 24
Finished Jun 30 04:50:05 PM PDT 24
Peak memory 359196 kb
Host smart-3f3fdae5-e75f-41a9-9e01-ca32961ef15b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856790510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi
ple_keys.3856790510
Directory /workspace/24.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access.3770237292
Short name T438
Test name
Test status
Simulation time 8150969928 ps
CPU time 15.15 seconds
Started Jun 30 04:44:33 PM PDT 24
Finished Jun 30 04:44:51 PM PDT 24
Peak memory 202744 kb
Host smart-fd880e49-ae8c-4e42-bcbd-1942bba4f4a8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770237292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
sram_ctrl_partial_access.3770237292
Directory /workspace/24.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.1515548018
Short name T109
Test name
Test status
Simulation time 80389183356 ps
CPU time 515.07 seconds
Started Jun 30 04:44:33 PM PDT 24
Finished Jun 30 04:53:10 PM PDT 24
Peak memory 202800 kb
Host smart-61d3f808-b174-4b74-9635-7831d0248676
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515548018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 24.sram_ctrl_partial_access_b2b.1515548018
Directory /workspace/24.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/24.sram_ctrl_ram_cfg.2492557698
Short name T649
Test name
Test status
Simulation time 346783364 ps
CPU time 3.3 seconds
Started Jun 30 04:44:29 PM PDT 24
Finished Jun 30 04:44:33 PM PDT 24
Peak memory 202644 kb
Host smart-4ec2774a-708b-49b8-bea1-8424b6059574
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492557698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.2492557698
Directory /workspace/24.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/24.sram_ctrl_regwen.2807641078
Short name T897
Test name
Test status
Simulation time 101964510415 ps
CPU time 1076.23 seconds
Started Jun 30 04:44:32 PM PDT 24
Finished Jun 30 05:02:30 PM PDT 24
Peak memory 374592 kb
Host smart-7a49852e-aff9-418c-bc42-45106a703999
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807641078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.2807641078
Directory /workspace/24.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/24.sram_ctrl_smoke.16605687
Short name T304
Test name
Test status
Simulation time 1141231538 ps
CPU time 89.86 seconds
Started Jun 30 04:44:32 PM PDT 24
Finished Jun 30 04:46:03 PM PDT 24
Peak memory 336568 kb
Host smart-5236a93d-ffdf-4a0e-b33c-69305c1c5314
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16605687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.16605687
Directory /workspace/24.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_all.4251074118
Short name T792
Test name
Test status
Simulation time 155575161269 ps
CPU time 2921.14 seconds
Started Jun 30 04:44:29 PM PDT 24
Finished Jun 30 05:33:11 PM PDT 24
Peak memory 386772 kb
Host smart-3a014d81-a2a2-4839-9ce5-d9ee295b6e79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251074118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 24.sram_ctrl_stress_all.4251074118
Directory /workspace/24.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.1807389369
Short name T51
Test name
Test status
Simulation time 10900052453 ps
CPU time 23.48 seconds
Started Jun 30 04:44:29 PM PDT 24
Finished Jun 30 04:44:53 PM PDT 24
Peak memory 212984 kb
Host smart-fea696e1-1162-4a6c-8842-eb8589e4d993
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1807389369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.1807389369
Directory /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_pipeline.249643472
Short name T235
Test name
Test status
Simulation time 11777210493 ps
CPU time 217.51 seconds
Started Jun 30 04:44:30 PM PDT 24
Finished Jun 30 04:48:08 PM PDT 24
Peak memory 202752 kb
Host smart-501fdf98-88ce-49ef-83d9-9a642a9f021e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249643472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.sram_ctrl_stress_pipeline.249643472
Directory /workspace/24.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1696728929
Short name T414
Test name
Test status
Simulation time 709785735 ps
CPU time 14.62 seconds
Started Jun 30 04:44:33 PM PDT 24
Finished Jun 30 04:44:50 PM PDT 24
Peak memory 240304 kb
Host smart-fecb30a7-d663-49ab-8dd4-15d045e93fff
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696728929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.1696728929
Directory /workspace/24.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/25.sram_ctrl_access_during_key_req.2937115991
Short name T317
Test name
Test status
Simulation time 16320666754 ps
CPU time 460.84 seconds
Started Jun 30 04:44:33 PM PDT 24
Finished Jun 30 04:52:16 PM PDT 24
Peak memory 378032 kb
Host smart-4525baa9-3686-41c9-b841-b9c39e03aade
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937115991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.sram_ctrl_access_during_key_req.2937115991
Directory /workspace/25.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/25.sram_ctrl_alert_test.2031269852
Short name T576
Test name
Test status
Simulation time 25569559 ps
CPU time 0.74 seconds
Started Jun 30 04:44:32 PM PDT 24
Finished Jun 30 04:44:34 PM PDT 24
Peak memory 202480 kb
Host smart-0ef34956-5ef8-44ee-93ed-bffeee10175d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031269852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.sram_ctrl_alert_test.2031269852
Directory /workspace/25.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sram_ctrl_bijection.967760752
Short name T856
Test name
Test status
Simulation time 168252033801 ps
CPU time 866.65 seconds
Started Jun 30 04:44:27 PM PDT 24
Finished Jun 30 04:58:54 PM PDT 24
Peak memory 202876 kb
Host smart-8626c275-e188-4e3f-a4fb-78a6e11eeb86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967760752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection.
967760752
Directory /workspace/25.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/25.sram_ctrl_executable.3458159202
Short name T796
Test name
Test status
Simulation time 5509935169 ps
CPU time 185.28 seconds
Started Jun 30 04:44:27 PM PDT 24
Finished Jun 30 04:47:33 PM PDT 24
Peak memory 327832 kb
Host smart-6424954b-a04c-479b-9d28-711e2ead5f1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458159202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executab
le.3458159202
Directory /workspace/25.sram_ctrl_executable/latest

Test location /workspace/coverage/default/25.sram_ctrl_lc_escalation.305244211
Short name T160
Test name
Test status
Simulation time 53696363921 ps
CPU time 60.75 seconds
Started Jun 30 04:44:30 PM PDT 24
Finished Jun 30 04:45:32 PM PDT 24
Peak memory 210964 kb
Host smart-1b7ac926-ad30-44bd-8fd4-6d7796d58789
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305244211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_esc
alation.305244211
Directory /workspace/25.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/25.sram_ctrl_max_throughput.102854482
Short name T577
Test name
Test status
Simulation time 800350102 ps
CPU time 170.41 seconds
Started Jun 30 04:44:32 PM PDT 24
Finished Jun 30 04:47:23 PM PDT 24
Peak memory 370228 kb
Host smart-207c9595-1cd6-4576-a2ae-43840e786bbf
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102854482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.sram_ctrl_max_throughput.102854482
Directory /workspace/25.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_partial_access.3047508753
Short name T49
Test name
Test status
Simulation time 5516998581 ps
CPU time 79.15 seconds
Started Jun 30 04:44:34 PM PDT 24
Finished Jun 30 04:45:55 PM PDT 24
Peak memory 210888 kb
Host smart-29e10782-acfd-471a-ae95-955041b6ce11
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047508753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_mem_partial_access.3047508753
Directory /workspace/25.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_walk.3321270041
Short name T644
Test name
Test status
Simulation time 82765325708 ps
CPU time 353.02 seconds
Started Jun 30 04:44:32 PM PDT 24
Finished Jun 30 04:50:27 PM PDT 24
Peak memory 210904 kb
Host smart-692f8c97-b452-4378-bae5-55da7c77abd9
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321270041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr
l_mem_walk.3321270041
Directory /workspace/25.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/25.sram_ctrl_multiple_keys.3713134365
Short name T428
Test name
Test status
Simulation time 200072091627 ps
CPU time 1151.84 seconds
Started Jun 30 04:44:33 PM PDT 24
Finished Jun 30 05:03:47 PM PDT 24
Peak memory 374560 kb
Host smart-fc6ca24d-97ee-4428-800a-49e3d95e5cee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713134365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi
ple_keys.3713134365
Directory /workspace/25.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access.3393214999
Short name T360
Test name
Test status
Simulation time 2180341409 ps
CPU time 14.45 seconds
Started Jun 30 04:44:27 PM PDT 24
Finished Jun 30 04:44:42 PM PDT 24
Peak memory 202604 kb
Host smart-730ba1a7-ccdb-4fd7-9d67-d639ce8c917a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393214999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
sram_ctrl_partial_access.3393214999
Directory /workspace/25.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3873710861
Short name T241
Test name
Test status
Simulation time 5752402832 ps
CPU time 305.14 seconds
Started Jun 30 04:44:32 PM PDT 24
Finished Jun 30 04:49:38 PM PDT 24
Peak memory 202676 kb
Host smart-de22a346-d455-4ddf-824e-0a2eb9b4dac3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873710861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 25.sram_ctrl_partial_access_b2b.3873710861
Directory /workspace/25.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/25.sram_ctrl_ram_cfg.1519762513
Short name T234
Test name
Test status
Simulation time 2578901471 ps
CPU time 4.29 seconds
Started Jun 30 04:44:36 PM PDT 24
Finished Jun 30 04:44:41 PM PDT 24
Peak memory 202836 kb
Host smart-b0875e5a-a47f-4e07-a380-0a71414a07d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519762513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.1519762513
Directory /workspace/25.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/25.sram_ctrl_regwen.2862333865
Short name T580
Test name
Test status
Simulation time 39282253309 ps
CPU time 704.79 seconds
Started Jun 30 04:44:33 PM PDT 24
Finished Jun 30 04:56:20 PM PDT 24
Peak memory 378660 kb
Host smart-56fbcfdd-d545-4e90-8057-e334d67672db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862333865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.2862333865
Directory /workspace/25.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/25.sram_ctrl_smoke.3242133067
Short name T224
Test name
Test status
Simulation time 6369898881 ps
CPU time 16.58 seconds
Started Jun 30 04:44:31 PM PDT 24
Finished Jun 30 04:44:48 PM PDT 24
Peak memory 202696 kb
Host smart-31bcd16b-2efc-4b6e-b087-812d04dbbd83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242133067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.3242133067
Directory /workspace/25.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all.456781328
Short name T762
Test name
Test status
Simulation time 1562945870930 ps
CPU time 7624.66 seconds
Started Jun 30 04:44:34 PM PDT 24
Finished Jun 30 06:51:41 PM PDT 24
Peak memory 387844 kb
Host smart-fcdf628e-478f-4491-9fc6-7140c4d0eb03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456781328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 25.sram_ctrl_stress_all.456781328
Directory /workspace/25.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2053042615
Short name T730
Test name
Test status
Simulation time 3403432241 ps
CPU time 65.63 seconds
Started Jun 30 04:44:36 PM PDT 24
Finished Jun 30 04:45:43 PM PDT 24
Peak memory 211024 kb
Host smart-6bad8a2b-1ffa-4645-a612-aa9f04a563e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2053042615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.2053042615
Directory /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_pipeline.3135940573
Short name T472
Test name
Test status
Simulation time 25262797154 ps
CPU time 478.93 seconds
Started Jun 30 04:44:30 PM PDT 24
Finished Jun 30 04:52:30 PM PDT 24
Peak memory 202736 kb
Host smart-52b73a27-220d-4848-a91c-648ef2cafcb0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135940573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_stress_pipeline.3135940573
Directory /workspace/25.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.2266428411
Short name T375
Test name
Test status
Simulation time 1549485035 ps
CPU time 64.63 seconds
Started Jun 30 04:44:30 PM PDT 24
Finished Jun 30 04:45:35 PM PDT 24
Peak memory 327392 kb
Host smart-8293a5dd-fcdd-4652-9c7e-eaafc9f21bfe
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266428411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.2266428411
Directory /workspace/25.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/26.sram_ctrl_access_during_key_req.1356924512
Short name T876
Test name
Test status
Simulation time 31424279368 ps
CPU time 936.69 seconds
Started Jun 30 04:44:34 PM PDT 24
Finished Jun 30 05:00:13 PM PDT 24
Peak memory 376804 kb
Host smart-d2faf891-cdf0-4923-8a57-2dd9364dd64d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356924512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.sram_ctrl_access_during_key_req.1356924512
Directory /workspace/26.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/26.sram_ctrl_alert_test.1636205603
Short name T433
Test name
Test status
Simulation time 68383766 ps
CPU time 0.66 seconds
Started Jun 30 04:44:42 PM PDT 24
Finished Jun 30 04:44:43 PM PDT 24
Peak memory 202472 kb
Host smart-d271af05-0e80-49bd-b700-b5bf65588753
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636205603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.sram_ctrl_alert_test.1636205603
Directory /workspace/26.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sram_ctrl_bijection.2397718068
Short name T255
Test name
Test status
Simulation time 520492617635 ps
CPU time 2313.26 seconds
Started Jun 30 04:44:35 PM PDT 24
Finished Jun 30 05:23:10 PM PDT 24
Peak memory 202848 kb
Host smart-358ee9f7-d0b6-4ddf-8112-9cdaa04f8bbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397718068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection
.2397718068
Directory /workspace/26.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/26.sram_ctrl_executable.1434129919
Short name T681
Test name
Test status
Simulation time 11518284146 ps
CPU time 726.89 seconds
Started Jun 30 04:44:34 PM PDT 24
Finished Jun 30 04:56:43 PM PDT 24
Peak memory 379208 kb
Host smart-07d9d36e-1f87-49f0-a394-aab88c63d350
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434129919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executab
le.1434129919
Directory /workspace/26.sram_ctrl_executable/latest

Test location /workspace/coverage/default/26.sram_ctrl_lc_escalation.1423434650
Short name T865
Test name
Test status
Simulation time 13257673428 ps
CPU time 80.66 seconds
Started Jun 30 04:44:30 PM PDT 24
Finished Jun 30 04:45:52 PM PDT 24
Peak memory 202784 kb
Host smart-9afee4da-90a6-4d9c-85df-c52d112fa3a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423434650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_es
calation.1423434650
Directory /workspace/26.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/26.sram_ctrl_max_throughput.686753714
Short name T690
Test name
Test status
Simulation time 727477882 ps
CPU time 30.91 seconds
Started Jun 30 04:44:33 PM PDT 24
Finished Jun 30 04:45:06 PM PDT 24
Peak memory 290912 kb
Host smart-83ab5c57-f422-46b5-8dc7-44f23e1cf2c8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686753714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.sram_ctrl_max_throughput.686753714
Directory /workspace/26.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_partial_access.1501716153
Short name T588
Test name
Test status
Simulation time 3314350506 ps
CPU time 133.02 seconds
Started Jun 30 04:44:38 PM PDT 24
Finished Jun 30 04:46:52 PM PDT 24
Peak memory 219104 kb
Host smart-6be5037b-c4e1-48c8-96ba-ae32f8945d85
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501716153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_mem_partial_access.1501716153
Directory /workspace/26.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_walk.765846862
Short name T272
Test name
Test status
Simulation time 44908252761 ps
CPU time 358.08 seconds
Started Jun 30 04:44:34 PM PDT 24
Finished Jun 30 04:50:34 PM PDT 24
Peak memory 210976 kb
Host smart-bc94c61b-f4cb-41c0-8808-0bc5c3fd2f98
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765846862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl
_mem_walk.765846862
Directory /workspace/26.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/26.sram_ctrl_multiple_keys.4019187443
Short name T402
Test name
Test status
Simulation time 39918000034 ps
CPU time 837.36 seconds
Started Jun 30 04:44:27 PM PDT 24
Finished Jun 30 04:58:25 PM PDT 24
Peak memory 341988 kb
Host smart-eafe5401-06b6-49f6-8f5e-706f8349bc56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019187443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi
ple_keys.4019187443
Directory /workspace/26.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access.4086766685
Short name T542
Test name
Test status
Simulation time 5117575048 ps
CPU time 24.44 seconds
Started Jun 30 04:44:37 PM PDT 24
Finished Jun 30 04:45:02 PM PDT 24
Peak memory 202752 kb
Host smart-aecb46b9-b312-4c37-a347-766928d926ac
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086766685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
sram_ctrl_partial_access.4086766685
Directory /workspace/26.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.681062100
Short name T230
Test name
Test status
Simulation time 6585408389 ps
CPU time 182.17 seconds
Started Jun 30 04:44:32 PM PDT 24
Finished Jun 30 04:47:36 PM PDT 24
Peak memory 202756 kb
Host smart-efb03b11-eb2a-4fe5-8842-823fd0354479
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681062100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.sram_ctrl_partial_access_b2b.681062100
Directory /workspace/26.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/26.sram_ctrl_ram_cfg.3979643840
Short name T187
Test name
Test status
Simulation time 675882589 ps
CPU time 3.65 seconds
Started Jun 30 04:44:36 PM PDT 24
Finished Jun 30 04:44:40 PM PDT 24
Peak memory 202712 kb
Host smart-bd58e512-a545-404c-b32f-b0c8df06f416
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979643840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.3979643840
Directory /workspace/26.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/26.sram_ctrl_regwen.2926997540
Short name T839
Test name
Test status
Simulation time 2286191874 ps
CPU time 250.15 seconds
Started Jun 30 04:44:31 PM PDT 24
Finished Jun 30 04:48:42 PM PDT 24
Peak memory 324500 kb
Host smart-f5d3cb13-a338-4e47-8251-db53ae2afa9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926997540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.2926997540
Directory /workspace/26.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/26.sram_ctrl_smoke.2732538553
Short name T291
Test name
Test status
Simulation time 3365390665 ps
CPU time 15.44 seconds
Started Jun 30 04:44:31 PM PDT 24
Finished Jun 30 04:44:48 PM PDT 24
Peak memory 238028 kb
Host smart-a631734f-8007-47a0-807b-e7b49f49f632
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732538553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.2732538553
Directory /workspace/26.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all.2338648671
Short name T333
Test name
Test status
Simulation time 60116692710 ps
CPU time 3005.85 seconds
Started Jun 30 04:44:34 PM PDT 24
Finished Jun 30 05:34:42 PM PDT 24
Peak memory 378892 kb
Host smart-e1980e38-1cda-47f3-8f28-88b7e06ebc34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338648671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 26.sram_ctrl_stress_all.2338648671
Directory /workspace/26.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.307130907
Short name T471
Test name
Test status
Simulation time 1821657925 ps
CPU time 15.33 seconds
Started Jun 30 04:44:32 PM PDT 24
Finished Jun 30 04:44:48 PM PDT 24
Peak memory 210976 kb
Host smart-b41adea7-868e-4085-bf38-ea9e34d16d96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=307130907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.307130907
Directory /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_pipeline.1221603172
Short name T553
Test name
Test status
Simulation time 42991779486 ps
CPU time 230.14 seconds
Started Jun 30 04:44:33 PM PDT 24
Finished Jun 30 04:48:25 PM PDT 24
Peak memory 202744 kb
Host smart-3abdb141-e68c-4912-8f90-102cd53231bd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221603172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_stress_pipeline.1221603172
Directory /workspace/26.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.609229881
Short name T384
Test name
Test status
Simulation time 712982805 ps
CPU time 8.61 seconds
Started Jun 30 04:44:32 PM PDT 24
Finished Jun 30 04:44:43 PM PDT 24
Peak memory 221456 kb
Host smart-6739f43c-8131-4ee6-8e17-f155dba4b4d4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609229881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.sram_ctrl_throughput_w_partial_write.609229881
Directory /workspace/26.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/27.sram_ctrl_access_during_key_req.2273555858
Short name T791
Test name
Test status
Simulation time 6748350082 ps
CPU time 278.89 seconds
Started Jun 30 04:44:35 PM PDT 24
Finished Jun 30 04:49:16 PM PDT 24
Peak memory 325628 kb
Host smart-eaf989e5-cc76-4a41-a2f4-bcea462001c5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273555858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.sram_ctrl_access_during_key_req.2273555858
Directory /workspace/27.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/27.sram_ctrl_alert_test.2233677833
Short name T318
Test name
Test status
Simulation time 52257110 ps
CPU time 0.68 seconds
Started Jun 30 04:44:36 PM PDT 24
Finished Jun 30 04:44:38 PM PDT 24
Peak memory 202244 kb
Host smart-fe953624-dc4e-422e-95b7-85ffbc0a570d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233677833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.sram_ctrl_alert_test.2233677833
Directory /workspace/27.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sram_ctrl_bijection.951340776
Short name T706
Test name
Test status
Simulation time 57732672453 ps
CPU time 1264.73 seconds
Started Jun 30 04:44:37 PM PDT 24
Finished Jun 30 05:05:42 PM PDT 24
Peak memory 203340 kb
Host smart-6296124e-2aea-4ebc-ab75-e98c2cac7d10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951340776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection.
951340776
Directory /workspace/27.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/27.sram_ctrl_executable.121019558
Short name T282
Test name
Test status
Simulation time 16562320969 ps
CPU time 420.83 seconds
Started Jun 30 04:44:32 PM PDT 24
Finished Jun 30 04:51:35 PM PDT 24
Peak memory 370028 kb
Host smart-b94dbc44-8b87-4e27-843e-241f01ac2d40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121019558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executabl
e.121019558
Directory /workspace/27.sram_ctrl_executable/latest

Test location /workspace/coverage/default/27.sram_ctrl_lc_escalation.4230594037
Short name T196
Test name
Test status
Simulation time 27209327873 ps
CPU time 76.16 seconds
Started Jun 30 04:44:33 PM PDT 24
Finished Jun 30 04:45:51 PM PDT 24
Peak memory 202704 kb
Host smart-05fa23ad-998c-4ab7-b626-5efeb9215bc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230594037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_es
calation.4230594037
Directory /workspace/27.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/27.sram_ctrl_max_throughput.2918884357
Short name T138
Test name
Test status
Simulation time 3001189487 ps
CPU time 38.03 seconds
Started Jun 30 04:44:34 PM PDT 24
Finished Jun 30 04:45:14 PM PDT 24
Peak memory 289744 kb
Host smart-298802c0-4970-4988-a08c-caf4b719b058
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918884357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.sram_ctrl_max_throughput.2918884357
Directory /workspace/27.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_partial_access.812019923
Short name T358
Test name
Test status
Simulation time 6114847674 ps
CPU time 178.08 seconds
Started Jun 30 04:44:33 PM PDT 24
Finished Jun 30 04:47:33 PM PDT 24
Peak memory 219064 kb
Host smart-f70eb2fd-f0c2-448f-95e5-e450d7afc58a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812019923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.sram_ctrl_mem_partial_access.812019923
Directory /workspace/27.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_walk.3243593562
Short name T405
Test name
Test status
Simulation time 86071240280 ps
CPU time 363.37 seconds
Started Jun 30 04:44:31 PM PDT 24
Finished Jun 30 04:50:35 PM PDT 24
Peak memory 210820 kb
Host smart-2e166989-32b2-4736-b5f3-d30b870e80df
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243593562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr
l_mem_walk.3243593562
Directory /workspace/27.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/27.sram_ctrl_multiple_keys.124570054
Short name T473
Test name
Test status
Simulation time 61077115356 ps
CPU time 683.21 seconds
Started Jun 30 04:44:34 PM PDT 24
Finished Jun 30 04:55:59 PM PDT 24
Peak memory 357088 kb
Host smart-cac59835-8ec5-4cfd-9197-07f4060553b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124570054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multip
le_keys.124570054
Directory /workspace/27.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access.3586998113
Short name T854
Test name
Test status
Simulation time 5199684897 ps
CPU time 68.14 seconds
Started Jun 30 04:44:38 PM PDT 24
Finished Jun 30 04:45:46 PM PDT 24
Peak memory 308840 kb
Host smart-1a922be0-27df-41b8-bca6-ff7b10b1fc0a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586998113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
sram_ctrl_partial_access.3586998113
Directory /workspace/27.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2486043925
Short name T650
Test name
Test status
Simulation time 25577536737 ps
CPU time 305.19 seconds
Started Jun 30 04:44:37 PM PDT 24
Finished Jun 30 04:49:43 PM PDT 24
Peak memory 202768 kb
Host smart-61c6a43a-e669-4157-ba3a-19d923e98259
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486043925 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 27.sram_ctrl_partial_access_b2b.2486043925
Directory /workspace/27.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/27.sram_ctrl_ram_cfg.1334729711
Short name T465
Test name
Test status
Simulation time 1408448036 ps
CPU time 3.34 seconds
Started Jun 30 04:44:34 PM PDT 24
Finished Jun 30 04:44:40 PM PDT 24
Peak memory 202668 kb
Host smart-0ecc4676-cbc0-4b69-9ae8-f77b2e53e27c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334729711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.1334729711
Directory /workspace/27.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/27.sram_ctrl_regwen.2293506245
Short name T164
Test name
Test status
Simulation time 23841201456 ps
CPU time 1586.93 seconds
Started Jun 30 04:44:33 PM PDT 24
Finished Jun 30 05:11:02 PM PDT 24
Peak memory 377568 kb
Host smart-38543253-fd15-49f6-a3f9-749e5a99e21b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293506245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.2293506245
Directory /workspace/27.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/27.sram_ctrl_smoke.2994782858
Short name T496
Test name
Test status
Simulation time 769405313 ps
CPU time 7.79 seconds
Started Jun 30 04:44:35 PM PDT 24
Finished Jun 30 04:44:44 PM PDT 24
Peak memory 209620 kb
Host smart-d1ba0fe8-7a78-4e78-812c-7566d0d6cc57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994782858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.2994782858
Directory /workspace/27.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all.542588674
Short name T30
Test name
Test status
Simulation time 97521531290 ps
CPU time 2799.08 seconds
Started Jun 30 04:44:37 PM PDT 24
Finished Jun 30 05:31:17 PM PDT 24
Peak memory 372508 kb
Host smart-c79c0688-660b-4b6a-94bb-2de9df8ab142
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542588674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 27.sram_ctrl_stress_all.542588674
Directory /workspace/27.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2591626246
Short name T891
Test name
Test status
Simulation time 2509923789 ps
CPU time 162.84 seconds
Started Jun 30 04:44:33 PM PDT 24
Finished Jun 30 04:47:17 PM PDT 24
Peak memory 334636 kb
Host smart-0c44af84-9bb0-4199-83d2-7346bd40baf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2591626246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.2591626246
Directory /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_pipeline.4168549321
Short name T612
Test name
Test status
Simulation time 24635630863 ps
CPU time 463.05 seconds
Started Jun 30 04:44:37 PM PDT 24
Finished Jun 30 04:52:21 PM PDT 24
Peak memory 202724 kb
Host smart-f7a35acc-064b-48b6-9f61-38de18374541
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168549321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_stress_pipeline.4168549321
Directory /workspace/27.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.3378301190
Short name T561
Test name
Test status
Simulation time 1658042500 ps
CPU time 84.8 seconds
Started Jun 30 04:44:40 PM PDT 24
Finished Jun 30 04:46:05 PM PDT 24
Peak memory 338568 kb
Host smart-142733e6-5776-4342-bd58-73f6053671d9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378301190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.3378301190
Directory /workspace/27.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/28.sram_ctrl_access_during_key_req.2732979709
Short name T603
Test name
Test status
Simulation time 10800294912 ps
CPU time 861.73 seconds
Started Jun 30 04:44:31 PM PDT 24
Finished Jun 30 04:58:55 PM PDT 24
Peak memory 379624 kb
Host smart-3eca5008-0d7a-47e7-a3a3-8c413236699c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732979709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.sram_ctrl_access_during_key_req.2732979709
Directory /workspace/28.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/28.sram_ctrl_alert_test.4017726854
Short name T928
Test name
Test status
Simulation time 11850172 ps
CPU time 0.71 seconds
Started Jun 30 04:44:39 PM PDT 24
Finished Jun 30 04:44:41 PM PDT 24
Peak memory 202272 kb
Host smart-a89de0c3-a6c4-4d1e-80e0-1a79a8db3c5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017726854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.sram_ctrl_alert_test.4017726854
Directory /workspace/28.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sram_ctrl_bijection.952070282
Short name T487
Test name
Test status
Simulation time 152093937092 ps
CPU time 1228.41 seconds
Started Jun 30 04:44:33 PM PDT 24
Finished Jun 30 05:05:04 PM PDT 24
Peak memory 203304 kb
Host smart-a8a5da1c-907e-48ec-89e2-ca947c655786
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952070282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection.
952070282
Directory /workspace/28.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/28.sram_ctrl_executable.959354806
Short name T877
Test name
Test status
Simulation time 15091007553 ps
CPU time 630.11 seconds
Started Jun 30 04:44:29 PM PDT 24
Finished Jun 30 04:55:00 PM PDT 24
Peak memory 362248 kb
Host smart-e135ceb7-767c-4e43-b656-28b54d35de32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959354806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executabl
e.959354806
Directory /workspace/28.sram_ctrl_executable/latest

Test location /workspace/coverage/default/28.sram_ctrl_lc_escalation.979913797
Short name T552
Test name
Test status
Simulation time 60543360734 ps
CPU time 115.86 seconds
Started Jun 30 04:44:40 PM PDT 24
Finished Jun 30 04:46:37 PM PDT 24
Peak memory 202736 kb
Host smart-de5abaed-af21-47e8-a989-4f3eb86b2cb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979913797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_esc
alation.979913797
Directory /workspace/28.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/28.sram_ctrl_max_throughput.426632714
Short name T908
Test name
Test status
Simulation time 708130199 ps
CPU time 6.68 seconds
Started Jun 30 04:44:31 PM PDT 24
Finished Jun 30 04:44:39 PM PDT 24
Peak memory 213676 kb
Host smart-48a18140-2b77-41e5-a832-897233b05f85
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426632714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.sram_ctrl_max_throughput.426632714
Directory /workspace/28.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_partial_access.971119686
Short name T31
Test name
Test status
Simulation time 1425919529 ps
CPU time 77.48 seconds
Started Jun 30 04:44:44 PM PDT 24
Finished Jun 30 04:46:02 PM PDT 24
Peak memory 218944 kb
Host smart-caa89f48-8759-4ed7-b6f8-63179635ab62
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971119686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.sram_ctrl_mem_partial_access.971119686
Directory /workspace/28.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_walk.3464565275
Short name T779
Test name
Test status
Simulation time 4034648348 ps
CPU time 124.68 seconds
Started Jun 30 04:44:36 PM PDT 24
Finished Jun 30 04:46:41 PM PDT 24
Peak memory 210908 kb
Host smart-177023af-d7e7-4c01-9064-0b47c3177089
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464565275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctr
l_mem_walk.3464565275
Directory /workspace/28.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/28.sram_ctrl_multiple_keys.3139043510
Short name T785
Test name
Test status
Simulation time 30264969305 ps
CPU time 413.93 seconds
Started Jun 30 04:44:34 PM PDT 24
Finished Jun 30 04:51:30 PM PDT 24
Peak memory 327508 kb
Host smart-70ea571d-5952-4630-8495-dd317aaeaf67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139043510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi
ple_keys.3139043510
Directory /workspace/28.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access.614812735
Short name T441
Test name
Test status
Simulation time 1662650016 ps
CPU time 85.72 seconds
Started Jun 30 04:44:36 PM PDT 24
Finished Jun 30 04:46:03 PM PDT 24
Peak memory 336500 kb
Host smart-921ed088-d68a-4251-8bb5-254e1a20ff43
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614812735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.s
ram_ctrl_partial_access.614812735
Directory /workspace/28.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.2406518426
Short name T748
Test name
Test status
Simulation time 15500915951 ps
CPU time 228.15 seconds
Started Jun 30 04:44:37 PM PDT 24
Finished Jun 30 04:48:26 PM PDT 24
Peak memory 202744 kb
Host smart-6abfab98-f2d0-4f5e-92fe-db1767a1018d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406518426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 28.sram_ctrl_partial_access_b2b.2406518426
Directory /workspace/28.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/28.sram_ctrl_ram_cfg.2723344165
Short name T27
Test name
Test status
Simulation time 349763572 ps
CPU time 3.32 seconds
Started Jun 30 04:44:33 PM PDT 24
Finished Jun 30 04:44:39 PM PDT 24
Peak memory 202724 kb
Host smart-e27b2516-c33d-4de6-876c-ca8683a3a2c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723344165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.2723344165
Directory /workspace/28.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/28.sram_ctrl_regwen.3345935601
Short name T40
Test name
Test status
Simulation time 31422945639 ps
CPU time 1076.69 seconds
Started Jun 30 04:44:35 PM PDT 24
Finished Jun 30 05:02:33 PM PDT 24
Peak memory 377788 kb
Host smart-e90610d7-bbb8-4027-bc97-3be5dcaaf56f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345935601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.3345935601
Directory /workspace/28.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/28.sram_ctrl_smoke.795183633
Short name T666
Test name
Test status
Simulation time 776401542 ps
CPU time 6.47 seconds
Started Jun 30 04:44:34 PM PDT 24
Finished Jun 30 04:44:42 PM PDT 24
Peak memory 202296 kb
Host smart-deafde62-7297-45b5-8555-6d56865d0f1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795183633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.795183633
Directory /workspace/28.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all.2036918668
Short name T634
Test name
Test status
Simulation time 136110397683 ps
CPU time 5120.04 seconds
Started Jun 30 04:44:40 PM PDT 24
Finished Jun 30 06:10:02 PM PDT 24
Peak memory 381628 kb
Host smart-f0e54f45-346f-403d-bc7e-e36861008c44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036918668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 28.sram_ctrl_stress_all.2036918668
Directory /workspace/28.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.4223374586
Short name T497
Test name
Test status
Simulation time 8524231112 ps
CPU time 93.27 seconds
Started Jun 30 04:44:45 PM PDT 24
Finished Jun 30 04:46:19 PM PDT 24
Peak memory 292404 kb
Host smart-22b63912-5928-46e7-b219-0acad00e1798
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4223374586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.4223374586
Directory /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_pipeline.3474591234
Short name T371
Test name
Test status
Simulation time 5529824550 ps
CPU time 457.41 seconds
Started Jun 30 04:44:37 PM PDT 24
Finished Jun 30 04:52:15 PM PDT 24
Peak memory 202804 kb
Host smart-ac1b0762-6c2d-4143-9bc9-347193d0bb4d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474591234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.sram_ctrl_stress_pipeline.3474591234
Directory /workspace/28.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.2242639852
Short name T148
Test name
Test status
Simulation time 2884407699 ps
CPU time 29.26 seconds
Started Jun 30 04:44:36 PM PDT 24
Finished Jun 30 04:45:06 PM PDT 24
Peak memory 280412 kb
Host smart-71758d13-57a5-429d-87ce-37666635046c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242639852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.2242639852
Directory /workspace/28.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/29.sram_ctrl_access_during_key_req.1959008519
Short name T607
Test name
Test status
Simulation time 9762913143 ps
CPU time 413.26 seconds
Started Jun 30 04:44:41 PM PDT 24
Finished Jun 30 04:51:36 PM PDT 24
Peak memory 335584 kb
Host smart-902a7ec2-5927-43c2-b54b-ef9c16bd44d7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959008519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.sram_ctrl_access_during_key_req.1959008519
Directory /workspace/29.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/29.sram_ctrl_alert_test.3365841556
Short name T378
Test name
Test status
Simulation time 44664629 ps
CPU time 0.69 seconds
Started Jun 30 04:44:43 PM PDT 24
Finished Jun 30 04:44:44 PM PDT 24
Peak memory 202260 kb
Host smart-3b28645a-30ee-490c-90d9-0592dcdd29d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365841556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.sram_ctrl_alert_test.3365841556
Directory /workspace/29.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sram_ctrl_bijection.8928722
Short name T347
Test name
Test status
Simulation time 42756489731 ps
CPU time 1482.44 seconds
Started Jun 30 04:44:45 PM PDT 24
Finished Jun 30 05:09:28 PM PDT 24
Peak memory 203468 kb
Host smart-e22f7a8f-ac07-4458-8e18-314425f3d099
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8928722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijecti
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection.8928722
Directory /workspace/29.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/29.sram_ctrl_executable.3920927578
Short name T637
Test name
Test status
Simulation time 13574320557 ps
CPU time 444.14 seconds
Started Jun 30 04:44:41 PM PDT 24
Finished Jun 30 04:52:06 PM PDT 24
Peak memory 375536 kb
Host smart-3a3d9ffd-63f1-4998-ab38-bdfa647536f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920927578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab
le.3920927578
Directory /workspace/29.sram_ctrl_executable/latest

Test location /workspace/coverage/default/29.sram_ctrl_lc_escalation.2251563346
Short name T453
Test name
Test status
Simulation time 665281856 ps
CPU time 4.77 seconds
Started Jun 30 04:44:43 PM PDT 24
Finished Jun 30 04:44:49 PM PDT 24
Peak memory 202528 kb
Host smart-624016f4-41db-44d2-ab9b-1acaf559a76e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251563346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_es
calation.2251563346
Directory /workspace/29.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/29.sram_ctrl_max_throughput.2439606040
Short name T621
Test name
Test status
Simulation time 723419785 ps
CPU time 18.54 seconds
Started Jun 30 04:44:42 PM PDT 24
Finished Jun 30 04:45:02 PM PDT 24
Peak memory 252784 kb
Host smart-70840d08-7330-4c5f-be9c-ee2392a7397b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439606040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.sram_ctrl_max_throughput.2439606040
Directory /workspace/29.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_partial_access.1061506229
Short name T664
Test name
Test status
Simulation time 18865223131 ps
CPU time 149.06 seconds
Started Jun 30 04:44:41 PM PDT 24
Finished Jun 30 04:47:11 PM PDT 24
Peak memory 210932 kb
Host smart-70086e40-83b7-4217-801b-362be6dfa666
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061506229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_mem_partial_access.1061506229
Directory /workspace/29.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_walk.411232741
Short name T48
Test name
Test status
Simulation time 62918412244 ps
CPU time 179.15 seconds
Started Jun 30 04:44:42 PM PDT 24
Finished Jun 30 04:47:43 PM PDT 24
Peak memory 210880 kb
Host smart-5d4cd0ea-4323-4f13-bdbf-cc6e948b75cd
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411232741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl
_mem_walk.411232741
Directory /workspace/29.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/29.sram_ctrl_multiple_keys.3992517196
Short name T238
Test name
Test status
Simulation time 16078231860 ps
CPU time 250.84 seconds
Started Jun 30 04:44:39 PM PDT 24
Finished Jun 30 04:48:50 PM PDT 24
Peak memory 344848 kb
Host smart-e7f9e472-8bb8-4a25-855a-c2a95ba987b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992517196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi
ple_keys.3992517196
Directory /workspace/29.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access.2425907183
Short name T896
Test name
Test status
Simulation time 9146990499 ps
CPU time 26.6 seconds
Started Jun 30 04:44:41 PM PDT 24
Finished Jun 30 04:45:09 PM PDT 24
Peak memory 203108 kb
Host smart-002fa1ff-9308-4a82-8e23-0892c8690682
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425907183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
sram_ctrl_partial_access.2425907183
Directory /workspace/29.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.1849347714
Short name T249
Test name
Test status
Simulation time 31949208116 ps
CPU time 406.54 seconds
Started Jun 30 04:44:44 PM PDT 24
Finished Jun 30 04:51:31 PM PDT 24
Peak memory 202732 kb
Host smart-25c0057b-a18c-4bf0-b528-73a422092f68
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849347714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 29.sram_ctrl_partial_access_b2b.1849347714
Directory /workspace/29.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/29.sram_ctrl_ram_cfg.3766685364
Short name T629
Test name
Test status
Simulation time 350462923 ps
CPU time 3.3 seconds
Started Jun 30 04:44:41 PM PDT 24
Finished Jun 30 04:44:45 PM PDT 24
Peak memory 202736 kb
Host smart-907e905b-45a8-4864-85bd-627b9dd9e0ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766685364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.3766685364
Directory /workspace/29.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/29.sram_ctrl_regwen.4273073523
Short name T841
Test name
Test status
Simulation time 7552011973 ps
CPU time 117.73 seconds
Started Jun 30 04:44:42 PM PDT 24
Finished Jun 30 04:46:41 PM PDT 24
Peak memory 308724 kb
Host smart-5c095556-d850-4342-9a69-5e459855ffa9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273073523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.4273073523
Directory /workspace/29.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/29.sram_ctrl_smoke.573897801
Short name T406
Test name
Test status
Simulation time 497249504 ps
CPU time 10.9 seconds
Started Jun 30 04:44:39 PM PDT 24
Finished Jun 30 04:44:50 PM PDT 24
Peak memory 232472 kb
Host smart-62be8654-affd-4b09-bad4-223ffb17cc08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573897801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.573897801
Directory /workspace/29.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_all.3512013055
Short name T931
Test name
Test status
Simulation time 166577369861 ps
CPU time 5937.62 seconds
Started Jun 30 04:44:42 PM PDT 24
Finished Jun 30 06:23:41 PM PDT 24
Peak memory 381736 kb
Host smart-3384f523-3e94-4bae-a0fe-3f873c86eb77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512013055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 29.sram_ctrl_stress_all.3512013055
Directory /workspace/29.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.2779119136
Short name T455
Test name
Test status
Simulation time 401816273 ps
CPU time 20.46 seconds
Started Jun 30 04:44:41 PM PDT 24
Finished Jun 30 04:45:03 PM PDT 24
Peak memory 211500 kb
Host smart-b0dd1afb-0be7-4a14-a6ea-bca0d2c77919
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2779119136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.2779119136
Directory /workspace/29.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_pipeline.780242573
Short name T570
Test name
Test status
Simulation time 2851528031 ps
CPU time 87.33 seconds
Started Jun 30 04:44:43 PM PDT 24
Finished Jun 30 04:46:11 PM PDT 24
Peak memory 202672 kb
Host smart-8af1330d-a5e9-4cb7-b020-74953ccc8eef
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780242573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.sram_ctrl_stress_pipeline.780242573
Directory /workspace/29.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.626479651
Short name T260
Test name
Test status
Simulation time 9779629989 ps
CPU time 180.9 seconds
Started Jun 30 04:44:42 PM PDT 24
Finished Jun 30 04:47:44 PM PDT 24
Peak memory 370364 kb
Host smart-6338c787-a7ab-4c61-8f07-f6d2c62c9dac
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626479651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.sram_ctrl_throughput_w_partial_write.626479651
Directory /workspace/29.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/3.sram_ctrl_access_during_key_req.1947087132
Short name T654
Test name
Test status
Simulation time 6660297814 ps
CPU time 287.15 seconds
Started Jun 30 04:43:38 PM PDT 24
Finished Jun 30 04:48:26 PM PDT 24
Peak memory 341924 kb
Host smart-f110ed20-8a17-48e9-af9c-b4c34f2e9f97
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947087132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.sram_ctrl_access_during_key_req.1947087132
Directory /workspace/3.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/3.sram_ctrl_alert_test.1085104262
Short name T640
Test name
Test status
Simulation time 74185776 ps
CPU time 0.68 seconds
Started Jun 30 04:43:56 PM PDT 24
Finished Jun 30 04:44:03 PM PDT 24
Peak memory 202280 kb
Host smart-03511632-36f5-4cba-8df9-9762e5f83266
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085104262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_alert_test.1085104262
Directory /workspace/3.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sram_ctrl_bijection.1451536268
Short name T903
Test name
Test status
Simulation time 261010366623 ps
CPU time 1382.05 seconds
Started Jun 30 04:43:28 PM PDT 24
Finished Jun 30 05:06:31 PM PDT 24
Peak memory 203376 kb
Host smart-393441a4-5799-4a44-a283-4ae98f0393e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451536268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.
1451536268
Directory /workspace/3.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/3.sram_ctrl_executable.2123434926
Short name T761
Test name
Test status
Simulation time 110559424128 ps
CPU time 1227.95 seconds
Started Jun 30 04:43:51 PM PDT 24
Finished Jun 30 05:04:20 PM PDT 24
Peak memory 372144 kb
Host smart-b5efee07-88e3-456c-95b4-efb6cf3b913e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123434926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl
e.2123434926
Directory /workspace/3.sram_ctrl_executable/latest

Test location /workspace/coverage/default/3.sram_ctrl_lc_escalation.4185684570
Short name T451
Test name
Test status
Simulation time 8087608862 ps
CPU time 27.44 seconds
Started Jun 30 04:43:47 PM PDT 24
Finished Jun 30 04:44:16 PM PDT 24
Peak memory 202748 kb
Host smart-5b4985ce-2637-4672-a8ba-8a1691ce8017
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185684570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc
alation.4185684570
Directory /workspace/3.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/3.sram_ctrl_max_throughput.3451481837
Short name T143
Test name
Test status
Simulation time 4019761276 ps
CPU time 122.69 seconds
Started Jun 30 04:43:39 PM PDT 24
Finished Jun 30 04:45:43 PM PDT 24
Peak memory 371580 kb
Host smart-07943150-3199-45be-aaf0-ae1f78a7597d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451481837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.sram_ctrl_max_throughput.3451481837
Directory /workspace/3.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_partial_access.1204271969
Short name T89
Test name
Test status
Simulation time 4576804618 ps
CPU time 152.48 seconds
Started Jun 30 04:43:49 PM PDT 24
Finished Jun 30 04:46:22 PM PDT 24
Peak memory 210940 kb
Host smart-52c8d161-e1b4-43fc-9433-ad4ad132bd2d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204271969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_mem_partial_access.1204271969
Directory /workspace/3.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_walk.1780992527
Short name T835
Test name
Test status
Simulation time 3942338993 ps
CPU time 265.04 seconds
Started Jun 30 04:43:41 PM PDT 24
Finished Jun 30 04:48:06 PM PDT 24
Peak memory 210892 kb
Host smart-6c4b7f15-e335-4325-943c-25d0edf408ef
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780992527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl
_mem_walk.1780992527
Directory /workspace/3.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/3.sram_ctrl_multiple_keys.3679037796
Short name T703
Test name
Test status
Simulation time 40533639121 ps
CPU time 622.15 seconds
Started Jun 30 04:43:41 PM PDT 24
Finished Jun 30 04:54:04 PM PDT 24
Peak memory 364756 kb
Host smart-56a1750f-e6b9-4502-a0d1-cb69bee334cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679037796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip
le_keys.3679037796
Directory /workspace/3.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access.1519890543
Short name T156
Test name
Test status
Simulation time 2104389555 ps
CPU time 5.93 seconds
Started Jun 30 04:43:47 PM PDT 24
Finished Jun 30 04:43:55 PM PDT 24
Peak memory 202580 kb
Host smart-eeda1334-d6a6-42bf-b75b-70c41ecf1cef
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519890543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s
ram_ctrl_partial_access.1519890543
Directory /workspace/3.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3335479709
Short name T351
Test name
Test status
Simulation time 10093113432 ps
CPU time 301.32 seconds
Started Jun 30 04:43:38 PM PDT 24
Finished Jun 30 04:48:40 PM PDT 24
Peak memory 202712 kb
Host smart-e657fd84-aa0d-408d-b83d-87d56a7cde5c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335479709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 3.sram_ctrl_partial_access_b2b.3335479709
Directory /workspace/3.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/3.sram_ctrl_ram_cfg.66094243
Short name T820
Test name
Test status
Simulation time 359391119 ps
CPU time 3.34 seconds
Started Jun 30 04:43:37 PM PDT 24
Finished Jun 30 04:43:40 PM PDT 24
Peak memory 202780 kb
Host smart-97e2ea76-5196-4325-b310-343cee8a7756
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66094243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf
g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.66094243
Directory /workspace/3.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/3.sram_ctrl_regwen.2438648256
Short name T533
Test name
Test status
Simulation time 2219046317 ps
CPU time 702.19 seconds
Started Jun 30 04:43:39 PM PDT 24
Finished Jun 30 04:55:22 PM PDT 24
Peak memory 371752 kb
Host smart-2304a42b-54fa-4137-af27-7f82b2f7e409
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438648256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.2438648256
Directory /workspace/3.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/3.sram_ctrl_sec_cm.3848734458
Short name T17
Test name
Test status
Simulation time 1063016703 ps
CPU time 2.99 seconds
Started Jun 30 04:43:30 PM PDT 24
Finished Jun 30 04:43:34 PM PDT 24
Peak memory 221868 kb
Host smart-f925593c-6b8b-41a0-83d5-2544d44a33a3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848734458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_sec_cm.3848734458
Directory /workspace/3.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sram_ctrl_smoke.2259664135
Short name T484
Test name
Test status
Simulation time 4122322045 ps
CPU time 13.47 seconds
Started Jun 30 04:43:39 PM PDT 24
Finished Jun 30 04:43:54 PM PDT 24
Peak memory 202748 kb
Host smart-f8039896-1a38-4dd8-95fd-492a1532d119
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259664135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.2259664135
Directory /workspace/3.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all.3111743949
Short name T902
Test name
Test status
Simulation time 94538682368 ps
CPU time 6180.23 seconds
Started Jun 30 04:43:40 PM PDT 24
Finished Jun 30 06:26:42 PM PDT 24
Peak memory 380072 kb
Host smart-e64167a6-615c-43e9-aa09-bd7da057d9cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111743949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 3.sram_ctrl_stress_all.3111743949
Directory /workspace/3.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.235413891
Short name T426
Test name
Test status
Simulation time 984112559 ps
CPU time 30.67 seconds
Started Jun 30 04:43:45 PM PDT 24
Finished Jun 30 04:44:16 PM PDT 24
Peak memory 210980 kb
Host smart-e80530ce-364f-4907-8cb4-3e3a9803ab64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=235413891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.235413891
Directory /workspace/3.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_pipeline.3818534820
Short name T409
Test name
Test status
Simulation time 4598927186 ps
CPU time 262.4 seconds
Started Jun 30 04:43:28 PM PDT 24
Finished Jun 30 04:47:52 PM PDT 24
Peak memory 202736 kb
Host smart-9d41feb3-0058-483c-ab6e-8a0bb1bcb353
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818534820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_stress_pipeline.3818534820
Directory /workspace/3.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.3604274091
Short name T398
Test name
Test status
Simulation time 679878957 ps
CPU time 8.65 seconds
Started Jun 30 04:43:53 PM PDT 24
Finished Jun 30 04:44:02 PM PDT 24
Peak memory 219004 kb
Host smart-d81a413c-b102-4885-a69f-15a475f0d640
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604274091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.3604274091
Directory /workspace/3.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/30.sram_ctrl_access_during_key_req.1415124184
Short name T43
Test name
Test status
Simulation time 23608465447 ps
CPU time 1001.69 seconds
Started Jun 30 04:44:43 PM PDT 24
Finished Jun 30 05:01:26 PM PDT 24
Peak memory 368676 kb
Host smart-f176831e-b752-4cf1-9879-d39f945e3e8b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415124184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.sram_ctrl_access_during_key_req.1415124184
Directory /workspace/30.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/30.sram_ctrl_alert_test.4223109577
Short name T13
Test name
Test status
Simulation time 12790744 ps
CPU time 0.65 seconds
Started Jun 30 04:44:49 PM PDT 24
Finished Jun 30 04:44:50 PM PDT 24
Peak memory 202288 kb
Host smart-a07eeebd-307d-4009-94ab-541e8d37924b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223109577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.sram_ctrl_alert_test.4223109577
Directory /workspace/30.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sram_ctrl_bijection.1583462663
Short name T771
Test name
Test status
Simulation time 726368348715 ps
CPU time 2434.1 seconds
Started Jun 30 04:44:41 PM PDT 24
Finished Jun 30 05:25:16 PM PDT 24
Peak memory 202788 kb
Host smart-a27d3466-3c57-4fb1-a444-71e1987f3c9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583462663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection
.1583462663
Directory /workspace/30.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/30.sram_ctrl_executable.4259028405
Short name T600
Test name
Test status
Simulation time 7200562491 ps
CPU time 1003.99 seconds
Started Jun 30 04:44:41 PM PDT 24
Finished Jun 30 05:01:27 PM PDT 24
Peak memory 379652 kb
Host smart-3e331255-b2e0-4292-86dc-34fed7ddafef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259028405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executab
le.4259028405
Directory /workspace/30.sram_ctrl_executable/latest

Test location /workspace/coverage/default/30.sram_ctrl_lc_escalation.591527682
Short name T587
Test name
Test status
Simulation time 6580950432 ps
CPU time 46.59 seconds
Started Jun 30 04:44:41 PM PDT 24
Finished Jun 30 04:45:29 PM PDT 24
Peak memory 210940 kb
Host smart-2128e087-a1a7-4dd1-a104-389f1496b425
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591527682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_esc
alation.591527682
Directory /workspace/30.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/30.sram_ctrl_max_throughput.1977792147
Short name T700
Test name
Test status
Simulation time 1456611733 ps
CPU time 11.04 seconds
Started Jun 30 04:44:43 PM PDT 24
Finished Jun 30 04:44:55 PM PDT 24
Peak memory 235304 kb
Host smart-d1d18fb5-7f65-44aa-9bc3-429a64761074
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977792147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.sram_ctrl_max_throughput.1977792147
Directory /workspace/30.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_partial_access.2012474301
Short name T92
Test name
Test status
Simulation time 41341679009 ps
CPU time 161.22 seconds
Started Jun 30 04:44:51 PM PDT 24
Finished Jun 30 04:47:32 PM PDT 24
Peak memory 211044 kb
Host smart-61187952-f697-483f-8307-1ad6ae235c28
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012474301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_mem_partial_access.2012474301
Directory /workspace/30.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_walk.2001049902
Short name T517
Test name
Test status
Simulation time 53260353851 ps
CPU time 315.99 seconds
Started Jun 30 04:44:52 PM PDT 24
Finished Jun 30 04:50:08 PM PDT 24
Peak memory 210840 kb
Host smart-c811d30b-2767-45ca-bea4-d003141fc4f2
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001049902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr
l_mem_walk.2001049902
Directory /workspace/30.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/30.sram_ctrl_multiple_keys.2424844506
Short name T733
Test name
Test status
Simulation time 13252690076 ps
CPU time 85.71 seconds
Started Jun 30 04:44:39 PM PDT 24
Finished Jun 30 04:46:06 PM PDT 24
Peak memory 295712 kb
Host smart-dd93ca6a-6a51-48b4-89c8-cd9090a3a789
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424844506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi
ple_keys.2424844506
Directory /workspace/30.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access.863460499
Short name T626
Test name
Test status
Simulation time 774177024 ps
CPU time 47.45 seconds
Started Jun 30 04:44:41 PM PDT 24
Finished Jun 30 04:45:29 PM PDT 24
Peak memory 287016 kb
Host smart-643c3a56-c187-4c34-bb00-f3b690918ff8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863460499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.s
ram_ctrl_partial_access.863460499
Directory /workspace/30.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.3417981024
Short name T459
Test name
Test status
Simulation time 17243637683 ps
CPU time 408.27 seconds
Started Jun 30 04:44:43 PM PDT 24
Finished Jun 30 04:51:33 PM PDT 24
Peak memory 202712 kb
Host smart-d70dd222-8042-4b06-830c-62a1720fffa8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417981024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 30.sram_ctrl_partial_access_b2b.3417981024
Directory /workspace/30.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/30.sram_ctrl_ram_cfg.3602090635
Short name T34
Test name
Test status
Simulation time 362954072 ps
CPU time 3.3 seconds
Started Jun 30 04:44:50 PM PDT 24
Finished Jun 30 04:44:54 PM PDT 24
Peak memory 202768 kb
Host smart-72fdf4aa-02c1-44e3-9614-bd4e2146477c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602090635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.3602090635
Directory /workspace/30.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/30.sram_ctrl_regwen.1211453844
Short name T798
Test name
Test status
Simulation time 19317788043 ps
CPU time 635.35 seconds
Started Jun 30 04:44:40 PM PDT 24
Finished Jun 30 04:55:16 PM PDT 24
Peak memory 377588 kb
Host smart-64528d96-223f-434e-a369-3eb622a6165b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211453844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.1211453844
Directory /workspace/30.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/30.sram_ctrl_smoke.21849874
Short name T297
Test name
Test status
Simulation time 1586680001 ps
CPU time 17.38 seconds
Started Jun 30 04:44:43 PM PDT 24
Finished Jun 30 04:45:02 PM PDT 24
Peak memory 202728 kb
Host smart-dac67f3f-99f6-455f-b244-36d93470bb4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21849874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.21849874
Directory /workspace/30.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all.513244116
Short name T711
Test name
Test status
Simulation time 907339694783 ps
CPU time 4892.7 seconds
Started Jun 30 04:44:50 PM PDT 24
Finished Jun 30 06:06:23 PM PDT 24
Peak memory 380224 kb
Host smart-17890ec4-84ed-4a8f-95db-d2d647698ff1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513244116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 30.sram_ctrl_stress_all.513244116
Directory /workspace/30.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.458084243
Short name T824
Test name
Test status
Simulation time 1982608665 ps
CPU time 83.09 seconds
Started Jun 30 04:44:49 PM PDT 24
Finished Jun 30 04:46:13 PM PDT 24
Peak memory 212776 kb
Host smart-647ac7a6-f1a0-4b75-bf8e-22823f57b38a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=458084243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.458084243
Directory /workspace/30.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_pipeline.2967202696
Short name T313
Test name
Test status
Simulation time 9700347088 ps
CPU time 305.68 seconds
Started Jun 30 04:44:42 PM PDT 24
Finished Jun 30 04:49:49 PM PDT 24
Peak memory 202732 kb
Host smart-837dcb2a-a314-4ce5-949c-f8a1a52a5a8a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967202696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_stress_pipeline.2967202696
Directory /workspace/30.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1266094667
Short name T729
Test name
Test status
Simulation time 767849998 ps
CPU time 17.27 seconds
Started Jun 30 04:44:42 PM PDT 24
Finished Jun 30 04:45:00 PM PDT 24
Peak memory 251668 kb
Host smart-d5e97e22-4ac8-4a60-96f6-7ff6ab27f08e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266094667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.1266094667
Directory /workspace/30.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/31.sram_ctrl_access_during_key_req.3640295970
Short name T904
Test name
Test status
Simulation time 28518801958 ps
CPU time 819.99 seconds
Started Jun 30 04:44:48 PM PDT 24
Finished Jun 30 04:58:29 PM PDT 24
Peak memory 374428 kb
Host smart-ee2f450e-f3b8-4533-bd47-c4d1657b180a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640295970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.sram_ctrl_access_during_key_req.3640295970
Directory /workspace/31.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/31.sram_ctrl_alert_test.693236019
Short name T345
Test name
Test status
Simulation time 60337580 ps
CPU time 0.74 seconds
Started Jun 30 04:44:48 PM PDT 24
Finished Jun 30 04:44:49 PM PDT 24
Peak memory 202340 kb
Host smart-1771d677-3da1-491e-87f7-e2a0d6c3ee74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693236019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.sram_ctrl_alert_test.693236019
Directory /workspace/31.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sram_ctrl_bijection.89237279
Short name T548
Test name
Test status
Simulation time 167003556376 ps
CPU time 2649.5 seconds
Started Jun 30 04:44:51 PM PDT 24
Finished Jun 30 05:29:01 PM PDT 24
Peak memory 203512 kb
Host smart-faf16f4b-fe75-4185-a33a-986e69557bca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89237279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject
ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection.89237279
Directory /workspace/31.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/31.sram_ctrl_executable.4201158503
Short name T550
Test name
Test status
Simulation time 15046631304 ps
CPU time 491.46 seconds
Started Jun 30 04:44:47 PM PDT 24
Finished Jun 30 04:52:59 PM PDT 24
Peak memory 368408 kb
Host smart-917bcb29-8d21-411b-b630-07a2ac4c75e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201158503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executab
le.4201158503
Directory /workspace/31.sram_ctrl_executable/latest

Test location /workspace/coverage/default/31.sram_ctrl_lc_escalation.768235499
Short name T734
Test name
Test status
Simulation time 49201487066 ps
CPU time 87.23 seconds
Started Jun 30 04:44:50 PM PDT 24
Finished Jun 30 04:46:18 PM PDT 24
Peak memory 202732 kb
Host smart-837a26ee-4ff7-43bf-bd6b-400294dfb001
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768235499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_esc
alation.768235499
Directory /workspace/31.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/31.sram_ctrl_max_throughput.2706864359
Short name T253
Test name
Test status
Simulation time 1873785240 ps
CPU time 64.32 seconds
Started Jun 30 04:44:48 PM PDT 24
Finished Jun 30 04:45:53 PM PDT 24
Peak memory 309812 kb
Host smart-559a75a8-294b-45cf-bd63-cd7e6d8a0c51
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706864359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.sram_ctrl_max_throughput.2706864359
Directory /workspace/31.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_walk.2092190072
Short name T330
Test name
Test status
Simulation time 2083308992 ps
CPU time 137.76 seconds
Started Jun 30 04:44:50 PM PDT 24
Finished Jun 30 04:47:09 PM PDT 24
Peak memory 211316 kb
Host smart-d07435f6-a8f8-4941-898d-58157a64312b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092190072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr
l_mem_walk.2092190072
Directory /workspace/31.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/31.sram_ctrl_multiple_keys.568029559
Short name T873
Test name
Test status
Simulation time 56338802238 ps
CPU time 539.19 seconds
Started Jun 30 04:44:50 PM PDT 24
Finished Jun 30 04:53:50 PM PDT 24
Peak memory 356092 kb
Host smart-b7808bff-d990-42c0-9879-d4477f47e830
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568029559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multip
le_keys.568029559
Directory /workspace/31.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access.2589428543
Short name T5
Test name
Test status
Simulation time 3674507210 ps
CPU time 19.92 seconds
Started Jun 30 04:44:48 PM PDT 24
Finished Jun 30 04:45:09 PM PDT 24
Peak memory 262376 kb
Host smart-ab7bee41-20b6-40c5-83df-86d448bc4f27
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589428543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
sram_ctrl_partial_access.2589428543
Directory /workspace/31.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.1700242704
Short name T516
Test name
Test status
Simulation time 15414744196 ps
CPU time 373.41 seconds
Started Jun 30 04:44:48 PM PDT 24
Finished Jun 30 04:51:02 PM PDT 24
Peak memory 202760 kb
Host smart-0cdb6669-e475-49da-97c1-b23c4c156d83
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700242704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 31.sram_ctrl_partial_access_b2b.1700242704
Directory /workspace/31.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/31.sram_ctrl_ram_cfg.2693910119
Short name T332
Test name
Test status
Simulation time 486406394 ps
CPU time 3.27 seconds
Started Jun 30 04:44:49 PM PDT 24
Finished Jun 30 04:44:52 PM PDT 24
Peak memory 202684 kb
Host smart-a8253de9-d4a9-413c-ab29-8de00ed75e0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693910119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.2693910119
Directory /workspace/31.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/31.sram_ctrl_regwen.2016076467
Short name T501
Test name
Test status
Simulation time 25938592891 ps
CPU time 752.46 seconds
Started Jun 30 04:44:50 PM PDT 24
Finished Jun 30 04:57:23 PM PDT 24
Peak memory 380676 kb
Host smart-1d2b388b-fb31-4bb1-a6c7-b4414ff90093
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016076467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.2016076467
Directory /workspace/31.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/31.sram_ctrl_smoke.1760876903
Short name T454
Test name
Test status
Simulation time 682606240 ps
CPU time 6.89 seconds
Started Jun 30 04:44:50 PM PDT 24
Finished Jun 30 04:44:57 PM PDT 24
Peak memory 204884 kb
Host smart-bab11bd1-c1b6-479d-bb35-aa6d6fd76071
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760876903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.1760876903
Directory /workspace/31.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all.632125297
Short name T843
Test name
Test status
Simulation time 209058765334 ps
CPU time 3587.62 seconds
Started Jun 30 04:44:50 PM PDT 24
Finished Jun 30 05:44:39 PM PDT 24
Peak memory 380652 kb
Host smart-c4abb161-01a7-425a-8355-3b52fb174254
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632125297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 31.sram_ctrl_stress_all.632125297
Directory /workspace/31.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2009974272
Short name T853
Test name
Test status
Simulation time 1061316150 ps
CPU time 27.02 seconds
Started Jun 30 04:44:47 PM PDT 24
Finished Jun 30 04:45:14 PM PDT 24
Peak memory 210912 kb
Host smart-6e2e40f7-cd67-4422-b4ea-a2058ca24ccc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2009974272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.2009974272
Directory /workspace/31.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_pipeline.3445849558
Short name T242
Test name
Test status
Simulation time 19773745565 ps
CPU time 148.85 seconds
Started Jun 30 04:44:48 PM PDT 24
Finished Jun 30 04:47:17 PM PDT 24
Peak memory 202756 kb
Host smart-49940e12-5d62-42d4-8d91-7653ab6af689
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445849558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_stress_pipeline.3445849558
Directory /workspace/31.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.2902789064
Short name T177
Test name
Test status
Simulation time 1517440191 ps
CPU time 16.1 seconds
Started Jun 30 04:44:50 PM PDT 24
Finished Jun 30 04:45:07 PM PDT 24
Peak memory 243044 kb
Host smart-ebd457d6-5fde-4d29-b2fd-bbe97c6c417a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902789064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.2902789064
Directory /workspace/31.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/32.sram_ctrl_access_during_key_req.3751522407
Short name T749
Test name
Test status
Simulation time 39190264936 ps
CPU time 1588.81 seconds
Started Jun 30 04:44:50 PM PDT 24
Finished Jun 30 05:11:20 PM PDT 24
Peak memory 377684 kb
Host smart-13be9c3b-13aa-482c-b964-3e82330390cc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751522407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.sram_ctrl_access_during_key_req.3751522407
Directory /workspace/32.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/32.sram_ctrl_alert_test.1660008301
Short name T404
Test name
Test status
Simulation time 10962332 ps
CPU time 0.67 seconds
Started Jun 30 04:44:56 PM PDT 24
Finished Jun 30 04:44:57 PM PDT 24
Peak memory 202236 kb
Host smart-36e52b3f-fbe6-49e7-b669-90ae08197fd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660008301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.sram_ctrl_alert_test.1660008301
Directory /workspace/32.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sram_ctrl_bijection.2693955850
Short name T287
Test name
Test status
Simulation time 149383087091 ps
CPU time 945.79 seconds
Started Jun 30 04:44:50 PM PDT 24
Finished Jun 30 05:00:37 PM PDT 24
Peak memory 203256 kb
Host smart-f62b2186-e8af-47ce-ae0a-786354a478ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693955850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection
.2693955850
Directory /workspace/32.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/32.sram_ctrl_executable.1925560003
Short name T395
Test name
Test status
Simulation time 33737677822 ps
CPU time 596.55 seconds
Started Jun 30 04:44:55 PM PDT 24
Finished Jun 30 04:54:53 PM PDT 24
Peak memory 371404 kb
Host smart-fdc7465f-99a3-4e66-b193-d91b767b803c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925560003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executab
le.1925560003
Directory /workspace/32.sram_ctrl_executable/latest

Test location /workspace/coverage/default/32.sram_ctrl_lc_escalation.2509219427
Short name T938
Test name
Test status
Simulation time 23030610954 ps
CPU time 67.5 seconds
Started Jun 30 04:44:49 PM PDT 24
Finished Jun 30 04:45:57 PM PDT 24
Peak memory 202772 kb
Host smart-c98c0ca0-aead-4a27-8852-af0dd96cc0e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509219427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_es
calation.2509219427
Directory /workspace/32.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/32.sram_ctrl_max_throughput.1124952300
Short name T201
Test name
Test status
Simulation time 751715679 ps
CPU time 26.65 seconds
Started Jun 30 04:44:52 PM PDT 24
Finished Jun 30 04:45:19 PM PDT 24
Peak memory 268000 kb
Host smart-813c2ef2-2e6a-4129-85fa-449af8b593f8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124952300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.sram_ctrl_max_throughput.1124952300
Directory /workspace/32.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_partial_access.1301984460
Short name T376
Test name
Test status
Simulation time 10936122070 ps
CPU time 88.06 seconds
Started Jun 30 04:44:57 PM PDT 24
Finished Jun 30 04:46:25 PM PDT 24
Peak memory 210920 kb
Host smart-238917aa-52e1-4908-9978-ba308cf65c9e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301984460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.sram_ctrl_mem_partial_access.1301984460
Directory /workspace/32.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_walk.22478308
Short name T303
Test name
Test status
Simulation time 2019621023 ps
CPU time 129.8 seconds
Started Jun 30 04:44:56 PM PDT 24
Finished Jun 30 04:47:06 PM PDT 24
Peak memory 210756 kb
Host smart-a12382a4-2dd6-459c-b58b-2b20fabcf4a7
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22478308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr
am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_
mem_walk.22478308
Directory /workspace/32.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/32.sram_ctrl_multiple_keys.3890527771
Short name T166
Test name
Test status
Simulation time 4988316650 ps
CPU time 558.69 seconds
Started Jun 30 04:44:52 PM PDT 24
Finished Jun 30 04:54:11 PM PDT 24
Peak memory 378176 kb
Host smart-2228e323-a22d-4756-8d6d-e4a30c4efca2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890527771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multi
ple_keys.3890527771
Directory /workspace/32.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access.1716063947
Short name T929
Test name
Test status
Simulation time 1452043272 ps
CPU time 104.3 seconds
Started Jun 30 04:44:48 PM PDT 24
Finished Jun 30 04:46:33 PM PDT 24
Peak memory 360228 kb
Host smart-f4883511-79a5-4e77-97d5-6051379c1544
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716063947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
sram_ctrl_partial_access.1716063947
Directory /workspace/32.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.994539264
Short name T563
Test name
Test status
Simulation time 5651857837 ps
CPU time 286.36 seconds
Started Jun 30 04:44:51 PM PDT 24
Finished Jun 30 04:49:38 PM PDT 24
Peak memory 202676 kb
Host smart-f864f6d7-486b-4432-9a18-bf6a44786677
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994539264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.sram_ctrl_partial_access_b2b.994539264
Directory /workspace/32.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/32.sram_ctrl_ram_cfg.2951754872
Short name T799
Test name
Test status
Simulation time 359487697 ps
CPU time 3.21 seconds
Started Jun 30 04:44:56 PM PDT 24
Finished Jun 30 04:45:00 PM PDT 24
Peak memory 202668 kb
Host smart-fbf03ee7-fcec-4b07-9d86-a576daa1317c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951754872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.2951754872
Directory /workspace/32.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/32.sram_ctrl_regwen.2349145733
Short name T635
Test name
Test status
Simulation time 19754511192 ps
CPU time 728.09 seconds
Started Jun 30 04:44:55 PM PDT 24
Finished Jun 30 04:57:04 PM PDT 24
Peak memory 382748 kb
Host smart-560953a1-e161-4377-972f-ea228b727e37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349145733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.2349145733
Directory /workspace/32.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/32.sram_ctrl_smoke.4006871125
Short name T727
Test name
Test status
Simulation time 6339527170 ps
CPU time 24.25 seconds
Started Jun 30 04:44:50 PM PDT 24
Finished Jun 30 04:45:15 PM PDT 24
Peak memory 202780 kb
Host smart-54443a04-4cf3-44b1-a1cd-ddfeb049d9ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006871125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.4006871125
Directory /workspace/32.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all.134338679
Short name T413
Test name
Test status
Simulation time 47653031427 ps
CPU time 2379.76 seconds
Started Jun 30 04:44:55 PM PDT 24
Finished Jun 30 05:24:36 PM PDT 24
Peak memory 378600 kb
Host smart-b505e8c1-adca-49d1-ac1f-7a5c0fee98e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134338679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 32.sram_ctrl_stress_all.134338679
Directory /workspace/32.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.412796846
Short name T462
Test name
Test status
Simulation time 1037384317 ps
CPU time 93.74 seconds
Started Jun 30 04:44:56 PM PDT 24
Finished Jun 30 04:46:30 PM PDT 24
Peak memory 288488 kb
Host smart-60878650-ec11-43e9-80bd-80089b477136
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=412796846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.412796846
Directory /workspace/32.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_pipeline.3324910639
Short name T892
Test name
Test status
Simulation time 25573727798 ps
CPU time 479.87 seconds
Started Jun 30 04:44:50 PM PDT 24
Finished Jun 30 04:52:51 PM PDT 24
Peak memory 202680 kb
Host smart-e290c3ed-f867-48ae-a8b1-02a5f4334ad2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324910639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.sram_ctrl_stress_pipeline.3324910639
Directory /workspace/32.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3659773220
Short name T154
Test name
Test status
Simulation time 2524836833 ps
CPU time 7.6 seconds
Started Jun 30 04:44:47 PM PDT 24
Finished Jun 30 04:44:55 PM PDT 24
Peak memory 218812 kb
Host smart-9b73e45b-d160-4571-9aed-a08951457a83
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659773220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.3659773220
Directory /workspace/32.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/33.sram_ctrl_access_during_key_req.1501948238
Short name T91
Test name
Test status
Simulation time 9953437858 ps
CPU time 700.48 seconds
Started Jun 30 04:45:02 PM PDT 24
Finished Jun 30 04:56:42 PM PDT 24
Peak memory 363188 kb
Host smart-f990148c-faff-42da-a3fe-05efa9d1a112
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501948238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.sram_ctrl_access_during_key_req.1501948238
Directory /workspace/33.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/33.sram_ctrl_alert_test.4245044768
Short name T571
Test name
Test status
Simulation time 40763784 ps
CPU time 0.63 seconds
Started Jun 30 04:45:00 PM PDT 24
Finished Jun 30 04:45:01 PM PDT 24
Peak memory 202404 kb
Host smart-fd82d623-52ed-4077-92e8-080cdab51a46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245044768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.sram_ctrl_alert_test.4245044768
Directory /workspace/33.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sram_ctrl_bijection.196503770
Short name T63
Test name
Test status
Simulation time 20067288640 ps
CPU time 943.46 seconds
Started Jun 30 04:44:56 PM PDT 24
Finished Jun 30 05:00:40 PM PDT 24
Peak memory 203472 kb
Host smart-1dd70ee6-5a77-4d73-ae0b-39b10c29317f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196503770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection.
196503770
Directory /workspace/33.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/33.sram_ctrl_executable.2357470926
Short name T419
Test name
Test status
Simulation time 140822275289 ps
CPU time 519.88 seconds
Started Jun 30 04:44:56 PM PDT 24
Finished Jun 30 04:53:36 PM PDT 24
Peak memory 360216 kb
Host smart-e0d2376b-0952-4eea-ab0f-786e0c2f1857
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357470926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executab
le.2357470926
Directory /workspace/33.sram_ctrl_executable/latest

Test location /workspace/coverage/default/33.sram_ctrl_lc_escalation.2388754415
Short name T900
Test name
Test status
Simulation time 9426773105 ps
CPU time 31.64 seconds
Started Jun 30 04:44:54 PM PDT 24
Finished Jun 30 04:45:26 PM PDT 24
Peak memory 210936 kb
Host smart-804faad1-1df3-4016-9b05-b837cbc5fe3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388754415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_es
calation.2388754415
Directory /workspace/33.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/33.sram_ctrl_max_throughput.1376239053
Short name T307
Test name
Test status
Simulation time 3149319431 ps
CPU time 42.69 seconds
Started Jun 30 04:45:01 PM PDT 24
Finished Jun 30 04:45:44 PM PDT 24
Peak memory 301804 kb
Host smart-1361018c-904f-421b-bd4e-6a3febb133bc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376239053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.sram_ctrl_max_throughput.1376239053
Directory /workspace/33.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_partial_access.1707911557
Short name T278
Test name
Test status
Simulation time 2467215367 ps
CPU time 80.18 seconds
Started Jun 30 04:44:57 PM PDT 24
Finished Jun 30 04:46:18 PM PDT 24
Peak memory 210932 kb
Host smart-5c3f8b22-1a02-433b-a441-0cc2dea4cc28
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707911557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_mem_partial_access.1707911557
Directory /workspace/33.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_walk.1355454192
Short name T912
Test name
Test status
Simulation time 13974935014 ps
CPU time 338.43 seconds
Started Jun 30 04:44:59 PM PDT 24
Finished Jun 30 04:50:38 PM PDT 24
Peak memory 210844 kb
Host smart-62786712-c160-4475-95b4-8f2896b787fd
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355454192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr
l_mem_walk.1355454192
Directory /workspace/33.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/33.sram_ctrl_multiple_keys.3581994471
Short name T264
Test name
Test status
Simulation time 70143246357 ps
CPU time 745.23 seconds
Started Jun 30 04:44:53 PM PDT 24
Finished Jun 30 04:57:19 PM PDT 24
Peak memory 373172 kb
Host smart-fd29f5de-323a-42df-83a5-0a542269ce23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581994471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi
ple_keys.3581994471
Directory /workspace/33.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access.3891875147
Short name T176
Test name
Test status
Simulation time 985089362 ps
CPU time 14.09 seconds
Started Jun 30 04:44:57 PM PDT 24
Finished Jun 30 04:45:11 PM PDT 24
Peak memory 202564 kb
Host smart-e88cf875-05e8-431c-bb3c-2ed6a28a1082
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891875147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
sram_ctrl_partial_access.3891875147
Directory /workspace/33.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.2147364621
Short name T490
Test name
Test status
Simulation time 93536247356 ps
CPU time 541.97 seconds
Started Jun 30 04:44:56 PM PDT 24
Finished Jun 30 04:53:59 PM PDT 24
Peak memory 202736 kb
Host smart-a63d84c1-31e9-42a9-a631-1020e0825dc1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147364621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 33.sram_ctrl_partial_access_b2b.2147364621
Directory /workspace/33.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/33.sram_ctrl_ram_cfg.2357669443
Short name T259
Test name
Test status
Simulation time 1543214617 ps
CPU time 3.31 seconds
Started Jun 30 04:44:56 PM PDT 24
Finished Jun 30 04:45:00 PM PDT 24
Peak memory 202672 kb
Host smart-a1dfc15a-369e-44fa-a4e9-2a868b81fb72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357669443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.2357669443
Directory /workspace/33.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/33.sram_ctrl_regwen.3581679756
Short name T871
Test name
Test status
Simulation time 26133574842 ps
CPU time 1124.45 seconds
Started Jun 30 04:44:55 PM PDT 24
Finished Jun 30 05:03:40 PM PDT 24
Peak memory 382716 kb
Host smart-1a022ecb-2b9d-4bcb-a585-c20eaf7b28d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581679756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.3581679756
Directory /workspace/33.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/33.sram_ctrl_smoke.3926910025
Short name T407
Test name
Test status
Simulation time 1355640167 ps
CPU time 8.16 seconds
Started Jun 30 04:44:56 PM PDT 24
Finished Jun 30 04:45:05 PM PDT 24
Peak memory 202648 kb
Host smart-e8117279-5b59-49c9-a7c4-b566b83490de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926910025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.3926910025
Directory /workspace/33.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_all.2120618088
Short name T765
Test name
Test status
Simulation time 3292657538652 ps
CPU time 10025.5 seconds
Started Jun 30 04:44:56 PM PDT 24
Finished Jun 30 07:32:03 PM PDT 24
Peak memory 386832 kb
Host smart-4959bcc7-1200-48fa-93bd-70224793a102
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120618088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 33.sram_ctrl_stress_all.2120618088
Directory /workspace/33.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1657969952
Short name T513
Test name
Test status
Simulation time 584359452 ps
CPU time 20.27 seconds
Started Jun 30 04:44:55 PM PDT 24
Finished Jun 30 04:45:16 PM PDT 24
Peak memory 210940 kb
Host smart-8d02ebd4-9870-4bf6-996e-b6c2c4450ed1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1657969952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.1657969952
Directory /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_pipeline.125878495
Short name T747
Test name
Test status
Simulation time 8315843653 ps
CPU time 397.75 seconds
Started Jun 30 04:44:55 PM PDT 24
Finished Jun 30 04:51:34 PM PDT 24
Peak memory 202684 kb
Host smart-6a35bea7-1adf-4cf5-a46e-f616847a69f3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125878495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.sram_ctrl_stress_pipeline.125878495
Directory /workspace/33.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.2361112519
Short name T558
Test name
Test status
Simulation time 1872455961 ps
CPU time 7.57 seconds
Started Jun 30 04:44:55 PM PDT 24
Finished Jun 30 04:45:03 PM PDT 24
Peak memory 210816 kb
Host smart-deba32df-2fa5-4eef-b5e4-da2f360c9e88
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361112519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.2361112519
Directory /workspace/33.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/34.sram_ctrl_access_during_key_req.2690667090
Short name T803
Test name
Test status
Simulation time 11314344032 ps
CPU time 878.95 seconds
Started Jun 30 04:45:07 PM PDT 24
Finished Jun 30 04:59:47 PM PDT 24
Peak memory 379636 kb
Host smart-6af80baf-5785-4f2e-a99d-1a4441ae466c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690667090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.sram_ctrl_access_during_key_req.2690667090
Directory /workspace/34.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/34.sram_ctrl_alert_test.3009243814
Short name T619
Test name
Test status
Simulation time 26119558 ps
CPU time 0.68 seconds
Started Jun 30 04:45:03 PM PDT 24
Finished Jun 30 04:45:04 PM PDT 24
Peak memory 202440 kb
Host smart-908094ac-b76c-4a3c-8dd5-24a8798b6705
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009243814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.sram_ctrl_alert_test.3009243814
Directory /workspace/34.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sram_ctrl_bijection.1268550807
Short name T385
Test name
Test status
Simulation time 251833107714 ps
CPU time 1355.8 seconds
Started Jun 30 04:45:06 PM PDT 24
Finished Jun 30 05:07:42 PM PDT 24
Peak memory 203432 kb
Host smart-ec585b65-ccc1-436f-ac84-19daf00d28bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268550807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection
.1268550807
Directory /workspace/34.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/34.sram_ctrl_executable.2123672423
Short name T680
Test name
Test status
Simulation time 15832255551 ps
CPU time 945.21 seconds
Started Jun 30 04:45:05 PM PDT 24
Finished Jun 30 05:00:51 PM PDT 24
Peak memory 370484 kb
Host smart-4a9d158b-11a5-4ef4-b7cf-eae6c812d237
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123672423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executab
le.2123672423
Directory /workspace/34.sram_ctrl_executable/latest

Test location /workspace/coverage/default/34.sram_ctrl_lc_escalation.1144933746
Short name T608
Test name
Test status
Simulation time 29607336577 ps
CPU time 25.06 seconds
Started Jun 30 04:45:07 PM PDT 24
Finished Jun 30 04:45:33 PM PDT 24
Peak memory 210960 kb
Host smart-871ad595-a469-47ec-8345-c21d3340a65f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144933746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_es
calation.1144933746
Directory /workspace/34.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/34.sram_ctrl_max_throughput.2261586563
Short name T936
Test name
Test status
Simulation time 6166268361 ps
CPU time 56.14 seconds
Started Jun 30 04:45:04 PM PDT 24
Finished Jun 30 04:46:01 PM PDT 24
Peak memory 325404 kb
Host smart-3ef3f171-a248-4649-8777-4ee67d05cd83
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261586563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.sram_ctrl_max_throughput.2261586563
Directory /workspace/34.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_partial_access.1945322738
Short name T704
Test name
Test status
Simulation time 6371155695 ps
CPU time 130.71 seconds
Started Jun 30 04:45:04 PM PDT 24
Finished Jun 30 04:47:15 PM PDT 24
Peak memory 210904 kb
Host smart-6a8ed8f7-7544-4f34-8d82-f3c330313430
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945322738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.sram_ctrl_mem_partial_access.1945322738
Directory /workspace/34.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_walk.3244413792
Short name T162
Test name
Test status
Simulation time 8220595041 ps
CPU time 129.67 seconds
Started Jun 30 04:45:04 PM PDT 24
Finished Jun 30 04:47:15 PM PDT 24
Peak memory 210852 kb
Host smart-5c14c76d-1a03-48bc-9a68-d4bd999053ac
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244413792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr
l_mem_walk.3244413792
Directory /workspace/34.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/34.sram_ctrl_multiple_keys.1282584083
Short name T549
Test name
Test status
Simulation time 37375867503 ps
CPU time 476.05 seconds
Started Jun 30 04:45:04 PM PDT 24
Finished Jun 30 04:53:00 PM PDT 24
Peak memory 341048 kb
Host smart-2d9323b6-c001-4207-ac84-62f1fa072543
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282584083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi
ple_keys.1282584083
Directory /workspace/34.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access.1360748375
Short name T684
Test name
Test status
Simulation time 722668625 ps
CPU time 6.53 seconds
Started Jun 30 04:45:05 PM PDT 24
Finished Jun 30 04:45:12 PM PDT 24
Peak memory 202472 kb
Host smart-820ba775-9a6e-4f1a-8b41-7467db3980da
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360748375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
sram_ctrl_partial_access.1360748375
Directory /workspace/34.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.3957211
Short name T37
Test name
Test status
Simulation time 4928152968 ps
CPU time 251.16 seconds
Started Jun 30 04:45:04 PM PDT 24
Finished Jun 30 04:49:16 PM PDT 24
Peak memory 202688 kb
Host smart-7b2850e7-2c9a-4eca-8474-8060de91a213
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 34.sram_ctrl_partial_access_b2b.3957211
Directory /workspace/34.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/34.sram_ctrl_ram_cfg.1830013275
Short name T849
Test name
Test status
Simulation time 607155255 ps
CPU time 3.13 seconds
Started Jun 30 04:45:03 PM PDT 24
Finished Jun 30 04:45:06 PM PDT 24
Peak memory 202724 kb
Host smart-5d920ec0-81a2-4a7e-960c-12dfa61b26c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830013275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.1830013275
Directory /workspace/34.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/34.sram_ctrl_regwen.776685231
Short name T858
Test name
Test status
Simulation time 4574738064 ps
CPU time 238.31 seconds
Started Jun 30 04:45:02 PM PDT 24
Finished Jun 30 04:49:01 PM PDT 24
Peak memory 366264 kb
Host smart-9b77fee5-98fc-49a4-87e6-0c2b2b4ee970
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776685231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.776685231
Directory /workspace/34.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/34.sram_ctrl_smoke.251248845
Short name T769
Test name
Test status
Simulation time 7597922144 ps
CPU time 9.14 seconds
Started Jun 30 04:44:54 PM PDT 24
Finished Jun 30 04:45:04 PM PDT 24
Peak memory 202760 kb
Host smart-bea04839-c34f-4363-8e8f-35163d55937a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251248845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.251248845
Directory /workspace/34.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all.1533449506
Short name T656
Test name
Test status
Simulation time 98559987613 ps
CPU time 3218.35 seconds
Started Jun 30 04:45:05 PM PDT 24
Finished Jun 30 05:38:44 PM PDT 24
Peak memory 381732 kb
Host smart-12f8d4fa-eeed-43b7-88d6-ef8043732504
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533449506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 34.sram_ctrl_stress_all.1533449506
Directory /workspace/34.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2968618522
Short name T456
Test name
Test status
Simulation time 361491730 ps
CPU time 10.84 seconds
Started Jun 30 04:45:05 PM PDT 24
Finished Jun 30 04:45:17 PM PDT 24
Peak memory 210956 kb
Host smart-7675e405-b5f8-4098-9f6e-d8f4acbf28be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2968618522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.2968618522
Directory /workspace/34.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_pipeline.2779462549
Short name T337
Test name
Test status
Simulation time 5802113066 ps
CPU time 348.48 seconds
Started Jun 30 04:45:04 PM PDT 24
Finished Jun 30 04:50:53 PM PDT 24
Peak memory 202748 kb
Host smart-327dacc0-8a8a-43a6-afda-8db83c43ca0a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779462549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.sram_ctrl_stress_pipeline.2779462549
Directory /workspace/34.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.2074282694
Short name T590
Test name
Test status
Simulation time 1439772229 ps
CPU time 19.08 seconds
Started Jun 30 04:45:05 PM PDT 24
Finished Jun 30 04:45:25 PM PDT 24
Peak memory 251684 kb
Host smart-e5d750f4-5958-43dc-8463-bcb33d686396
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074282694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.2074282694
Directory /workspace/34.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/35.sram_ctrl_access_during_key_req.1346027853
Short name T601
Test name
Test status
Simulation time 40465968774 ps
CPU time 1895.41 seconds
Started Jun 30 04:45:13 PM PDT 24
Finished Jun 30 05:16:49 PM PDT 24
Peak memory 378780 kb
Host smart-c340f81d-4ed0-4a2b-8e51-7af1a4ecd560
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346027853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.sram_ctrl_access_during_key_req.1346027853
Directory /workspace/35.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/35.sram_ctrl_alert_test.1245207774
Short name T15
Test name
Test status
Simulation time 22384997 ps
CPU time 0.68 seconds
Started Jun 30 04:45:12 PM PDT 24
Finished Jun 30 04:45:13 PM PDT 24
Peak memory 202340 kb
Host smart-bf22d6f4-efac-4dc2-87cc-ae858e49f032
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245207774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.sram_ctrl_alert_test.1245207774
Directory /workspace/35.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sram_ctrl_bijection.3373276899
Short name T276
Test name
Test status
Simulation time 19035793921 ps
CPU time 650.94 seconds
Started Jun 30 04:45:03 PM PDT 24
Finished Jun 30 04:55:54 PM PDT 24
Peak memory 203480 kb
Host smart-92987b58-5125-4c41-b589-19c6aff21bb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373276899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection
.3373276899
Directory /workspace/35.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/35.sram_ctrl_executable.3467516263
Short name T756
Test name
Test status
Simulation time 4494121805 ps
CPU time 141.91 seconds
Started Jun 30 04:45:11 PM PDT 24
Finished Jun 30 04:47:33 PM PDT 24
Peak memory 368408 kb
Host smart-bad74e44-05a4-4c5a-8b17-38799de474af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467516263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab
le.3467516263
Directory /workspace/35.sram_ctrl_executable/latest

Test location /workspace/coverage/default/35.sram_ctrl_lc_escalation.2071502799
Short name T794
Test name
Test status
Simulation time 14910080388 ps
CPU time 48.51 seconds
Started Jun 30 04:45:14 PM PDT 24
Finished Jun 30 04:46:03 PM PDT 24
Peak memory 210960 kb
Host smart-e57ee349-f784-4e93-b6ac-f9b5a7b60ac5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071502799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es
calation.2071502799
Directory /workspace/35.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/35.sram_ctrl_max_throughput.1420804799
Short name T209
Test name
Test status
Simulation time 717536161 ps
CPU time 7.87 seconds
Started Jun 30 04:45:13 PM PDT 24
Finished Jun 30 04:45:21 PM PDT 24
Peak memory 218684 kb
Host smart-697f2497-1405-46c4-800c-240dc39bbfdf
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420804799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.sram_ctrl_max_throughput.1420804799
Directory /workspace/35.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_partial_access.2689230148
Short name T723
Test name
Test status
Simulation time 2001167237 ps
CPU time 74.71 seconds
Started Jun 30 04:45:16 PM PDT 24
Finished Jun 30 04:46:31 PM PDT 24
Peak memory 218932 kb
Host smart-a1b221e4-e47f-4922-8558-64cf47b28f2a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689230148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.sram_ctrl_mem_partial_access.2689230148
Directory /workspace/35.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_walk.3044794972
Short name T735
Test name
Test status
Simulation time 5366528657 ps
CPU time 148.63 seconds
Started Jun 30 04:45:16 PM PDT 24
Finished Jun 30 04:47:46 PM PDT 24
Peak memory 210888 kb
Host smart-d83869b6-2050-4cf9-8c5e-9a9d3c6698c2
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044794972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctr
l_mem_walk.3044794972
Directory /workspace/35.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/35.sram_ctrl_multiple_keys.2726019096
Short name T867
Test name
Test status
Simulation time 5421714607 ps
CPU time 135.55 seconds
Started Jun 30 04:45:03 PM PDT 24
Finished Jun 30 04:47:19 PM PDT 24
Peak memory 312248 kb
Host smart-2e59dd94-ccec-4afb-928a-802713697b21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726019096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multi
ple_keys.2726019096
Directory /workspace/35.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access.2566286338
Short name T757
Test name
Test status
Simulation time 455579546 ps
CPU time 30.86 seconds
Started Jun 30 04:45:02 PM PDT 24
Finished Jun 30 04:45:34 PM PDT 24
Peak memory 286160 kb
Host smart-de0ea8b8-82b3-4816-a27b-cc5db54c04e0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566286338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
sram_ctrl_partial_access.2566286338
Directory /workspace/35.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.678704922
Short name T662
Test name
Test status
Simulation time 7142034215 ps
CPU time 385.9 seconds
Started Jun 30 04:45:12 PM PDT 24
Finished Jun 30 04:51:38 PM PDT 24
Peak memory 202748 kb
Host smart-5f708aa3-b365-41d5-a9d7-f782089e4941
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678704922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.sram_ctrl_partial_access_b2b.678704922
Directory /workspace/35.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/35.sram_ctrl_ram_cfg.3198166841
Short name T710
Test name
Test status
Simulation time 1398248940 ps
CPU time 3.42 seconds
Started Jun 30 04:45:13 PM PDT 24
Finished Jun 30 04:45:17 PM PDT 24
Peak memory 202752 kb
Host smart-fbfd2cfd-089d-433a-bf2c-96dc9303bb5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198166841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.3198166841
Directory /workspace/35.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/35.sram_ctrl_regwen.2065046561
Short name T20
Test name
Test status
Simulation time 1659998162 ps
CPU time 293.57 seconds
Started Jun 30 04:45:12 PM PDT 24
Finished Jun 30 04:50:06 PM PDT 24
Peak memory 370592 kb
Host smart-3e656471-2c28-4e06-9a94-700d10942e39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065046561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.2065046561
Directory /workspace/35.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/35.sram_ctrl_smoke.715808672
Short name T477
Test name
Test status
Simulation time 4418061656 ps
CPU time 111.42 seconds
Started Jun 30 04:45:02 PM PDT 24
Finished Jun 30 04:46:54 PM PDT 24
Peak memory 338684 kb
Host smart-8ff986af-91d7-4790-9ab0-3580687bc1eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715808672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.715808672
Directory /workspace/35.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all.2199436808
Short name T823
Test name
Test status
Simulation time 57445237086 ps
CPU time 2551.23 seconds
Started Jun 30 04:45:16 PM PDT 24
Finished Jun 30 05:27:49 PM PDT 24
Peak memory 380620 kb
Host smart-e8bead79-aa26-40d0-aac8-a4646e52cc91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199436808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.sram_ctrl_stress_all.2199436808
Directory /workspace/35.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3394998124
Short name T65
Test name
Test status
Simulation time 3209523721 ps
CPU time 137.39 seconds
Started Jun 30 04:45:17 PM PDT 24
Finished Jun 30 04:47:35 PM PDT 24
Peak memory 337912 kb
Host smart-77fb98b6-3ac1-4a50-9159-13bb7f2b8c77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3394998124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.3394998124
Directory /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_pipeline.2824155011
Short name T275
Test name
Test status
Simulation time 2945987202 ps
CPU time 154.05 seconds
Started Jun 30 04:45:04 PM PDT 24
Finished Jun 30 04:47:38 PM PDT 24
Peak memory 202732 kb
Host smart-0e107518-2ecc-49c7-a38b-f53fc7968b5c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824155011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.sram_ctrl_stress_pipeline.2824155011
Directory /workspace/35.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.2471205558
Short name T863
Test name
Test status
Simulation time 2411661176 ps
CPU time 7.77 seconds
Started Jun 30 04:45:13 PM PDT 24
Finished Jun 30 04:45:21 PM PDT 24
Peak memory 216600 kb
Host smart-e1e025b5-78e6-4e1e-b442-2afa32b96344
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471205558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.2471205558
Directory /workspace/35.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/36.sram_ctrl_access_during_key_req.333355918
Short name T442
Test name
Test status
Simulation time 9421713256 ps
CPU time 431.86 seconds
Started Jun 30 04:45:12 PM PDT 24
Finished Jun 30 04:52:24 PM PDT 24
Peak memory 372552 kb
Host smart-c21f3e85-fb49-464c-b9fd-c5c5d8794c71
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333355918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 36.sram_ctrl_access_during_key_req.333355918
Directory /workspace/36.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/36.sram_ctrl_alert_test.3415164722
Short name T540
Test name
Test status
Simulation time 14093818 ps
CPU time 0.66 seconds
Started Jun 30 04:45:14 PM PDT 24
Finished Jun 30 04:45:15 PM PDT 24
Peak memory 202260 kb
Host smart-839c751b-c5aa-42f8-8138-481634d9d06c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415164722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.sram_ctrl_alert_test.3415164722
Directory /workspace/36.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sram_ctrl_bijection.1668979428
Short name T916
Test name
Test status
Simulation time 180490069919 ps
CPU time 2088.78 seconds
Started Jun 30 04:45:16 PM PDT 24
Finished Jun 30 05:20:06 PM PDT 24
Peak memory 203428 kb
Host smart-fa70af5d-a4bd-4e4a-b474-e2a31e8e0a6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668979428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection
.1668979428
Directory /workspace/36.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/36.sram_ctrl_executable.2245289723
Short name T599
Test name
Test status
Simulation time 27312466153 ps
CPU time 303.83 seconds
Started Jun 30 04:45:11 PM PDT 24
Finished Jun 30 04:50:15 PM PDT 24
Peak memory 299460 kb
Host smart-9d282e3e-9ec5-43c9-8665-df83ab67c2e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245289723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab
le.2245289723
Directory /workspace/36.sram_ctrl_executable/latest

Test location /workspace/coverage/default/36.sram_ctrl_lc_escalation.3163421800
Short name T339
Test name
Test status
Simulation time 48345874280 ps
CPU time 88.42 seconds
Started Jun 30 04:45:13 PM PDT 24
Finished Jun 30 04:46:42 PM PDT 24
Peak memory 202740 kb
Host smart-aa2ff4cd-51f9-42ce-9b67-b264b6a8e772
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163421800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es
calation.3163421800
Directory /workspace/36.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/36.sram_ctrl_max_throughput.1763072046
Short name T726
Test name
Test status
Simulation time 791931968 ps
CPU time 38.06 seconds
Started Jun 30 04:45:12 PM PDT 24
Finished Jun 30 04:45:51 PM PDT 24
Peak memory 292760 kb
Host smart-e09a82a1-4807-4dd8-8c35-d4d86c3cd125
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763072046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sram_ctrl_max_throughput.1763072046
Directory /workspace/36.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_partial_access.3821874078
Short name T55
Test name
Test status
Simulation time 19541033726 ps
CPU time 178.18 seconds
Started Jun 30 04:45:15 PM PDT 24
Finished Jun 30 04:48:13 PM PDT 24
Peak memory 219096 kb
Host smart-49b8495d-41e1-4e96-a18d-56d1ccaf2ea8
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821874078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.sram_ctrl_mem_partial_access.3821874078
Directory /workspace/36.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_walk.941513734
Short name T653
Test name
Test status
Simulation time 138242246597 ps
CPU time 186.4 seconds
Started Jun 30 04:45:14 PM PDT 24
Finished Jun 30 04:48:21 PM PDT 24
Peak memory 203524 kb
Host smart-8d0a8d18-30f1-4fbd-a2c9-4cadae1c4f84
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941513734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl
_mem_walk.941513734
Directory /workspace/36.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/36.sram_ctrl_multiple_keys.514021582
Short name T184
Test name
Test status
Simulation time 61229889658 ps
CPU time 1297.54 seconds
Started Jun 30 04:45:16 PM PDT 24
Finished Jun 30 05:06:55 PM PDT 24
Peak memory 380668 kb
Host smart-a79f918e-3755-43e7-9ec6-5d20d74f6c2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514021582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multip
le_keys.514021582
Directory /workspace/36.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access.2993522029
Short name T529
Test name
Test status
Simulation time 941971677 ps
CPU time 37.09 seconds
Started Jun 30 04:45:14 PM PDT 24
Finished Jun 30 04:45:52 PM PDT 24
Peak memory 274104 kb
Host smart-3a2dba37-d178-48d5-8066-c859a57a1538
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993522029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
sram_ctrl_partial_access.2993522029
Directory /workspace/36.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.2581187084
Short name T528
Test name
Test status
Simulation time 13169361520 ps
CPU time 307.56 seconds
Started Jun 30 04:45:16 PM PDT 24
Finished Jun 30 04:50:25 PM PDT 24
Peak memory 202692 kb
Host smart-c4f1d112-f87c-4889-998d-f1bb17ce3f77
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581187084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 36.sram_ctrl_partial_access_b2b.2581187084
Directory /workspace/36.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/36.sram_ctrl_ram_cfg.3609020797
Short name T780
Test name
Test status
Simulation time 1406860009 ps
CPU time 3.49 seconds
Started Jun 30 04:45:17 PM PDT 24
Finished Jun 30 04:45:21 PM PDT 24
Peak memory 202776 kb
Host smart-f74a02d7-626a-413c-8762-07f36e58aa1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609020797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.3609020797
Directory /workspace/36.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/36.sram_ctrl_regwen.1822350847
Short name T554
Test name
Test status
Simulation time 9034561707 ps
CPU time 467.84 seconds
Started Jun 30 04:45:13 PM PDT 24
Finished Jun 30 04:53:01 PM PDT 24
Peak memory 376544 kb
Host smart-2df27f0d-452b-452b-b5b2-a995d59b7ee6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822350847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.1822350847
Directory /workspace/36.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/36.sram_ctrl_smoke.2219764450
Short name T636
Test name
Test status
Simulation time 1426243914 ps
CPU time 153.04 seconds
Started Jun 30 04:45:16 PM PDT 24
Finished Jun 30 04:47:49 PM PDT 24
Peak memory 368192 kb
Host smart-95a01de6-4d2f-4231-8b86-25cf9ebe5311
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219764450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.2219764450
Directory /workspace/36.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all.3662388754
Short name T469
Test name
Test status
Simulation time 143615202148 ps
CPU time 5197.43 seconds
Started Jun 30 04:45:12 PM PDT 24
Finished Jun 30 06:11:51 PM PDT 24
Peak memory 381748 kb
Host smart-c73851bc-0f0c-4156-8680-adbe9227feb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662388754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 36.sram_ctrl_stress_all.3662388754
Directory /workspace/36.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.2090500105
Short name T112
Test name
Test status
Simulation time 1478582667 ps
CPU time 9.87 seconds
Started Jun 30 04:45:17 PM PDT 24
Finished Jun 30 04:45:28 PM PDT 24
Peak memory 210956 kb
Host smart-5fc3eec2-f2d1-4868-8de8-f33320fd80cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2090500105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.2090500105
Directory /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_pipeline.369780912
Short name T787
Test name
Test status
Simulation time 18718952222 ps
CPU time 264.94 seconds
Started Jun 30 04:45:16 PM PDT 24
Finished Jun 30 04:49:41 PM PDT 24
Peak memory 202712 kb
Host smart-198c1b1a-ffac-4c8b-a5c2-0c88279ed68c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369780912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.sram_ctrl_stress_pipeline.369780912
Directory /workspace/36.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.907377165
Short name T285
Test name
Test status
Simulation time 2721845076 ps
CPU time 39.54 seconds
Started Jun 30 04:45:11 PM PDT 24
Finished Jun 30 04:45:51 PM PDT 24
Peak memory 300736 kb
Host smart-83db7765-85b4-4ab9-8f1f-a532b9572aba
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907377165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sram_ctrl_throughput_w_partial_write.907377165
Directory /workspace/36.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/37.sram_ctrl_access_during_key_req.189499676
Short name T768
Test name
Test status
Simulation time 13743039516 ps
CPU time 1309.02 seconds
Started Jun 30 04:45:20 PM PDT 24
Finished Jun 30 05:07:10 PM PDT 24
Peak memory 376576 kb
Host smart-9cd53556-96cf-4d3d-b490-6f99d8577f57
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189499676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 37.sram_ctrl_access_during_key_req.189499676
Directory /workspace/37.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/37.sram_ctrl_alert_test.1544552323
Short name T534
Test name
Test status
Simulation time 13532475 ps
CPU time 0.64 seconds
Started Jun 30 04:45:23 PM PDT 24
Finished Jun 30 04:45:24 PM PDT 24
Peak memory 201976 kb
Host smart-1fbed779-858b-40aa-ac3f-a59f48a90cb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544552323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.sram_ctrl_alert_test.1544552323
Directory /workspace/37.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sram_ctrl_bijection.3964039723
Short name T423
Test name
Test status
Simulation time 199981808170 ps
CPU time 1422.1 seconds
Started Jun 30 04:45:19 PM PDT 24
Finished Jun 30 05:09:02 PM PDT 24
Peak memory 203428 kb
Host smart-f6747ae2-0ad1-444c-87cd-1e2c403f1487
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964039723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection
.3964039723
Directory /workspace/37.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/37.sram_ctrl_executable.438610424
Short name T766
Test name
Test status
Simulation time 29235815339 ps
CPU time 863.3 seconds
Started Jun 30 04:45:19 PM PDT 24
Finished Jun 30 04:59:43 PM PDT 24
Peak memory 372496 kb
Host smart-bc7c3d7f-bc3e-4826-a2ed-497caeb0a172
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438610424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executabl
e.438610424
Directory /workspace/37.sram_ctrl_executable/latest

Test location /workspace/coverage/default/37.sram_ctrl_lc_escalation.207178949
Short name T566
Test name
Test status
Simulation time 182390644423 ps
CPU time 94.81 seconds
Started Jun 30 04:45:20 PM PDT 24
Finished Jun 30 04:46:55 PM PDT 24
Peak memory 202784 kb
Host smart-dd2e9dc3-7580-4404-ac9a-137627c17857
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207178949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_esc
alation.207178949
Directory /workspace/37.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/37.sram_ctrl_max_throughput.3280433962
Short name T696
Test name
Test status
Simulation time 2889261482 ps
CPU time 18.33 seconds
Started Jun 30 04:45:24 PM PDT 24
Finished Jun 30 04:45:43 PM PDT 24
Peak memory 252100 kb
Host smart-40a9197e-efd9-4717-ba78-8f41e11af7ae
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280433962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.sram_ctrl_max_throughput.3280433962
Directory /workspace/37.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_walk.2353601117
Short name T36
Test name
Test status
Simulation time 21323176166 ps
CPU time 346.6 seconds
Started Jun 30 04:45:19 PM PDT 24
Finished Jun 30 04:51:06 PM PDT 24
Peak memory 210976 kb
Host smart-13ffe632-941a-4122-8ccb-d7310949ff83
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353601117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr
l_mem_walk.2353601117
Directory /workspace/37.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/37.sram_ctrl_multiple_keys.2330653317
Short name T832
Test name
Test status
Simulation time 27210623284 ps
CPU time 562.24 seconds
Started Jun 30 04:45:16 PM PDT 24
Finished Jun 30 04:54:39 PM PDT 24
Peak memory 366284 kb
Host smart-2dd6dcea-a20c-4c3d-bcca-ed0469f51142
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330653317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multi
ple_keys.2330653317
Directory /workspace/37.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access.1259281524
Short name T875
Test name
Test status
Simulation time 6533398722 ps
CPU time 29.76 seconds
Started Jun 30 04:45:20 PM PDT 24
Finished Jun 30 04:45:50 PM PDT 24
Peak memory 202748 kb
Host smart-da2d318d-ae4d-49c8-a2ee-92326a3b5f37
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259281524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
sram_ctrl_partial_access.1259281524
Directory /workspace/37.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.3643410713
Short name T801
Test name
Test status
Simulation time 8727644663 ps
CPU time 243.77 seconds
Started Jun 30 04:45:20 PM PDT 24
Finished Jun 30 04:49:24 PM PDT 24
Peak memory 202732 kb
Host smart-cadc384c-1c18-4bc1-af66-51cd91df1452
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643410713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 37.sram_ctrl_partial_access_b2b.3643410713
Directory /workspace/37.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/37.sram_ctrl_ram_cfg.1614904615
Short name T708
Test name
Test status
Simulation time 709280691 ps
CPU time 3.34 seconds
Started Jun 30 04:45:23 PM PDT 24
Finished Jun 30 04:45:26 PM PDT 24
Peak memory 202672 kb
Host smart-a9568a62-8b5b-4e86-a82f-d4e92b919ec4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614904615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.1614904615
Directory /workspace/37.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/37.sram_ctrl_regwen.204281991
Short name T645
Test name
Test status
Simulation time 13851051700 ps
CPU time 1056.23 seconds
Started Jun 30 04:45:20 PM PDT 24
Finished Jun 30 05:02:57 PM PDT 24
Peak memory 379736 kb
Host smart-fdb3c875-d09f-40d3-94bb-34dd044c850f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204281991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.204281991
Directory /workspace/37.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/37.sram_ctrl_smoke.148487093
Short name T192
Test name
Test status
Simulation time 2963630147 ps
CPU time 42.16 seconds
Started Jun 30 04:45:13 PM PDT 24
Finished Jun 30 04:45:56 PM PDT 24
Peak memory 295680 kb
Host smart-0304f010-a2a5-449e-9f18-8e116392e790
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148487093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.148487093
Directory /workspace/37.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all.718716868
Short name T736
Test name
Test status
Simulation time 183546429802 ps
CPU time 2763.73 seconds
Started Jun 30 04:45:21 PM PDT 24
Finished Jun 30 05:31:26 PM PDT 24
Peak memory 382740 kb
Host smart-40f0f899-5439-4a2e-8eab-7e5721375664
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718716868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 37.sram_ctrl_stress_all.718716868
Directory /workspace/37.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2987356111
Short name T356
Test name
Test status
Simulation time 10719868277 ps
CPU time 110.75 seconds
Started Jun 30 04:45:18 PM PDT 24
Finished Jun 30 04:47:09 PM PDT 24
Peak memory 338808 kb
Host smart-dfbd74b3-abaa-4e76-bb54-827a67923f42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2987356111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.2987356111
Directory /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_pipeline.1016384519
Short name T886
Test name
Test status
Simulation time 22343930633 ps
CPU time 334.09 seconds
Started Jun 30 04:45:25 PM PDT 24
Finished Jun 30 04:50:59 PM PDT 24
Peak memory 203048 kb
Host smart-daee84c4-fb5e-4afb-b4d9-d990e38b2a0d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016384519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_stress_pipeline.1016384519
Directory /workspace/37.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.4195807631
Short name T145
Test name
Test status
Simulation time 1515903910 ps
CPU time 36.25 seconds
Started Jun 30 04:45:19 PM PDT 24
Finished Jun 30 04:45:56 PM PDT 24
Peak memory 284424 kb
Host smart-16cbfeb2-b7a1-4fdc-8a10-dcb3d188dd15
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195807631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.4195807631
Directory /workspace/37.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/38.sram_ctrl_access_during_key_req.2215305956
Short name T789
Test name
Test status
Simulation time 9415851729 ps
CPU time 942.36 seconds
Started Jun 30 04:45:21 PM PDT 24
Finished Jun 30 05:01:04 PM PDT 24
Peak memory 377624 kb
Host smart-24312e9c-33c8-4412-8ff5-66e3fc63d449
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215305956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.sram_ctrl_access_during_key_req.2215305956
Directory /workspace/38.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/38.sram_ctrl_alert_test.3664207877
Short name T866
Test name
Test status
Simulation time 62416460 ps
CPU time 0.66 seconds
Started Jun 30 04:45:21 PM PDT 24
Finished Jun 30 04:45:22 PM PDT 24
Peak memory 202444 kb
Host smart-035d1975-872d-4971-8b24-61b889170426
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664207877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.sram_ctrl_alert_test.3664207877
Directory /workspace/38.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sram_ctrl_bijection.1270500952
Short name T208
Test name
Test status
Simulation time 41197586846 ps
CPU time 1166.62 seconds
Started Jun 30 04:45:24 PM PDT 24
Finished Jun 30 05:04:51 PM PDT 24
Peak memory 203896 kb
Host smart-e8e1892f-af6b-4b38-a2d3-ffac4b740fc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270500952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection
.1270500952
Directory /workspace/38.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/38.sram_ctrl_executable.3087718174
Short name T425
Test name
Test status
Simulation time 19206799405 ps
CPU time 817.13 seconds
Started Jun 30 04:45:22 PM PDT 24
Finished Jun 30 04:58:59 PM PDT 24
Peak memory 378676 kb
Host smart-ad66a016-0ca1-49a0-b026-71a826d91046
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087718174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executab
le.3087718174
Directory /workspace/38.sram_ctrl_executable/latest

Test location /workspace/coverage/default/38.sram_ctrl_max_throughput.1405351225
Short name T859
Test name
Test status
Simulation time 2914249423 ps
CPU time 20.65 seconds
Started Jun 30 04:45:20 PM PDT 24
Finished Jun 30 04:45:42 PM PDT 24
Peak memory 254492 kb
Host smart-e5cbde30-4861-4b12-82aa-cd31e1204b18
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405351225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.sram_ctrl_max_throughput.1405351225
Directory /workspace/38.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_partial_access.3762514500
Short name T310
Test name
Test status
Simulation time 9526009929 ps
CPU time 86.93 seconds
Started Jun 30 04:45:20 PM PDT 24
Finished Jun 30 04:46:47 PM PDT 24
Peak memory 210968 kb
Host smart-78b5e12d-ca53-4b5f-97f7-0390ab8aee4c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762514500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.sram_ctrl_mem_partial_access.3762514500
Directory /workspace/38.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_walk.2744961573
Short name T408
Test name
Test status
Simulation time 14129830027 ps
CPU time 302.66 seconds
Started Jun 30 04:45:20 PM PDT 24
Finished Jun 30 04:50:23 PM PDT 24
Peak memory 210792 kb
Host smart-fb7d81ff-fa2c-402e-8f4e-f825b27fcd7c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744961573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr
l_mem_walk.2744961573
Directory /workspace/38.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/38.sram_ctrl_multiple_keys.1468844800
Short name T693
Test name
Test status
Simulation time 5323417229 ps
CPU time 447.12 seconds
Started Jun 30 04:45:19 PM PDT 24
Finished Jun 30 04:52:46 PM PDT 24
Peak memory 370372 kb
Host smart-32f74c9b-3f1f-488c-ba48-c8799328f072
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468844800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multi
ple_keys.1468844800
Directory /workspace/38.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access.677498011
Short name T783
Test name
Test status
Simulation time 1316888933 ps
CPU time 16.63 seconds
Started Jun 30 04:45:18 PM PDT 24
Finished Jun 30 04:45:35 PM PDT 24
Peak memory 202616 kb
Host smart-a1b4b800-327c-4b74-b1e5-ed5ff40de00b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677498011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.s
ram_ctrl_partial_access.677498011
Directory /workspace/38.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.4074765483
Short name T488
Test name
Test status
Simulation time 43236551175 ps
CPU time 269.2 seconds
Started Jun 30 04:45:25 PM PDT 24
Finished Jun 30 04:49:55 PM PDT 24
Peak memory 202740 kb
Host smart-4e927998-7eb3-493a-af8b-c3e67ec8b2dc
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074765483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 38.sram_ctrl_partial_access_b2b.4074765483
Directory /workspace/38.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/38.sram_ctrl_ram_cfg.196758458
Short name T836
Test name
Test status
Simulation time 1409839052 ps
CPU time 3.54 seconds
Started Jun 30 04:45:19 PM PDT 24
Finished Jun 30 04:45:23 PM PDT 24
Peak memory 202676 kb
Host smart-fa46a9da-2aeb-4762-b6f2-75fee0b13c2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196758458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.196758458
Directory /workspace/38.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/38.sram_ctrl_regwen.2142381347
Short name T494
Test name
Test status
Simulation time 19606855725 ps
CPU time 793.39 seconds
Started Jun 30 04:45:21 PM PDT 24
Finished Jun 30 04:58:35 PM PDT 24
Peak memory 374456 kb
Host smart-73ca28d6-064c-4c2e-9563-ef70afe1444d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142381347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.2142381347
Directory /workspace/38.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/38.sram_ctrl_smoke.2286668414
Short name T140
Test name
Test status
Simulation time 1687358099 ps
CPU time 8.13 seconds
Started Jun 30 04:45:25 PM PDT 24
Finished Jun 30 04:45:34 PM PDT 24
Peak memory 202640 kb
Host smart-3c9f11d3-cbf8-4a19-8589-d4e8732bab30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286668414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.2286668414
Directory /workspace/38.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_all.4023446252
Short name T186
Test name
Test status
Simulation time 985717848385 ps
CPU time 6296.77 seconds
Started Jun 30 04:45:25 PM PDT 24
Finished Jun 30 06:30:23 PM PDT 24
Peak memory 387816 kb
Host smart-e224193e-1d1c-473c-a4a2-eb387b86a32e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023446252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 38.sram_ctrl_stress_all.4023446252
Directory /workspace/38.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1930802231
Short name T294
Test name
Test status
Simulation time 2522538147 ps
CPU time 54.63 seconds
Started Jun 30 04:45:21 PM PDT 24
Finished Jun 30 04:46:16 PM PDT 24
Peak memory 280396 kb
Host smart-7a53b0ea-79f9-4b50-9f0e-b6c37d7b7a8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1930802231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.1930802231
Directory /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_pipeline.4036332689
Short name T840
Test name
Test status
Simulation time 4465204483 ps
CPU time 333.32 seconds
Started Jun 30 04:45:21 PM PDT 24
Finished Jun 30 04:50:55 PM PDT 24
Peak memory 202620 kb
Host smart-e00a9725-d7ae-4cae-82b5-1efbc24681a7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036332689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.sram_ctrl_stress_pipeline.4036332689
Directory /workspace/38.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.4230819319
Short name T764
Test name
Test status
Simulation time 1584864363 ps
CPU time 62.89 seconds
Started Jun 30 04:45:22 PM PDT 24
Finished Jun 30 04:46:25 PM PDT 24
Peak memory 312936 kb
Host smart-b2c9de30-d888-4e08-aa2e-c780ba730d4f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230819319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.4230819319
Directory /workspace/38.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/39.sram_ctrl_access_during_key_req.3493546420
Short name T296
Test name
Test status
Simulation time 4972281209 ps
CPU time 355.74 seconds
Started Jun 30 04:45:30 PM PDT 24
Finished Jun 30 04:51:26 PM PDT 24
Peak memory 371564 kb
Host smart-5a3a70d4-86e0-4658-ac45-c01f16aa2dbe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493546420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.sram_ctrl_access_during_key_req.3493546420
Directory /workspace/39.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/39.sram_ctrl_alert_test.3876371567
Short name T924
Test name
Test status
Simulation time 105370821 ps
CPU time 0.67 seconds
Started Jun 30 04:45:27 PM PDT 24
Finished Jun 30 04:45:28 PM PDT 24
Peak memory 202448 kb
Host smart-0f1182e0-099e-464c-9226-b8af2939655b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876371567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.sram_ctrl_alert_test.3876371567
Directory /workspace/39.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sram_ctrl_bijection.420103227
Short name T86
Test name
Test status
Simulation time 35466949294 ps
CPU time 583.2 seconds
Started Jun 30 04:45:20 PM PDT 24
Finished Jun 30 04:55:03 PM PDT 24
Peak memory 203472 kb
Host smart-cad8973a-0264-4559-a304-5d670a0d61e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420103227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection.
420103227
Directory /workspace/39.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/39.sram_ctrl_executable.586121879
Short name T724
Test name
Test status
Simulation time 25292142916 ps
CPU time 1206.12 seconds
Started Jun 30 04:45:27 PM PDT 24
Finished Jun 30 05:05:34 PM PDT 24
Peak memory 379788 kb
Host smart-52d7aa7c-e604-4451-8b79-1c063a4b639f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586121879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executabl
e.586121879
Directory /workspace/39.sram_ctrl_executable/latest

Test location /workspace/coverage/default/39.sram_ctrl_lc_escalation.1772177349
Short name T560
Test name
Test status
Simulation time 32760218380 ps
CPU time 34.85 seconds
Started Jun 30 04:45:31 PM PDT 24
Finished Jun 30 04:46:07 PM PDT 24
Peak memory 202820 kb
Host smart-4017c154-7685-4ce9-9046-fdf52733c026
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772177349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es
calation.1772177349
Directory /workspace/39.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/39.sram_ctrl_max_throughput.2829381621
Short name T163
Test name
Test status
Simulation time 15242579294 ps
CPU time 122.31 seconds
Started Jun 30 04:45:31 PM PDT 24
Finished Jun 30 04:47:34 PM PDT 24
Peak memory 370676 kb
Host smart-7f2c5be2-c966-42a9-b06d-7298d10294be
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829381621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.sram_ctrl_max_throughput.2829381621
Directory /workspace/39.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_partial_access.343911411
Short name T709
Test name
Test status
Simulation time 10472400625 ps
CPU time 174.6 seconds
Started Jun 30 04:45:26 PM PDT 24
Finished Jun 30 04:48:21 PM PDT 24
Peak memory 210920 kb
Host smart-953c0002-05a7-48fc-8b91-9ccce7b98e90
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343911411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.sram_ctrl_mem_partial_access.343911411
Directory /workspace/39.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_walk.1947735565
Short name T593
Test name
Test status
Simulation time 31413071646 ps
CPU time 171.75 seconds
Started Jun 30 04:45:32 PM PDT 24
Finished Jun 30 04:48:24 PM PDT 24
Peak memory 210916 kb
Host smart-4b2e5397-c2bd-4a97-8ef1-859c787bb9ea
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947735565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr
l_mem_walk.1947735565
Directory /workspace/39.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/39.sram_ctrl_multiple_keys.585588988
Short name T782
Test name
Test status
Simulation time 65181385964 ps
CPU time 1441.47 seconds
Started Jun 30 04:45:22 PM PDT 24
Finished Jun 30 05:09:24 PM PDT 24
Peak memory 379660 kb
Host smart-e0d77065-a54f-4a33-b108-ef6a73f6b04f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585588988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multip
le_keys.585588988
Directory /workspace/39.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access.1284063547
Short name T418
Test name
Test status
Simulation time 5276219533 ps
CPU time 12.01 seconds
Started Jun 30 04:45:20 PM PDT 24
Finished Jun 30 04:45:33 PM PDT 24
Peak memory 202728 kb
Host smart-448a6ce9-ff58-4297-bf4f-05089f621841
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284063547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
sram_ctrl_partial_access.1284063547
Directory /workspace/39.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.1063293188
Short name T937
Test name
Test status
Simulation time 10646773599 ps
CPU time 315.45 seconds
Started Jun 30 04:45:30 PM PDT 24
Finished Jun 30 04:50:46 PM PDT 24
Peak memory 202708 kb
Host smart-4b64349c-0a0c-444a-a86b-7c2d9c383e2c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063293188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 39.sram_ctrl_partial_access_b2b.1063293188
Directory /workspace/39.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/39.sram_ctrl_ram_cfg.3869803980
Short name T33
Test name
Test status
Simulation time 1775196611 ps
CPU time 3.68 seconds
Started Jun 30 04:45:31 PM PDT 24
Finished Jun 30 04:45:35 PM PDT 24
Peak memory 202648 kb
Host smart-9f02e26d-cc78-4cf3-a36d-974c0af226ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869803980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.3869803980
Directory /workspace/39.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/39.sram_ctrl_regwen.3759287366
Short name T146
Test name
Test status
Simulation time 42214187193 ps
CPU time 611.7 seconds
Started Jun 30 04:45:29 PM PDT 24
Finished Jun 30 04:55:41 PM PDT 24
Peak memory 376548 kb
Host smart-f0507aed-9648-4ec2-9373-cea131f6438e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759287366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.3759287366
Directory /workspace/39.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/39.sram_ctrl_smoke.1117189840
Short name T911
Test name
Test status
Simulation time 420967085 ps
CPU time 4.84 seconds
Started Jun 30 04:45:25 PM PDT 24
Finished Jun 30 04:45:30 PM PDT 24
Peak memory 208600 kb
Host smart-8b3745e0-dc31-4e2b-a07d-7dc1eec56cce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117189840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.1117189840
Directory /workspace/39.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1513522738
Short name T476
Test name
Test status
Simulation time 10598612378 ps
CPU time 44.27 seconds
Started Jun 30 04:45:27 PM PDT 24
Finished Jun 30 04:46:11 PM PDT 24
Peak memory 212740 kb
Host smart-f8d4e534-d957-43b7-8eb4-1550541c8895
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1513522738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.1513522738
Directory /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_pipeline.2565434053
Short name T506
Test name
Test status
Simulation time 4060843221 ps
CPU time 328.95 seconds
Started Jun 30 04:45:24 PM PDT 24
Finished Jun 30 04:50:53 PM PDT 24
Peak memory 202720 kb
Host smart-729dd247-3b3c-48c8-b4c1-56d934d2b79f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565434053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.sram_ctrl_stress_pipeline.2565434053
Directory /workspace/39.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.4104310277
Short name T615
Test name
Test status
Simulation time 769246202 ps
CPU time 117.48 seconds
Started Jun 30 04:45:28 PM PDT 24
Finished Jun 30 04:47:26 PM PDT 24
Peak memory 348804 kb
Host smart-d8bf4c77-40e8-4310-9992-5c4c438bb845
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104310277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.4104310277
Directory /workspace/39.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/4.sram_ctrl_access_during_key_req.2743113354
Short name T597
Test name
Test status
Simulation time 47732997648 ps
CPU time 884.96 seconds
Started Jun 30 04:43:36 PM PDT 24
Finished Jun 30 04:58:21 PM PDT 24
Peak memory 363024 kb
Host smart-4263b028-c27f-4649-994d-b6f449500f2c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743113354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_access_during_key_req.2743113354
Directory /workspace/4.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/4.sram_ctrl_alert_test.3268792274
Short name T11
Test name
Test status
Simulation time 13743990 ps
CPU time 0.63 seconds
Started Jun 30 04:43:51 PM PDT 24
Finished Jun 30 04:43:53 PM PDT 24
Peak memory 202184 kb
Host smart-dc98d8c0-909d-4cab-bfa9-4d6c6ffa129f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268792274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_alert_test.3268792274
Directory /workspace/4.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sram_ctrl_bijection.555184864
Short name T668
Test name
Test status
Simulation time 33953966545 ps
CPU time 749.77 seconds
Started Jun 30 04:43:38 PM PDT 24
Finished Jun 30 04:56:08 PM PDT 24
Peak memory 203396 kb
Host smart-348c667c-59f8-4596-9e08-12a8f2dd2c14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555184864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.555184864
Directory /workspace/4.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/4.sram_ctrl_executable.3103115011
Short name T831
Test name
Test status
Simulation time 26317694332 ps
CPU time 1844.54 seconds
Started Jun 30 04:43:37 PM PDT 24
Finished Jun 30 05:14:23 PM PDT 24
Peak memory 378580 kb
Host smart-2fb5eae5-7ed5-4f1e-a229-1b779743c10f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103115011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executabl
e.3103115011
Directory /workspace/4.sram_ctrl_executable/latest

Test location /workspace/coverage/default/4.sram_ctrl_lc_escalation.1521120918
Short name T222
Test name
Test status
Simulation time 24142049539 ps
CPU time 38.37 seconds
Started Jun 30 04:43:45 PM PDT 24
Finished Jun 30 04:44:24 PM PDT 24
Peak memory 202780 kb
Host smart-9ed9f351-9056-40e8-a1e4-d68eac8045fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521120918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esc
alation.1521120918
Directory /workspace/4.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/4.sram_ctrl_max_throughput.816431317
Short name T225
Test name
Test status
Simulation time 8661385249 ps
CPU time 18.08 seconds
Started Jun 30 04:43:52 PM PDT 24
Finished Jun 30 04:44:11 PM PDT 24
Peak memory 250916 kb
Host smart-5933b52f-b37f-4663-8593-e6e3badc1056
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816431317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.sram_ctrl_max_throughput.816431317
Directory /workspace/4.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_partial_access.2567619947
Short name T521
Test name
Test status
Simulation time 2734897830 ps
CPU time 87.59 seconds
Started Jun 30 04:43:39 PM PDT 24
Finished Jun 30 04:45:07 PM PDT 24
Peak memory 219008 kb
Host smart-719d52ed-315d-475f-baa9-76e071089966
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567619947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_mem_partial_access.2567619947
Directory /workspace/4.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_walk.1441566076
Short name T868
Test name
Test status
Simulation time 27676047095 ps
CPU time 327.68 seconds
Started Jun 30 04:43:51 PM PDT 24
Finished Jun 30 04:49:20 PM PDT 24
Peak memory 202604 kb
Host smart-d12ebfbc-bfec-45c1-b0e7-832f877e1b7e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441566076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl
_mem_walk.1441566076
Directory /workspace/4.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/4.sram_ctrl_multiple_keys.2424173545
Short name T429
Test name
Test status
Simulation time 260736048189 ps
CPU time 948.41 seconds
Started Jun 30 04:43:34 PM PDT 24
Finished Jun 30 04:59:23 PM PDT 24
Peak memory 373436 kb
Host smart-6a164252-30f0-4a8f-82e9-0d629c39b99f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424173545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip
le_keys.2424173545
Directory /workspace/4.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access.2290042652
Short name T295
Test name
Test status
Simulation time 756221256 ps
CPU time 4.39 seconds
Started Jun 30 04:43:43 PM PDT 24
Finished Jun 30 04:43:48 PM PDT 24
Peak memory 202600 kb
Host smart-fc8d31f3-a183-480f-bc4c-9e97fb4e7b7b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290042652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s
ram_ctrl_partial_access.2290042652
Directory /workspace/4.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.3979781016
Short name T254
Test name
Test status
Simulation time 8131650501 ps
CPU time 439.57 seconds
Started Jun 30 04:43:48 PM PDT 24
Finished Jun 30 04:51:09 PM PDT 24
Peak memory 202732 kb
Host smart-dc1ef565-9c66-42db-8f02-6decbfc972be
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979781016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 4.sram_ctrl_partial_access_b2b.3979781016
Directory /workspace/4.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/4.sram_ctrl_ram_cfg.2895838919
Short name T182
Test name
Test status
Simulation time 709977305 ps
CPU time 3.16 seconds
Started Jun 30 04:43:47 PM PDT 24
Finished Jun 30 04:43:51 PM PDT 24
Peak memory 202664 kb
Host smart-e0e2d841-becf-4cf9-83b4-5e703f45d075
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895838919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.2895838919
Directory /workspace/4.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/4.sram_ctrl_regwen.4193768144
Short name T483
Test name
Test status
Simulation time 9917184403 ps
CPU time 497.66 seconds
Started Jun 30 04:43:48 PM PDT 24
Finished Jun 30 04:52:06 PM PDT 24
Peak memory 370420 kb
Host smart-9a262fc4-7b9d-4046-823f-db25ee885ccf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193768144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.4193768144
Directory /workspace/4.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/4.sram_ctrl_sec_cm.3331906869
Short name T29
Test name
Test status
Simulation time 629537095 ps
CPU time 3.79 seconds
Started Jun 30 04:43:56 PM PDT 24
Finished Jun 30 04:44:01 PM PDT 24
Peak memory 222112 kb
Host smart-9ffbcb40-e771-4b8a-a547-15dcfe94a7fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331906869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_sec_cm.3331906869
Directory /workspace/4.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sram_ctrl_smoke.2786560156
Short name T584
Test name
Test status
Simulation time 17273341287 ps
CPU time 16.97 seconds
Started Jun 30 04:43:51 PM PDT 24
Finished Jun 30 04:44:09 PM PDT 24
Peak memory 202760 kb
Host smart-9b7fee6d-513f-4803-a26c-c70634e3971c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786560156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.2786560156
Directory /workspace/4.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all.4160876895
Short name T396
Test name
Test status
Simulation time 195978937570 ps
CPU time 2526.92 seconds
Started Jun 30 04:43:44 PM PDT 24
Finished Jun 30 05:25:51 PM PDT 24
Peak memory 388812 kb
Host smart-5370a797-3981-46a3-b945-33aa58f5797c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160876895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 4.sram_ctrl_stress_all.4160876895
Directory /workspace/4.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1911856067
Short name T530
Test name
Test status
Simulation time 322436761 ps
CPU time 10.79 seconds
Started Jun 30 04:43:54 PM PDT 24
Finished Jun 30 04:44:06 PM PDT 24
Peak memory 210920 kb
Host smart-3094a2ef-c81b-421f-bdeb-cca346aa501d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1911856067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.1911856067
Directory /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_pipeline.4231646886
Short name T909
Test name
Test status
Simulation time 21537968921 ps
CPU time 306.81 seconds
Started Jun 30 04:43:50 PM PDT 24
Finished Jun 30 04:48:58 PM PDT 24
Peak memory 202744 kb
Host smart-929cebe9-5cdc-4669-af9f-a1ee89ee4d93
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231646886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_stress_pipeline.4231646886
Directory /workspace/4.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.811476319
Short name T350
Test name
Test status
Simulation time 1544945573 ps
CPU time 12.78 seconds
Started Jun 30 04:43:37 PM PDT 24
Finished Jun 30 04:43:50 PM PDT 24
Peak memory 237356 kb
Host smart-2c12ce56-3267-4df4-9e6f-0fe10220240c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811476319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.sram_ctrl_throughput_w_partial_write.811476319
Directory /workspace/4.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/40.sram_ctrl_access_during_key_req.1130308650
Short name T848
Test name
Test status
Simulation time 14414784396 ps
CPU time 1164.1 seconds
Started Jun 30 04:45:31 PM PDT 24
Finished Jun 30 05:04:55 PM PDT 24
Peak memory 379312 kb
Host smart-0f5f18d7-1543-4387-bc95-b0637b77acfb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130308650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.sram_ctrl_access_during_key_req.1130308650
Directory /workspace/40.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/40.sram_ctrl_alert_test.4082725044
Short name T514
Test name
Test status
Simulation time 40538576 ps
CPU time 0.62 seconds
Started Jun 30 04:45:34 PM PDT 24
Finished Jun 30 04:45:35 PM PDT 24
Peak memory 202444 kb
Host smart-3b6b77c3-1610-49d1-bae5-324490cc45ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082725044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.sram_ctrl_alert_test.4082725044
Directory /workspace/40.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sram_ctrl_bijection.844578207
Short name T551
Test name
Test status
Simulation time 339890521059 ps
CPU time 1565.43 seconds
Started Jun 30 04:45:28 PM PDT 24
Finished Jun 30 05:11:34 PM PDT 24
Peak memory 202848 kb
Host smart-4758a7a8-dfe4-4a22-97bd-39199b47c7f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844578207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection.
844578207
Directory /workspace/40.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/40.sram_ctrl_executable.2075710057
Short name T707
Test name
Test status
Simulation time 16209378906 ps
CPU time 814.31 seconds
Started Jun 30 04:45:29 PM PDT 24
Finished Jun 30 04:59:03 PM PDT 24
Peak memory 369856 kb
Host smart-bb97ce83-b39a-4931-a57a-7447c96c71d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075710057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executab
le.2075710057
Directory /workspace/40.sram_ctrl_executable/latest

Test location /workspace/coverage/default/40.sram_ctrl_lc_escalation.2879762567
Short name T713
Test name
Test status
Simulation time 83743195696 ps
CPU time 106.09 seconds
Started Jun 30 04:45:27 PM PDT 24
Finished Jun 30 04:47:13 PM PDT 24
Peak memory 202736 kb
Host smart-83998522-e710-4954-b744-242e24e7f303
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879762567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_es
calation.2879762567
Directory /workspace/40.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/40.sram_ctrl_max_throughput.3970059195
Short name T520
Test name
Test status
Simulation time 772064572 ps
CPU time 116.62 seconds
Started Jun 30 04:45:28 PM PDT 24
Finished Jun 30 04:47:25 PM PDT 24
Peak memory 370240 kb
Host smart-e8cec9cd-78c9-4001-b00f-1aeeb1e67989
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970059195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.sram_ctrl_max_throughput.3970059195
Directory /workspace/40.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_partial_access.492018974
Short name T60
Test name
Test status
Simulation time 10176020375 ps
CPU time 161.4 seconds
Started Jun 30 04:45:35 PM PDT 24
Finished Jun 30 04:48:17 PM PDT 24
Peak memory 219080 kb
Host smart-a3a22420-5866-4bc8-8f2b-695bdd07db48
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492018974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.sram_ctrl_mem_partial_access.492018974
Directory /workspace/40.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_walk.2285514292
Short name T50
Test name
Test status
Simulation time 57669485185 ps
CPU time 313.07 seconds
Started Jun 30 04:45:39 PM PDT 24
Finished Jun 30 04:50:52 PM PDT 24
Peak memory 210824 kb
Host smart-25d1f79a-9a41-4f82-97e1-a43afd1fb25a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285514292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr
l_mem_walk.2285514292
Directory /workspace/40.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/40.sram_ctrl_multiple_keys.1710073359
Short name T604
Test name
Test status
Simulation time 5645798756 ps
CPU time 129.76 seconds
Started Jun 30 04:45:27 PM PDT 24
Finished Jun 30 04:47:38 PM PDT 24
Peak memory 347800 kb
Host smart-61016a21-60f4-4f12-9018-ebdc4ce620de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710073359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi
ple_keys.1710073359
Directory /workspace/40.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access.2468066967
Short name T573
Test name
Test status
Simulation time 3315348596 ps
CPU time 86.42 seconds
Started Jun 30 04:45:28 PM PDT 24
Finished Jun 30 04:46:55 PM PDT 24
Peak memory 326428 kb
Host smart-59f1858a-8580-4919-ad6b-7d5249c300f9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468066967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
sram_ctrl_partial_access.2468066967
Directory /workspace/40.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.3371689659
Short name T357
Test name
Test status
Simulation time 92675312311 ps
CPU time 558.78 seconds
Started Jun 30 04:45:27 PM PDT 24
Finished Jun 30 04:54:46 PM PDT 24
Peak memory 202760 kb
Host smart-44b94c3b-b3bd-4186-a592-653ed7da07cf
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371689659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 40.sram_ctrl_partial_access_b2b.3371689659
Directory /workspace/40.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/40.sram_ctrl_ram_cfg.3798467885
Short name T386
Test name
Test status
Simulation time 1473095256 ps
CPU time 3.93 seconds
Started Jun 30 04:45:35 PM PDT 24
Finished Jun 30 04:45:39 PM PDT 24
Peak memory 202704 kb
Host smart-66b19974-9bee-4af7-91e4-45f5c8a38187
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798467885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.3798467885
Directory /workspace/40.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/40.sram_ctrl_regwen.3726680133
Short name T250
Test name
Test status
Simulation time 30703294860 ps
CPU time 987.91 seconds
Started Jun 30 04:45:29 PM PDT 24
Finished Jun 30 05:01:58 PM PDT 24
Peak memory 380684 kb
Host smart-bec0ac36-3565-4de6-8a71-5dde7bb5a166
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726680133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.3726680133
Directory /workspace/40.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/40.sram_ctrl_smoke.1777136454
Short name T342
Test name
Test status
Simulation time 1247915031 ps
CPU time 74.34 seconds
Started Jun 30 04:45:32 PM PDT 24
Finished Jun 30 04:46:47 PM PDT 24
Peak memory 337628 kb
Host smart-8c23d630-354c-4016-86f8-431fd6e9fb31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777136454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.1777136454
Directory /workspace/40.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all.4084420502
Short name T389
Test name
Test status
Simulation time 312015239221 ps
CPU time 2753.19 seconds
Started Jun 30 04:45:37 PM PDT 24
Finished Jun 30 05:31:31 PM PDT 24
Peak memory 205168 kb
Host smart-0fb67b22-b782-4901-986b-ad208a15bfac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084420502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 40.sram_ctrl_stress_all.4084420502
Directory /workspace/40.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.3312329960
Short name T66
Test name
Test status
Simulation time 1314068148 ps
CPU time 35.05 seconds
Started Jun 30 04:45:39 PM PDT 24
Finished Jun 30 04:46:15 PM PDT 24
Peak memory 210996 kb
Host smart-ceef5bfc-006c-4e54-b6e2-61c7471888dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3312329960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.3312329960
Directory /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_pipeline.2708532769
Short name T344
Test name
Test status
Simulation time 3886297370 ps
CPU time 208.36 seconds
Started Jun 30 04:45:29 PM PDT 24
Finished Jun 30 04:48:58 PM PDT 24
Peak memory 202708 kb
Host smart-e94375b5-726f-4329-a724-4180672860ff
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708532769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_stress_pipeline.2708532769
Directory /workspace/40.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.643856859
Short name T265
Test name
Test status
Simulation time 3259075246 ps
CPU time 158 seconds
Started Jun 30 04:45:27 PM PDT 24
Finished Jun 30 04:48:06 PM PDT 24
Peak memory 372452 kb
Host smart-60d2d456-3adb-4437-9502-d6ab4d506ed5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643856859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.sram_ctrl_throughput_w_partial_write.643856859
Directory /workspace/40.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/41.sram_ctrl_access_during_key_req.2978600194
Short name T379
Test name
Test status
Simulation time 13669414148 ps
CPU time 1283.68 seconds
Started Jun 30 04:45:33 PM PDT 24
Finished Jun 30 05:06:58 PM PDT 24
Peak memory 378704 kb
Host smart-5db596b4-991c-4a3b-8f6f-811f2749486a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978600194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.sram_ctrl_access_during_key_req.2978600194
Directory /workspace/41.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/41.sram_ctrl_alert_test.1447931015
Short name T860
Test name
Test status
Simulation time 161825883 ps
CPU time 0.69 seconds
Started Jun 30 04:45:44 PM PDT 24
Finished Jun 30 04:45:45 PM PDT 24
Peak memory 202316 kb
Host smart-93c04c10-d0d5-41c2-8f85-4ebafcc06bd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447931015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.sram_ctrl_alert_test.1447931015
Directory /workspace/41.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sram_ctrl_bijection.3657530629
Short name T400
Test name
Test status
Simulation time 115370389380 ps
CPU time 1251.52 seconds
Started Jun 30 04:45:33 PM PDT 24
Finished Jun 30 05:06:26 PM PDT 24
Peak memory 203460 kb
Host smart-9c5fe4ec-2f10-4a82-8700-e2cf94dba5bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657530629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection
.3657530629
Directory /workspace/41.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/41.sram_ctrl_executable.2296018180
Short name T632
Test name
Test status
Simulation time 38806961128 ps
CPU time 820.62 seconds
Started Jun 30 04:45:34 PM PDT 24
Finished Jun 30 04:59:16 PM PDT 24
Peak memory 379672 kb
Host smart-74da773c-e63a-407b-8be4-c5e30fda7758
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296018180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executab
le.2296018180
Directory /workspace/41.sram_ctrl_executable/latest

Test location /workspace/coverage/default/41.sram_ctrl_lc_escalation.2766971920
Short name T589
Test name
Test status
Simulation time 121968895411 ps
CPU time 76.2 seconds
Started Jun 30 04:45:35 PM PDT 24
Finished Jun 30 04:46:52 PM PDT 24
Peak memory 202800 kb
Host smart-545912bd-93af-4f4e-9f0d-f1d5b0198458
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766971920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es
calation.2766971920
Directory /workspace/41.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/41.sram_ctrl_max_throughput.1611288887
Short name T173
Test name
Test status
Simulation time 768063341 ps
CPU time 102.92 seconds
Started Jun 30 04:45:36 PM PDT 24
Finished Jun 30 04:47:19 PM PDT 24
Peak memory 344744 kb
Host smart-cb17634e-654b-4db3-aa28-054b89f67864
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611288887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.sram_ctrl_max_throughput.1611288887
Directory /workspace/41.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_partial_access.587388952
Short name T458
Test name
Test status
Simulation time 18265124150 ps
CPU time 150.48 seconds
Started Jun 30 04:45:39 PM PDT 24
Finished Jun 30 04:48:10 PM PDT 24
Peak memory 210936 kb
Host smart-1fab9af3-817f-4a72-9bd6-cde5ddbc5b07
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587388952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.sram_ctrl_mem_partial_access.587388952
Directory /workspace/41.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_walk.941154031
Short name T279
Test name
Test status
Simulation time 3947120903 ps
CPU time 252.76 seconds
Started Jun 30 04:45:34 PM PDT 24
Finished Jun 30 04:49:47 PM PDT 24
Peak memory 210880 kb
Host smart-8c9f8424-a60a-4646-9273-d075416e17bb
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941154031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl
_mem_walk.941154031
Directory /workspace/41.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/41.sram_ctrl_multiple_keys.3818884403
Short name T567
Test name
Test status
Simulation time 121008805336 ps
CPU time 679.58 seconds
Started Jun 30 04:45:34 PM PDT 24
Finished Jun 30 04:56:54 PM PDT 24
Peak memory 339844 kb
Host smart-315ae834-c69b-4142-a1dd-5566ef6c8f2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818884403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi
ple_keys.3818884403
Directory /workspace/41.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access.3306768016
Short name T306
Test name
Test status
Simulation time 1115388930 ps
CPU time 103.01 seconds
Started Jun 30 04:45:36 PM PDT 24
Finished Jun 30 04:47:19 PM PDT 24
Peak memory 370268 kb
Host smart-b82fdddc-e756-424b-b0ee-0c692035e792
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306768016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
sram_ctrl_partial_access.3306768016
Directory /workspace/41.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.3273673131
Short name T913
Test name
Test status
Simulation time 135126754330 ps
CPU time 278.45 seconds
Started Jun 30 04:45:35 PM PDT 24
Finished Jun 30 04:50:14 PM PDT 24
Peak memory 202740 kb
Host smart-2edd1d14-e6c5-450e-9df7-1a4ba8f0dd38
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273673131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 41.sram_ctrl_partial_access_b2b.3273673131
Directory /workspace/41.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/41.sram_ctrl_ram_cfg.988750840
Short name T602
Test name
Test status
Simulation time 359049935 ps
CPU time 3.61 seconds
Started Jun 30 04:45:33 PM PDT 24
Finished Jun 30 04:45:37 PM PDT 24
Peak memory 202724 kb
Host smart-1dfa6b3d-eb9e-43d0-ab91-234c03101878
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988750840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.988750840
Directory /workspace/41.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/41.sram_ctrl_regwen.637066323
Short name T627
Test name
Test status
Simulation time 60907512223 ps
CPU time 891.21 seconds
Started Jun 30 04:45:34 PM PDT 24
Finished Jun 30 05:00:26 PM PDT 24
Peak memory 372592 kb
Host smart-da711075-9088-4b0b-985d-8f2f58528bb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637066323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.637066323
Directory /workspace/41.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/41.sram_ctrl_smoke.1661796440
Short name T431
Test name
Test status
Simulation time 2021868970 ps
CPU time 15.26 seconds
Started Jun 30 04:45:35 PM PDT 24
Finished Jun 30 04:45:51 PM PDT 24
Peak memory 202660 kb
Host smart-ab4d23d0-b8fc-4ce9-b5f5-d1cdba609226
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661796440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.1661796440
Directory /workspace/41.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all.1790919512
Short name T531
Test name
Test status
Simulation time 51756009410 ps
CPU time 3634.73 seconds
Started Jun 30 04:45:39 PM PDT 24
Finished Jun 30 05:46:14 PM PDT 24
Peak memory 378208 kb
Host smart-d57a4994-5abc-43f8-80e2-1a660baf4440
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790919512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 41.sram_ctrl_stress_all.1790919512
Directory /workspace/41.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.469644244
Short name T778
Test name
Test status
Simulation time 361822807 ps
CPU time 11.3 seconds
Started Jun 30 04:45:35 PM PDT 24
Finished Jun 30 04:45:47 PM PDT 24
Peak memory 211060 kb
Host smart-3089492b-ab66-4750-8c59-4b0fb9b8fa0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=469644244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.469644244
Directory /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_pipeline.3152746674
Short name T869
Test name
Test status
Simulation time 16008236763 ps
CPU time 249.23 seconds
Started Jun 30 04:45:34 PM PDT 24
Finished Jun 30 04:49:44 PM PDT 24
Peak memory 202740 kb
Host smart-b6bdd78f-bebd-4a80-9e84-f046c69f1bcf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152746674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_stress_pipeline.3152746674
Directory /workspace/41.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.794190623
Short name T432
Test name
Test status
Simulation time 4580318639 ps
CPU time 123.96 seconds
Started Jun 30 04:45:33 PM PDT 24
Finished Jun 30 04:47:38 PM PDT 24
Peak memory 368312 kb
Host smart-e2b11913-49ab-4327-a91f-17ce33132d80
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794190623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.sram_ctrl_throughput_w_partial_write.794190623
Directory /workspace/41.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/42.sram_ctrl_access_during_key_req.3658578462
Short name T594
Test name
Test status
Simulation time 12270368227 ps
CPU time 817.16 seconds
Started Jun 30 04:45:42 PM PDT 24
Finished Jun 30 04:59:20 PM PDT 24
Peak memory 373712 kb
Host smart-91477c95-44af-4227-8bd1-c18f87597d9f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658578462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.sram_ctrl_access_during_key_req.3658578462
Directory /workspace/42.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/42.sram_ctrl_alert_test.3798303306
Short name T745
Test name
Test status
Simulation time 27182260 ps
CPU time 0.68 seconds
Started Jun 30 04:45:44 PM PDT 24
Finished Jun 30 04:45:45 PM PDT 24
Peak memory 202280 kb
Host smart-63ac2a48-945a-4968-b294-08f43c2980a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798303306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.sram_ctrl_alert_test.3798303306
Directory /workspace/42.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sram_ctrl_bijection.3534866166
Short name T1
Test name
Test status
Simulation time 13866537866 ps
CPU time 970.99 seconds
Started Jun 30 04:45:42 PM PDT 24
Finished Jun 30 05:01:53 PM PDT 24
Peak memory 203504 kb
Host smart-ec0c166f-963b-496e-ac08-1c8957484146
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534866166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection
.3534866166
Directory /workspace/42.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/42.sram_ctrl_executable.905688153
Short name T300
Test name
Test status
Simulation time 6475210549 ps
CPU time 577.19 seconds
Started Jun 30 04:45:41 PM PDT 24
Finished Jun 30 04:55:19 PM PDT 24
Peak memory 363284 kb
Host smart-e4f2ccd0-921a-4575-b7d9-614bac7f76f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905688153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executabl
e.905688153
Directory /workspace/42.sram_ctrl_executable/latest

Test location /workspace/coverage/default/42.sram_ctrl_lc_escalation.3186019114
Short name T850
Test name
Test status
Simulation time 13623653649 ps
CPU time 37.83 seconds
Started Jun 30 04:45:41 PM PDT 24
Finished Jun 30 04:46:19 PM PDT 24
Peak memory 210964 kb
Host smart-70d0d0d4-ef82-46ae-918e-341939b0be58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186019114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_es
calation.3186019114
Directory /workspace/42.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/42.sram_ctrl_max_throughput.3159535613
Short name T569
Test name
Test status
Simulation time 4195847627 ps
CPU time 29.52 seconds
Started Jun 30 04:45:41 PM PDT 24
Finished Jun 30 04:46:11 PM PDT 24
Peak memory 284572 kb
Host smart-b4561103-9b54-439c-956d-1a571c2146c0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159535613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.sram_ctrl_max_throughput.3159535613
Directory /workspace/42.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_partial_access.1426350836
Short name T646
Test name
Test status
Simulation time 5626179521 ps
CPU time 81.21 seconds
Started Jun 30 04:45:42 PM PDT 24
Finished Jun 30 04:47:03 PM PDT 24
Peak memory 210944 kb
Host smart-25b1e783-7c8e-4ba0-a5c3-1cabfc68c6d4
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426350836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_mem_partial_access.1426350836
Directory /workspace/42.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_walk.1590624877
Short name T466
Test name
Test status
Simulation time 78043301080 ps
CPU time 330.56 seconds
Started Jun 30 04:45:41 PM PDT 24
Finished Jun 30 04:51:12 PM PDT 24
Peak memory 210888 kb
Host smart-199004a6-86f9-4edc-b209-bb17a25e007a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590624877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr
l_mem_walk.1590624877
Directory /workspace/42.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/42.sram_ctrl_multiple_keys.749984508
Short name T920
Test name
Test status
Simulation time 9041431198 ps
CPU time 939.27 seconds
Started Jun 30 04:45:42 PM PDT 24
Finished Jun 30 05:01:22 PM PDT 24
Peak memory 378596 kb
Host smart-1bf93364-1003-4e80-baa7-811de5e6c5ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749984508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multip
le_keys.749984508
Directory /workspace/42.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access.3935520723
Short name T670
Test name
Test status
Simulation time 1785905372 ps
CPU time 5.04 seconds
Started Jun 30 04:45:44 PM PDT 24
Finished Jun 30 04:45:50 PM PDT 24
Peak memory 202600 kb
Host smart-52476800-947c-4962-a4f9-8f6c2a7ec038
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935520723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
sram_ctrl_partial_access.3935520723
Directory /workspace/42.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1480506982
Short name T136
Test name
Test status
Simulation time 9275187543 ps
CPU time 187.59 seconds
Started Jun 30 04:45:43 PM PDT 24
Finished Jun 30 04:48:51 PM PDT 24
Peak memory 202744 kb
Host smart-9ceedf7e-8f83-4ebd-b655-2a8dbed7c679
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480506982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 42.sram_ctrl_partial_access_b2b.1480506982
Directory /workspace/42.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/42.sram_ctrl_ram_cfg.2292600871
Short name T203
Test name
Test status
Simulation time 1991480534 ps
CPU time 4.04 seconds
Started Jun 30 04:45:44 PM PDT 24
Finished Jun 30 04:45:48 PM PDT 24
Peak memory 202720 kb
Host smart-f37365d8-7d49-4879-bd17-587b690fac6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292600871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.2292600871
Directory /workspace/42.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/42.sram_ctrl_regwen.1556718452
Short name T353
Test name
Test status
Simulation time 4603597833 ps
CPU time 370.14 seconds
Started Jun 30 04:45:41 PM PDT 24
Finished Jun 30 04:51:51 PM PDT 24
Peak memory 372112 kb
Host smart-9d7bb932-baf5-4b74-b6d2-ed9315bf67f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556718452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.1556718452
Directory /workspace/42.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/42.sram_ctrl_smoke.990222460
Short name T499
Test name
Test status
Simulation time 756352718 ps
CPU time 10.22 seconds
Started Jun 30 04:45:43 PM PDT 24
Finished Jun 30 04:45:54 PM PDT 24
Peak memory 202644 kb
Host smart-b825b24c-8f8a-4d0a-8ffa-3319f63a2b51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990222460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.990222460
Directory /workspace/42.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all.1597300415
Short name T826
Test name
Test status
Simulation time 499360487325 ps
CPU time 4072.82 seconds
Started Jun 30 04:45:41 PM PDT 24
Finished Jun 30 05:53:35 PM PDT 24
Peak memory 381664 kb
Host smart-c9e000ff-bfe0-439e-abc4-d3240f4d804b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597300415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 42.sram_ctrl_stress_all.1597300415
Directory /workspace/42.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.825465558
Short name T751
Test name
Test status
Simulation time 6160966800 ps
CPU time 181.53 seconds
Started Jun 30 04:45:44 PM PDT 24
Finished Jun 30 04:48:46 PM PDT 24
Peak memory 376900 kb
Host smart-3c739130-110e-4f28-b14a-b5f6e43395dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=825465558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.825465558
Directory /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_pipeline.1360186715
Short name T915
Test name
Test status
Simulation time 46362706949 ps
CPU time 286.57 seconds
Started Jun 30 04:45:43 PM PDT 24
Finished Jun 30 04:50:30 PM PDT 24
Peak memory 202744 kb
Host smart-e8a25863-b378-4432-a254-e998b56434c5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360186715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_stress_pipeline.1360186715
Directory /workspace/42.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1201174259
Short name T439
Test name
Test status
Simulation time 810104770 ps
CPU time 87.79 seconds
Started Jun 30 04:45:43 PM PDT 24
Finished Jun 30 04:47:12 PM PDT 24
Peak memory 341648 kb
Host smart-7409d6fb-666e-40ce-8a17-b348cb1944ae
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201174259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.1201174259
Directory /workspace/42.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/43.sram_ctrl_access_during_key_req.1640775771
Short name T739
Test name
Test status
Simulation time 15162248353 ps
CPU time 1119.91 seconds
Started Jun 30 04:45:51 PM PDT 24
Finished Jun 30 05:04:31 PM PDT 24
Peak memory 376588 kb
Host smart-1b463032-1ef8-46c0-ae4f-a3fe32697c6c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640775771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.sram_ctrl_access_during_key_req.1640775771
Directory /workspace/43.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/43.sram_ctrl_alert_test.4006777024
Short name T702
Test name
Test status
Simulation time 38406844 ps
CPU time 0.66 seconds
Started Jun 30 04:45:52 PM PDT 24
Finished Jun 30 04:45:53 PM PDT 24
Peak memory 202288 kb
Host smart-c5c21be1-653b-4616-a05d-13cfc585fe68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006777024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.sram_ctrl_alert_test.4006777024
Directory /workspace/43.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sram_ctrl_executable.495668647
Short name T535
Test name
Test status
Simulation time 21453540593 ps
CPU time 684.51 seconds
Started Jun 30 04:45:52 PM PDT 24
Finished Jun 30 04:57:17 PM PDT 24
Peak memory 376532 kb
Host smart-700bfe40-e610-4a5b-af22-410a8acdb8c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495668647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executabl
e.495668647
Directory /workspace/43.sram_ctrl_executable/latest

Test location /workspace/coverage/default/43.sram_ctrl_lc_escalation.1155156986
Short name T159
Test name
Test status
Simulation time 6865677952 ps
CPU time 44.75 seconds
Started Jun 30 04:45:41 PM PDT 24
Finished Jun 30 04:46:26 PM PDT 24
Peak memory 210912 kb
Host smart-f654e3d4-6a5b-49c2-9836-1bb0209df25e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155156986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_es
calation.1155156986
Directory /workspace/43.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/43.sram_ctrl_max_throughput.2934763004
Short name T864
Test name
Test status
Simulation time 781659646 ps
CPU time 68.47 seconds
Started Jun 30 04:45:43 PM PDT 24
Finished Jun 30 04:46:52 PM PDT 24
Peak memory 317144 kb
Host smart-4e85d2e2-a024-4946-a2d0-c513c5689951
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934763004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.sram_ctrl_max_throughput.2934763004
Directory /workspace/43.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_partial_access.193508153
Short name T879
Test name
Test status
Simulation time 19085143529 ps
CPU time 163.86 seconds
Started Jun 30 04:45:50 PM PDT 24
Finished Jun 30 04:48:34 PM PDT 24
Peak memory 210932 kb
Host smart-5b06c837-93fe-4092-a666-116772d02128
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193508153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.sram_ctrl_mem_partial_access.193508153
Directory /workspace/43.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_walk.3346181470
Short name T917
Test name
Test status
Simulation time 3982561420 ps
CPU time 256.45 seconds
Started Jun 30 04:45:52 PM PDT 24
Finished Jun 30 04:50:09 PM PDT 24
Peak memory 210900 kb
Host smart-102c258c-fc85-40dd-babc-3e3b42813a28
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346181470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr
l_mem_walk.3346181470
Directory /workspace/43.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/43.sram_ctrl_multiple_keys.3800895943
Short name T62
Test name
Test status
Simulation time 18931565914 ps
CPU time 1158.08 seconds
Started Jun 30 04:45:42 PM PDT 24
Finished Jun 30 05:05:00 PM PDT 24
Peak memory 365360 kb
Host smart-84c1f724-4847-4fbb-bed2-4e6686dbe89c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800895943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multi
ple_keys.3800895943
Directory /workspace/43.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access.1491184019
Short name T452
Test name
Test status
Simulation time 4374341862 ps
CPU time 45.13 seconds
Started Jun 30 04:45:44 PM PDT 24
Finished Jun 30 04:46:30 PM PDT 24
Peak memory 294692 kb
Host smart-f122eb0b-22ac-49ab-ac59-947babf3fb40
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491184019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
sram_ctrl_partial_access.1491184019
Directory /workspace/43.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3189160560
Short name T180
Test name
Test status
Simulation time 5503654008 ps
CPU time 348.21 seconds
Started Jun 30 04:45:43 PM PDT 24
Finished Jun 30 04:51:32 PM PDT 24
Peak memory 202796 kb
Host smart-22de8008-a7ea-4930-902b-1ca3bf52abdc
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189160560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 43.sram_ctrl_partial_access_b2b.3189160560
Directory /workspace/43.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/43.sram_ctrl_ram_cfg.3373582047
Short name T815
Test name
Test status
Simulation time 2234568330 ps
CPU time 3.32 seconds
Started Jun 30 04:45:51 PM PDT 24
Finished Jun 30 04:45:55 PM PDT 24
Peak memory 202772 kb
Host smart-09996779-f25a-4021-be43-c675e4abe1f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373582047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.3373582047
Directory /workspace/43.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/43.sram_ctrl_regwen.1933773711
Short name T905
Test name
Test status
Simulation time 48205544917 ps
CPU time 660.07 seconds
Started Jun 30 04:45:51 PM PDT 24
Finished Jun 30 04:56:51 PM PDT 24
Peak memory 366328 kb
Host smart-bc54074a-c2c7-4555-ac7c-7dda678565b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933773711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.1933773711
Directory /workspace/43.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/43.sram_ctrl_smoke.2430910719
Short name T652
Test name
Test status
Simulation time 852905232 ps
CPU time 61.34 seconds
Started Jun 30 04:45:43 PM PDT 24
Finished Jun 30 04:46:44 PM PDT 24
Peak memory 306844 kb
Host smart-335463a8-7e35-409f-81ed-f8d348d79794
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430910719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.2430910719
Directory /workspace/43.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_all.8193756
Short name T338
Test name
Test status
Simulation time 40154440159 ps
CPU time 1135.04 seconds
Started Jun 30 04:45:51 PM PDT 24
Finished Jun 30 05:04:47 PM PDT 24
Peak memory 385696 kb
Host smart-0c630b30-c65d-41da-8b33-f9890130fa7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8193756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.sram_ctrl_stress_all.8193756
Directory /workspace/43.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2848847310
Short name T114
Test name
Test status
Simulation time 1900615906 ps
CPU time 38.42 seconds
Started Jun 30 04:45:52 PM PDT 24
Finished Jun 30 04:46:31 PM PDT 24
Peak memory 255376 kb
Host smart-a01e16b8-6103-4889-873b-dea2d5414e83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2848847310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.2848847310
Directory /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_pipeline.1042508809
Short name T940
Test name
Test status
Simulation time 3855924902 ps
CPU time 247.07 seconds
Started Jun 30 04:45:42 PM PDT 24
Finished Jun 30 04:49:50 PM PDT 24
Peak memory 202748 kb
Host smart-121a0d60-213a-4e04-a898-eef113523dd5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042508809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_stress_pipeline.1042508809
Directory /workspace/43.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.15709672
Short name T422
Test name
Test status
Simulation time 1071812389 ps
CPU time 10.83 seconds
Started Jun 30 04:45:44 PM PDT 24
Finished Jun 30 04:45:55 PM PDT 24
Peak memory 226108 kb
Host smart-f5083ac2-de15-4971-a901-2c63d97e40d5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15709672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.sram_ctrl_throughput_w_partial_write.15709672
Directory /workspace/43.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/44.sram_ctrl_access_during_key_req.2228833658
Short name T883
Test name
Test status
Simulation time 5438130709 ps
CPU time 281.03 seconds
Started Jun 30 04:45:51 PM PDT 24
Finished Jun 30 04:50:34 PM PDT 24
Peak memory 332580 kb
Host smart-69704972-7e5b-4c67-a0f1-7c1c2b879562
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228833658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.sram_ctrl_access_during_key_req.2228833658
Directory /workspace/44.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/44.sram_ctrl_alert_test.1302235256
Short name T511
Test name
Test status
Simulation time 16358070 ps
CPU time 0.73 seconds
Started Jun 30 04:46:03 PM PDT 24
Finished Jun 30 04:46:04 PM PDT 24
Peak memory 202268 kb
Host smart-651a8137-5743-4c32-a716-af69b94a6e0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302235256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.sram_ctrl_alert_test.1302235256
Directory /workspace/44.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sram_ctrl_bijection.2465792708
Short name T555
Test name
Test status
Simulation time 275889446965 ps
CPU time 2376.81 seconds
Started Jun 30 04:45:49 PM PDT 24
Finished Jun 30 05:25:26 PM PDT 24
Peak memory 203384 kb
Host smart-7540b5cf-a312-44e5-ae86-f2051583a621
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465792708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection
.2465792708
Directory /workspace/44.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/44.sram_ctrl_executable.390564439
Short name T290
Test name
Test status
Simulation time 63357526211 ps
CPU time 514.87 seconds
Started Jun 30 04:45:51 PM PDT 24
Finished Jun 30 04:54:26 PM PDT 24
Peak memory 372436 kb
Host smart-38154210-03b2-4c0b-9494-150374c3d291
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390564439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executabl
e.390564439
Directory /workspace/44.sram_ctrl_executable/latest

Test location /workspace/coverage/default/44.sram_ctrl_lc_escalation.1600940422
Short name T699
Test name
Test status
Simulation time 6167195241 ps
CPU time 40.53 seconds
Started Jun 30 04:45:52 PM PDT 24
Finished Jun 30 04:46:33 PM PDT 24
Peak memory 202712 kb
Host smart-3b11631d-60c4-4473-a7fd-e2b1c67c26b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600940422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es
calation.1600940422
Directory /workspace/44.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/44.sram_ctrl_max_throughput.609368305
Short name T200
Test name
Test status
Simulation time 718731301 ps
CPU time 13.78 seconds
Started Jun 30 04:45:52 PM PDT 24
Finished Jun 30 04:46:06 PM PDT 24
Peak memory 244300 kb
Host smart-38c94aa6-05ba-44d4-8136-35f4dc16683d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609368305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.sram_ctrl_max_throughput.609368305
Directory /workspace/44.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_partial_access.78253368
Short name T669
Test name
Test status
Simulation time 4023345632 ps
CPU time 69.76 seconds
Started Jun 30 04:46:00 PM PDT 24
Finished Jun 30 04:47:11 PM PDT 24
Peak memory 211020 kb
Host smart-53be3f7b-48a0-469f-842c-fb5caaff57d8
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78253368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
sram_ctrl_mem_partial_access.78253368
Directory /workspace/44.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_walk.2008369925
Short name T901
Test name
Test status
Simulation time 35891896666 ps
CPU time 183.05 seconds
Started Jun 30 04:46:00 PM PDT 24
Finished Jun 30 04:49:04 PM PDT 24
Peak memory 203896 kb
Host smart-415dfae0-7ad8-4492-95d4-86fe763dcc46
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008369925 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr
l_mem_walk.2008369925
Directory /workspace/44.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/44.sram_ctrl_multiple_keys.4271452197
Short name T61
Test name
Test status
Simulation time 14875088403 ps
CPU time 304.15 seconds
Started Jun 30 04:45:51 PM PDT 24
Finished Jun 30 04:50:56 PM PDT 24
Peak memory 374424 kb
Host smart-f344fe4c-fd76-485d-84c3-b07ee459d896
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271452197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi
ple_keys.4271452197
Directory /workspace/44.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access.1748940151
Short name T547
Test name
Test status
Simulation time 1021810354 ps
CPU time 17.18 seconds
Started Jun 30 04:45:51 PM PDT 24
Finished Jun 30 04:46:09 PM PDT 24
Peak memory 202652 kb
Host smart-ba06e618-59e3-4a12-86bb-572d81e1f132
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748940151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
sram_ctrl_partial_access.1748940151
Directory /workspace/44.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.786899944
Short name T921
Test name
Test status
Simulation time 21962226745 ps
CPU time 514.48 seconds
Started Jun 30 04:45:50 PM PDT 24
Finished Jun 30 04:54:24 PM PDT 24
Peak memory 202744 kb
Host smart-c41a003a-92c9-4f19-b8d3-5dced33a3b79
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786899944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.sram_ctrl_partial_access_b2b.786899944
Directory /workspace/44.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/44.sram_ctrl_ram_cfg.3098630390
Short name T427
Test name
Test status
Simulation time 1434765838 ps
CPU time 3.7 seconds
Started Jun 30 04:45:59 PM PDT 24
Finished Jun 30 04:46:03 PM PDT 24
Peak memory 202744 kb
Host smart-fd417234-7911-4180-883c-59cc6768918b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098630390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.3098630390
Directory /workspace/44.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/44.sram_ctrl_regwen.2814455917
Short name T536
Test name
Test status
Simulation time 1282832676 ps
CPU time 122.38 seconds
Started Jun 30 04:45:53 PM PDT 24
Finished Jun 30 04:47:56 PM PDT 24
Peak memory 356008 kb
Host smart-1a32cee2-0fde-4236-ad88-96969eb75a18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814455917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.2814455917
Directory /workspace/44.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/44.sram_ctrl_smoke.1274434465
Short name T305
Test name
Test status
Simulation time 2095985810 ps
CPU time 57.62 seconds
Started Jun 30 04:45:53 PM PDT 24
Finished Jun 30 04:46:51 PM PDT 24
Peak memory 296964 kb
Host smart-5635878e-5ff7-41de-b3ee-787b7e43923e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274434465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.1274434465
Directory /workspace/44.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all.4057772165
Short name T578
Test name
Test status
Simulation time 494247017113 ps
CPU time 3023.38 seconds
Started Jun 30 04:45:59 PM PDT 24
Finished Jun 30 05:36:24 PM PDT 24
Peak memory 377580 kb
Host smart-c40fed18-72ee-42f8-b94f-df36361e5140
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057772165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.sram_ctrl_stress_all.4057772165
Directory /workspace/44.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_pipeline.3242226229
Short name T288
Test name
Test status
Simulation time 2392457207 ps
CPU time 132.59 seconds
Started Jun 30 04:45:50 PM PDT 24
Finished Jun 30 04:48:03 PM PDT 24
Peak memory 202652 kb
Host smart-9db2fd3d-9832-44ff-b22c-62ac8865b952
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242226229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_stress_pipeline.3242226229
Directory /workspace/44.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3142821949
Short name T918
Test name
Test status
Simulation time 783117704 ps
CPU time 71.91 seconds
Started Jun 30 04:45:51 PM PDT 24
Finished Jun 30 04:47:04 PM PDT 24
Peak memory 312968 kb
Host smart-b562d6f1-6e3e-4714-a101-23dc24cbac9a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142821949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.3142821949
Directory /workspace/44.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/45.sram_ctrl_access_during_key_req.370709406
Short name T46
Test name
Test status
Simulation time 43867417578 ps
CPU time 873.52 seconds
Started Jun 30 04:46:00 PM PDT 24
Finished Jun 30 05:00:34 PM PDT 24
Peak memory 377588 kb
Host smart-c8adf363-436f-4cfc-a279-8881f5dba598
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370709406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 45.sram_ctrl_access_during_key_req.370709406
Directory /workspace/45.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/45.sram_ctrl_alert_test.1220679748
Short name T417
Test name
Test status
Simulation time 57265222 ps
CPU time 0.68 seconds
Started Jun 30 04:45:59 PM PDT 24
Finished Jun 30 04:46:00 PM PDT 24
Peak memory 202264 kb
Host smart-8bc63e22-b635-485b-b9c4-360d67a4a750
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220679748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.sram_ctrl_alert_test.1220679748
Directory /workspace/45.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sram_ctrl_bijection.2761637689
Short name T489
Test name
Test status
Simulation time 66278941538 ps
CPU time 2150.36 seconds
Started Jun 30 04:45:58 PM PDT 24
Finished Jun 30 05:21:48 PM PDT 24
Peak memory 203328 kb
Host smart-cf00d24d-f079-4122-b262-792797186352
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761637689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection
.2761637689
Directory /workspace/45.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/45.sram_ctrl_executable.3262804769
Short name T515
Test name
Test status
Simulation time 29978881803 ps
CPU time 339.93 seconds
Started Jun 30 04:46:00 PM PDT 24
Finished Jun 30 04:51:41 PM PDT 24
Peak memory 342128 kb
Host smart-e8988d3d-6383-4129-9e41-08215867a515
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262804769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab
le.3262804769
Directory /workspace/45.sram_ctrl_executable/latest

Test location /workspace/coverage/default/45.sram_ctrl_lc_escalation.1207274369
Short name T7
Test name
Test status
Simulation time 34445676440 ps
CPU time 59.23 seconds
Started Jun 30 04:45:57 PM PDT 24
Finished Jun 30 04:46:57 PM PDT 24
Peak memory 202812 kb
Host smart-5200a467-9835-4de2-a21c-6bb0802e664a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207274369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_es
calation.1207274369
Directory /workspace/45.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/45.sram_ctrl_max_throughput.1549064623
Short name T845
Test name
Test status
Simulation time 5228333201 ps
CPU time 51.93 seconds
Started Jun 30 04:46:01 PM PDT 24
Finished Jun 30 04:46:53 PM PDT 24
Peak memory 314128 kb
Host smart-c558946c-fd00-4130-b563-62fb035e8f7c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549064623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.sram_ctrl_max_throughput.1549064623
Directory /workspace/45.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_partial_access.401992425
Short name T38
Test name
Test status
Simulation time 1593550062 ps
CPU time 124.55 seconds
Started Jun 30 04:46:03 PM PDT 24
Finished Jun 30 04:48:08 PM PDT 24
Peak memory 218952 kb
Host smart-d67d99ac-2f71-4b10-bcf8-bfb562e61652
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401992425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.sram_ctrl_mem_partial_access.401992425
Directory /workspace/45.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_walk.3846857240
Short name T689
Test name
Test status
Simulation time 10519034385 ps
CPU time 156.47 seconds
Started Jun 30 04:45:59 PM PDT 24
Finished Jun 30 04:48:36 PM PDT 24
Peak memory 210844 kb
Host smart-d99e9c37-5ce8-4495-8fd4-5c1bd4b9ab36
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846857240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctr
l_mem_walk.3846857240
Directory /workspace/45.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/45.sram_ctrl_multiple_keys.2162103434
Short name T732
Test name
Test status
Simulation time 7770308471 ps
CPU time 1138.97 seconds
Started Jun 30 04:46:00 PM PDT 24
Finished Jun 30 05:05:00 PM PDT 24
Peak memory 369424 kb
Host smart-de40845c-9381-4ebd-9024-ce7fe97a61ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162103434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multi
ple_keys.2162103434
Directory /workspace/45.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access.3649725733
Short name T898
Test name
Test status
Simulation time 2623675388 ps
CPU time 7.24 seconds
Started Jun 30 04:45:59 PM PDT 24
Finished Jun 30 04:46:07 PM PDT 24
Peak memory 202568 kb
Host smart-aea2e5a7-3eaf-4edc-b8e9-25c349a98038
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649725733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
sram_ctrl_partial_access.3649725733
Directory /workspace/45.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.327396628
Short name T611
Test name
Test status
Simulation time 10787461940 ps
CPU time 309.52 seconds
Started Jun 30 04:45:59 PM PDT 24
Finished Jun 30 04:51:08 PM PDT 24
Peak memory 202716 kb
Host smart-3c769d99-a0b4-402a-aac0-17b64a03bdce
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327396628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.sram_ctrl_partial_access_b2b.327396628
Directory /workspace/45.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/45.sram_ctrl_ram_cfg.315342199
Short name T293
Test name
Test status
Simulation time 463413541 ps
CPU time 3.07 seconds
Started Jun 30 04:45:58 PM PDT 24
Finished Jun 30 04:46:02 PM PDT 24
Peak memory 202732 kb
Host smart-d20d112e-d4c2-4d3b-8503-652fbd0e005a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315342199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.315342199
Directory /workspace/45.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/45.sram_ctrl_regwen.525601250
Short name T334
Test name
Test status
Simulation time 39517384621 ps
CPU time 1911.69 seconds
Started Jun 30 04:46:00 PM PDT 24
Finished Jun 30 05:17:52 PM PDT 24
Peak memory 379012 kb
Host smart-eab14aaf-487d-4c88-9c26-4e335948caa6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525601250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.525601250
Directory /workspace/45.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/45.sram_ctrl_smoke.2421675291
Short name T232
Test name
Test status
Simulation time 5425527586 ps
CPU time 78.52 seconds
Started Jun 30 04:46:00 PM PDT 24
Finished Jun 30 04:47:20 PM PDT 24
Peak memory 318200 kb
Host smart-f0031731-5480-497a-8eff-6df61cbe5ac1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421675291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.2421675291
Directory /workspace/45.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all.2201564442
Short name T116
Test name
Test status
Simulation time 126305987824 ps
CPU time 4134.76 seconds
Started Jun 30 04:46:00 PM PDT 24
Finished Jun 30 05:54:56 PM PDT 24
Peak memory 381732 kb
Host smart-a39657a7-150d-4b6e-8bf0-828edc4b07f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201564442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 45.sram_ctrl_stress_all.2201564442
Directory /workspace/45.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.4127312587
Short name T893
Test name
Test status
Simulation time 1171980567 ps
CPU time 49.26 seconds
Started Jun 30 04:46:00 PM PDT 24
Finished Jun 30 04:46:50 PM PDT 24
Peak memory 211120 kb
Host smart-640db5fa-63fa-4d60-b262-b17937b3df9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4127312587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.4127312587
Directory /workspace/45.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_pipeline.1545305705
Short name T107
Test name
Test status
Simulation time 7425511193 ps
CPU time 325.19 seconds
Started Jun 30 04:46:02 PM PDT 24
Finished Jun 30 04:51:28 PM PDT 24
Peak memory 202752 kb
Host smart-72c27254-fd92-414d-979f-73fec0e9a9d7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545305705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_stress_pipeline.1545305705
Directory /workspace/45.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1432350942
Short name T643
Test name
Test status
Simulation time 771898357 ps
CPU time 103.78 seconds
Started Jun 30 04:45:59 PM PDT 24
Finished Jun 30 04:47:43 PM PDT 24
Peak memory 349788 kb
Host smart-ee1859ad-d420-4a4e-8243-9da6ed3b195f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432350942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.1432350942
Directory /workspace/45.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/46.sram_ctrl_access_during_key_req.580883721
Short name T178
Test name
Test status
Simulation time 23557627917 ps
CPU time 716.97 seconds
Started Jun 30 04:46:06 PM PDT 24
Finished Jun 30 04:58:04 PM PDT 24
Peak memory 379416 kb
Host smart-021124f0-37e4-4dd5-bdf0-9a729181e8bc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580883721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 46.sram_ctrl_access_during_key_req.580883721
Directory /workspace/46.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/46.sram_ctrl_alert_test.2292260521
Short name T862
Test name
Test status
Simulation time 13472001 ps
CPU time 0.64 seconds
Started Jun 30 04:46:04 PM PDT 24
Finished Jun 30 04:46:05 PM PDT 24
Peak memory 202292 kb
Host smart-b52813db-d203-4ad3-bc79-1dc755d5f8e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292260521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.sram_ctrl_alert_test.2292260521
Directory /workspace/46.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sram_ctrl_bijection.733508680
Short name T755
Test name
Test status
Simulation time 159554979719 ps
CPU time 1764.66 seconds
Started Jun 30 04:46:00 PM PDT 24
Finished Jun 30 05:15:26 PM PDT 24
Peak memory 203368 kb
Host smart-f6f1989b-4aa9-4ef9-b185-723dbbda22a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733508680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection.
733508680
Directory /workspace/46.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/46.sram_ctrl_executable.3152438005
Short name T309
Test name
Test status
Simulation time 2651362676 ps
CPU time 67.64 seconds
Started Jun 30 04:46:05 PM PDT 24
Finished Jun 30 04:47:13 PM PDT 24
Peak memory 284532 kb
Host smart-13c3f2c8-8864-4961-908c-6e8faae474cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152438005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab
le.3152438005
Directory /workspace/46.sram_ctrl_executable/latest

Test location /workspace/coverage/default/46.sram_ctrl_lc_escalation.2636467243
Short name T605
Test name
Test status
Simulation time 19514978269 ps
CPU time 35.17 seconds
Started Jun 30 04:45:57 PM PDT 24
Finished Jun 30 04:46:32 PM PDT 24
Peak memory 210972 kb
Host smart-885f15b2-9a2a-499f-a645-8e6b350373b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636467243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es
calation.2636467243
Directory /workspace/46.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/46.sram_ctrl_max_throughput.3782094738
Short name T811
Test name
Test status
Simulation time 697498208 ps
CPU time 14.02 seconds
Started Jun 30 04:46:01 PM PDT 24
Finished Jun 30 04:46:15 PM PDT 24
Peak memory 244588 kb
Host smart-9012f386-87b7-434b-a57c-06ce64c95b4c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782094738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.sram_ctrl_max_throughput.3782094738
Directory /workspace/46.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_partial_access.595399297
Short name T687
Test name
Test status
Simulation time 32676128862 ps
CPU time 88.44 seconds
Started Jun 30 04:46:07 PM PDT 24
Finished Jun 30 04:47:36 PM PDT 24
Peak memory 212784 kb
Host smart-ce5f45f0-ead0-42c3-bde6-0ab7661c850a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595399297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.sram_ctrl_mem_partial_access.595399297
Directory /workspace/46.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_walk.1458480266
Short name T149
Test name
Test status
Simulation time 28181987467 ps
CPU time 136.96 seconds
Started Jun 30 04:46:06 PM PDT 24
Finished Jun 30 04:48:24 PM PDT 24
Peak memory 210904 kb
Host smart-fe4aac0e-4764-4b00-a09a-660ad19f5538
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458480266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctr
l_mem_walk.1458480266
Directory /workspace/46.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/46.sram_ctrl_multiple_keys.36298534
Short name T663
Test name
Test status
Simulation time 91045772479 ps
CPU time 490.83 seconds
Started Jun 30 04:46:03 PM PDT 24
Finished Jun 30 04:54:15 PM PDT 24
Peak memory 375164 kb
Host smart-9f7561c1-c21b-4661-82c9-81601774d44d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36298534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip
le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multipl
e_keys.36298534
Directory /workspace/46.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access.3858367580
Short name T682
Test name
Test status
Simulation time 960568886 ps
CPU time 34.61 seconds
Started Jun 30 04:45:59 PM PDT 24
Finished Jun 30 04:46:34 PM PDT 24
Peak memory 275868 kb
Host smart-0f299802-40fc-4df3-9988-3f1fa9af74eb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858367580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
sram_ctrl_partial_access.3858367580
Directory /workspace/46.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2147888404
Short name T202
Test name
Test status
Simulation time 12915544573 ps
CPU time 183 seconds
Started Jun 30 04:45:57 PM PDT 24
Finished Jun 30 04:49:00 PM PDT 24
Peak memory 202736 kb
Host smart-2a8922e9-f204-4d34-819f-bb5f6928c34e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147888404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 46.sram_ctrl_partial_access_b2b.2147888404
Directory /workspace/46.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/46.sram_ctrl_ram_cfg.2414723517
Short name T647
Test name
Test status
Simulation time 1357291052 ps
CPU time 3.16 seconds
Started Jun 30 04:46:05 PM PDT 24
Finished Jun 30 04:46:09 PM PDT 24
Peak memory 202632 kb
Host smart-5ee6925d-cb4c-4a86-8a99-967bccf77689
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414723517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.2414723517
Directory /workspace/46.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/46.sram_ctrl_regwen.3767795127
Short name T660
Test name
Test status
Simulation time 3054773810 ps
CPU time 113.43 seconds
Started Jun 30 04:46:08 PM PDT 24
Finished Jun 30 04:48:01 PM PDT 24
Peak memory 312148 kb
Host smart-2dc6c1a3-67c8-44a3-87ae-1439989c0190
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767795127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.3767795127
Directory /workspace/46.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/46.sram_ctrl_smoke.3134360149
Short name T819
Test name
Test status
Simulation time 1647975709 ps
CPU time 49.79 seconds
Started Jun 30 04:46:00 PM PDT 24
Finished Jun 30 04:46:50 PM PDT 24
Peak memory 319192 kb
Host smart-4bd0db5a-9f39-477d-b205-6f6345d90063
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134360149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.3134360149
Directory /workspace/46.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all.1389616659
Short name T436
Test name
Test status
Simulation time 16942446845 ps
CPU time 1049.43 seconds
Started Jun 30 04:46:06 PM PDT 24
Finished Jun 30 05:03:36 PM PDT 24
Peak memory 353712 kb
Host smart-62d4d333-6e64-4b61-b1fe-2a07116a2d42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389616659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 46.sram_ctrl_stress_all.1389616659
Directory /workspace/46.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.106355691
Short name T54
Test name
Test status
Simulation time 1901031914 ps
CPU time 27.92 seconds
Started Jun 30 04:46:08 PM PDT 24
Finished Jun 30 04:46:36 PM PDT 24
Peak memory 210964 kb
Host smart-bef4ab44-84f7-4eff-b56c-dc07c3898629
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=106355691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.106355691
Directory /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_pipeline.4180365031
Short name T613
Test name
Test status
Simulation time 13348517271 ps
CPU time 274.96 seconds
Started Jun 30 04:45:58 PM PDT 24
Finished Jun 30 04:50:34 PM PDT 24
Peak memory 202712 kb
Host smart-d753f7d5-c31b-418a-b2c2-21eb9a37a9b9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180365031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_stress_pipeline.4180365031
Directory /workspace/46.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.81627785
Short name T185
Test name
Test status
Simulation time 2953441877 ps
CPU time 22.15 seconds
Started Jun 30 04:45:58 PM PDT 24
Finished Jun 30 04:46:21 PM PDT 24
Peak memory 260576 kb
Host smart-ab938487-83e7-4dd8-b606-c018a61a4e65
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81627785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.sram_ctrl_throughput_w_partial_write.81627785
Directory /workspace/46.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/47.sram_ctrl_access_during_key_req.712389531
Short name T596
Test name
Test status
Simulation time 34335896364 ps
CPU time 838.32 seconds
Started Jun 30 04:46:14 PM PDT 24
Finished Jun 30 05:00:13 PM PDT 24
Peak memory 378596 kb
Host smart-794202d1-b09e-415d-ae62-c5648cb38b72
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712389531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 47.sram_ctrl_access_during_key_req.712389531
Directory /workspace/47.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/47.sram_ctrl_alert_test.2774901758
Short name T648
Test name
Test status
Simulation time 14722245 ps
CPU time 0.66 seconds
Started Jun 30 04:46:13 PM PDT 24
Finished Jun 30 04:46:14 PM PDT 24
Peak memory 202272 kb
Host smart-895b3fc5-6d47-4d96-8248-8318369a3a10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774901758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.sram_ctrl_alert_test.2774901758
Directory /workspace/47.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sram_ctrl_bijection.2425902592
Short name T324
Test name
Test status
Simulation time 51522334295 ps
CPU time 1805.56 seconds
Started Jun 30 04:46:06 PM PDT 24
Finished Jun 30 05:16:12 PM PDT 24
Peak memory 202844 kb
Host smart-742b69fd-f6b9-4bb2-9ab4-3540e3c5c745
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425902592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection
.2425902592
Directory /workspace/47.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/47.sram_ctrl_executable.2577355053
Short name T321
Test name
Test status
Simulation time 2211660500 ps
CPU time 30.54 seconds
Started Jun 30 04:46:14 PM PDT 24
Finished Jun 30 04:46:45 PM PDT 24
Peak memory 202716 kb
Host smart-229d427e-adc8-4a87-ba06-17ed65d6c3a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577355053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executab
le.2577355053
Directory /workspace/47.sram_ctrl_executable/latest

Test location /workspace/coverage/default/47.sram_ctrl_lc_escalation.3426742800
Short name T8
Test name
Test status
Simulation time 51450614687 ps
CPU time 83.9 seconds
Started Jun 30 04:46:14 PM PDT 24
Finished Jun 30 04:47:38 PM PDT 24
Peak memory 202832 kb
Host smart-44377762-0c4d-49b1-94f8-7d18652117f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426742800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_es
calation.3426742800
Directory /workspace/47.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/47.sram_ctrl_max_throughput.3880891441
Short name T320
Test name
Test status
Simulation time 1461985720 ps
CPU time 7.04 seconds
Started Jun 30 04:46:06 PM PDT 24
Finished Jun 30 04:46:14 PM PDT 24
Peak memory 210804 kb
Host smart-0b36e1bc-4b4d-4865-92f0-f32b67f10e65
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880891441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.sram_ctrl_max_throughput.3880891441
Directory /workspace/47.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_partial_access.4172913420
Short name T108
Test name
Test status
Simulation time 3313017228 ps
CPU time 127.49 seconds
Started Jun 30 04:46:12 PM PDT 24
Finished Jun 30 04:48:20 PM PDT 24
Peak memory 210940 kb
Host smart-1dc53548-0b2b-4dba-8b16-915bcbed5e2c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172913420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_mem_partial_access.4172913420
Directory /workspace/47.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_walk.1607871186
Short name T289
Test name
Test status
Simulation time 7313762417 ps
CPU time 133.26 seconds
Started Jun 30 04:46:14 PM PDT 24
Finished Jun 30 04:48:28 PM PDT 24
Peak memory 210884 kb
Host smart-dd65b91b-9eab-402b-a2fe-c139529c45b3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607871186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr
l_mem_walk.1607871186
Directory /workspace/47.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/47.sram_ctrl_multiple_keys.2299389864
Short name T373
Test name
Test status
Simulation time 47589827143 ps
CPU time 2017.67 seconds
Started Jun 30 04:46:04 PM PDT 24
Finished Jun 30 05:19:42 PM PDT 24
Peak memory 379688 kb
Host smart-3e97ac38-8320-47eb-830a-32f192211834
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299389864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi
ple_keys.2299389864
Directory /workspace/47.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access.3777145741
Short name T591
Test name
Test status
Simulation time 1282639402 ps
CPU time 85.5 seconds
Started Jun 30 04:46:08 PM PDT 24
Finished Jun 30 04:47:34 PM PDT 24
Peak memory 345724 kb
Host smart-5f98f85c-90a3-4ea3-a62c-21d894bd10ad
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777145741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
sram_ctrl_partial_access.3777145741
Directory /workspace/47.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2228327024
Short name T354
Test name
Test status
Simulation time 3054180543 ps
CPU time 206.94 seconds
Started Jun 30 04:46:07 PM PDT 24
Finished Jun 30 04:49:35 PM PDT 24
Peak memory 202756 kb
Host smart-66eeeb4f-09dc-46a5-ac76-9b53b50b8a74
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228327024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 47.sram_ctrl_partial_access_b2b.2228327024
Directory /workspace/47.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/47.sram_ctrl_ram_cfg.270703782
Short name T827
Test name
Test status
Simulation time 1405188119 ps
CPU time 3.78 seconds
Started Jun 30 04:46:14 PM PDT 24
Finished Jun 30 04:46:18 PM PDT 24
Peak memory 202784 kb
Host smart-449f7551-060c-4608-a96d-5e83683e461b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270703782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.270703782
Directory /workspace/47.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/47.sram_ctrl_regwen.3896877884
Short name T493
Test name
Test status
Simulation time 50536459619 ps
CPU time 789.61 seconds
Started Jun 30 04:46:13 PM PDT 24
Finished Jun 30 04:59:23 PM PDT 24
Peak memory 372960 kb
Host smart-79e809ed-72e3-419d-990b-ef2353c4a65e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896877884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.3896877884
Directory /workspace/47.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/47.sram_ctrl_smoke.1380663893
Short name T846
Test name
Test status
Simulation time 10107793088 ps
CPU time 15.82 seconds
Started Jun 30 04:46:05 PM PDT 24
Finished Jun 30 04:46:21 PM PDT 24
Peak memory 202764 kb
Host smart-e82d62a1-75bd-4ecc-937f-61dded21812f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380663893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.1380663893
Directory /workspace/47.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all.3392564674
Short name T659
Test name
Test status
Simulation time 672456228148 ps
CPU time 5723.79 seconds
Started Jun 30 04:46:13 PM PDT 24
Finished Jun 30 06:21:38 PM PDT 24
Peak memory 398044 kb
Host smart-32143593-f8dd-4ef2-8854-4a7db29dbd46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392564674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 47.sram_ctrl_stress_all.3392564674
Directory /workspace/47.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3775258988
Short name T572
Test name
Test status
Simulation time 3300993832 ps
CPU time 18.03 seconds
Started Jun 30 04:46:12 PM PDT 24
Finished Jun 30 04:46:30 PM PDT 24
Peak memory 211044 kb
Host smart-7ff62def-a870-4b72-8e25-7eb17a28d6b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3775258988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.3775258988
Directory /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_pipeline.1488657729
Short name T216
Test name
Test status
Simulation time 14546518741 ps
CPU time 243.36 seconds
Started Jun 30 04:46:06 PM PDT 24
Finished Jun 30 04:50:09 PM PDT 24
Peak memory 202744 kb
Host smart-69a0924e-ff0d-46b4-b75f-c8a7e552f480
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488657729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_stress_pipeline.1488657729
Directory /workspace/47.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2112397982
Short name T630
Test name
Test status
Simulation time 14865958164 ps
CPU time 54.54 seconds
Started Jun 30 04:46:06 PM PDT 24
Finished Jun 30 04:47:00 PM PDT 24
Peak memory 314128 kb
Host smart-6aa406b4-4f9c-4f91-9eff-eed399abc092
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112397982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.2112397982
Directory /workspace/47.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/48.sram_ctrl_access_during_key_req.1227302273
Short name T857
Test name
Test status
Simulation time 50044470363 ps
CPU time 1063.68 seconds
Started Jun 30 04:46:12 PM PDT 24
Finished Jun 30 05:03:56 PM PDT 24
Peak memory 376532 kb
Host smart-39b3c312-0aba-4eb9-ad88-959f244ac220
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227302273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.sram_ctrl_access_during_key_req.1227302273
Directory /workspace/48.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/48.sram_ctrl_alert_test.2385780051
Short name T753
Test name
Test status
Simulation time 15087436 ps
CPU time 0.69 seconds
Started Jun 30 04:46:25 PM PDT 24
Finished Jun 30 04:46:26 PM PDT 24
Peak memory 202760 kb
Host smart-b635d4eb-b586-46e5-be60-520501bc1064
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385780051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.sram_ctrl_alert_test.2385780051
Directory /workspace/48.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sram_ctrl_bijection.1236482470
Short name T688
Test name
Test status
Simulation time 129678090701 ps
CPU time 753.45 seconds
Started Jun 30 04:46:13 PM PDT 24
Finished Jun 30 04:58:47 PM PDT 24
Peak memory 202968 kb
Host smart-98b8d24d-27b5-497e-a7f4-8c792393b628
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236482470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection
.1236482470
Directory /workspace/48.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/48.sram_ctrl_executable.785386649
Short name T273
Test name
Test status
Simulation time 14835633692 ps
CPU time 1120.24 seconds
Started Jun 30 04:46:20 PM PDT 24
Finished Jun 30 05:05:00 PM PDT 24
Peak memory 377824 kb
Host smart-85e1f6ba-1422-4aff-a4b3-17582c03078d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785386649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executabl
e.785386649
Directory /workspace/48.sram_ctrl_executable/latest

Test location /workspace/coverage/default/48.sram_ctrl_lc_escalation.1077967745
Short name T198
Test name
Test status
Simulation time 13406968592 ps
CPU time 86.95 seconds
Started Jun 30 04:46:15 PM PDT 24
Finished Jun 30 04:47:42 PM PDT 24
Peak memory 202764 kb
Host smart-8d613288-03cd-41d0-9c96-d3e80bc99762
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077967745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es
calation.1077967745
Directory /workspace/48.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/48.sram_ctrl_max_throughput.2252899779
Short name T888
Test name
Test status
Simulation time 1344522270 ps
CPU time 6.74 seconds
Started Jun 30 04:46:10 PM PDT 24
Finished Jun 30 04:46:18 PM PDT 24
Peak memory 211924 kb
Host smart-e7e05eec-98a7-459a-857f-7625fe64d612
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252899779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.sram_ctrl_max_throughput.2252899779
Directory /workspace/48.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_partial_access.3499601459
Short name T795
Test name
Test status
Simulation time 1917231912 ps
CPU time 62 seconds
Started Jun 30 04:46:22 PM PDT 24
Finished Jun 30 04:47:24 PM PDT 24
Peak memory 210864 kb
Host smart-4fb3f6c9-ffac-4344-8171-eab3898f578d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499601459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.sram_ctrl_mem_partial_access.3499601459
Directory /workspace/48.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_walk.3955588590
Short name T677
Test name
Test status
Simulation time 29169648130 ps
CPU time 306.41 seconds
Started Jun 30 04:46:19 PM PDT 24
Finished Jun 30 04:51:26 PM PDT 24
Peak memory 210996 kb
Host smart-25caa923-803a-43db-b03b-598dde96c4e9
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955588590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr
l_mem_walk.3955588590
Directory /workspace/48.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/48.sram_ctrl_multiple_keys.2120565193
Short name T325
Test name
Test status
Simulation time 310669722826 ps
CPU time 1013.15 seconds
Started Jun 30 04:46:14 PM PDT 24
Finished Jun 30 05:03:07 PM PDT 24
Peak memory 370784 kb
Host smart-03539ed9-e10e-4108-8e1f-b817d7995167
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120565193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multi
ple_keys.2120565193
Directory /workspace/48.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access.3788104228
Short name T744
Test name
Test status
Simulation time 1667345390 ps
CPU time 28.06 seconds
Started Jun 30 04:46:12 PM PDT 24
Finished Jun 30 04:46:41 PM PDT 24
Peak memory 202608 kb
Host smart-8144a972-e8fd-4ca0-b932-b5c9d6440166
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788104228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
sram_ctrl_partial_access.3788104228
Directory /workspace/48.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1757407541
Short name T895
Test name
Test status
Simulation time 16609956494 ps
CPU time 328.74 seconds
Started Jun 30 04:46:12 PM PDT 24
Finished Jun 30 04:51:41 PM PDT 24
Peak memory 202720 kb
Host smart-5331c6fb-591e-4c0e-a063-5b53a385dd3d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757407541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 48.sram_ctrl_partial_access_b2b.1757407541
Directory /workspace/48.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/48.sram_ctrl_ram_cfg.711143880
Short name T171
Test name
Test status
Simulation time 2237698240 ps
CPU time 3.71 seconds
Started Jun 30 04:46:22 PM PDT 24
Finished Jun 30 04:46:26 PM PDT 24
Peak memory 202812 kb
Host smart-0f89e01b-9275-462d-9b96-f69065e781bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711143880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.711143880
Directory /workspace/48.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/48.sram_ctrl_regwen.765983389
Short name T503
Test name
Test status
Simulation time 2243239469 ps
CPU time 729.64 seconds
Started Jun 30 04:46:25 PM PDT 24
Finished Jun 30 04:58:35 PM PDT 24
Peak memory 377288 kb
Host smart-dd3b30c8-8079-4882-89f8-f38d042e4683
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765983389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.765983389
Directory /workspace/48.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/48.sram_ctrl_smoke.1457708919
Short name T475
Test name
Test status
Simulation time 5000892656 ps
CPU time 73.54 seconds
Started Jun 30 04:46:16 PM PDT 24
Finished Jun 30 04:47:29 PM PDT 24
Peak memory 347924 kb
Host smart-854d2e53-5dae-4644-8aa9-da134314ed32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457708919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.1457708919
Directory /workspace/48.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_all.3731150986
Short name T190
Test name
Test status
Simulation time 41876086484 ps
CPU time 6666.57 seconds
Started Jun 30 04:46:18 PM PDT 24
Finished Jun 30 06:37:26 PM PDT 24
Peak memory 382768 kb
Host smart-613c6416-2434-4763-a64c-a332b03e5c81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731150986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 48.sram_ctrl_stress_all.3731150986
Directory /workspace/48.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_pipeline.3550594568
Short name T68
Test name
Test status
Simulation time 71738348558 ps
CPU time 373.51 seconds
Started Jun 30 04:46:15 PM PDT 24
Finished Jun 30 04:52:29 PM PDT 24
Peak memory 202760 kb
Host smart-278fbfc8-a9cd-45ff-9859-b63a2b2f30df
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550594568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.sram_ctrl_stress_pipeline.3550594568
Directory /workspace/48.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2407735170
Short name T380
Test name
Test status
Simulation time 3022347475 ps
CPU time 64.13 seconds
Started Jun 30 04:46:13 PM PDT 24
Finished Jun 30 04:47:18 PM PDT 24
Peak memory 322236 kb
Host smart-72a63b91-2e62-4519-8457-ed45c1146499
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407735170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.2407735170
Directory /workspace/48.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/49.sram_ctrl_access_during_key_req.3168432320
Short name T774
Test name
Test status
Simulation time 22639068587 ps
CPU time 327.57 seconds
Started Jun 30 04:46:26 PM PDT 24
Finished Jun 30 04:51:54 PM PDT 24
Peak memory 366208 kb
Host smart-b435037d-27a1-4f96-b4cf-9c51f7c54fac
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168432320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.sram_ctrl_access_during_key_req.3168432320
Directory /workspace/49.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/49.sram_ctrl_alert_test.2970368460
Short name T679
Test name
Test status
Simulation time 48019604 ps
CPU time 0.66 seconds
Started Jun 30 04:46:27 PM PDT 24
Finished Jun 30 04:46:28 PM PDT 24
Peak memory 202448 kb
Host smart-955ac1f6-f838-4567-95cc-8c7a9140d02d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970368460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.sram_ctrl_alert_test.2970368460
Directory /workspace/49.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sram_ctrl_bijection.789516478
Short name T262
Test name
Test status
Simulation time 38581965862 ps
CPU time 896.92 seconds
Started Jun 30 04:46:18 PM PDT 24
Finished Jun 30 05:01:16 PM PDT 24
Peak memory 203392 kb
Host smart-b4d8911c-7bdc-4a89-b73b-038e9f35eeb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789516478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection.
789516478
Directory /workspace/49.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/49.sram_ctrl_executable.2480907124
Short name T312
Test name
Test status
Simulation time 19860608697 ps
CPU time 707.49 seconds
Started Jun 30 04:46:27 PM PDT 24
Finished Jun 30 04:58:15 PM PDT 24
Peak memory 380448 kb
Host smart-3b05f2f3-5a34-4a16-aab4-ad198373e7ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480907124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executab
le.2480907124
Directory /workspace/49.sram_ctrl_executable/latest

Test location /workspace/coverage/default/49.sram_ctrl_lc_escalation.1706768780
Short name T467
Test name
Test status
Simulation time 22920080978 ps
CPU time 63.04 seconds
Started Jun 30 04:46:31 PM PDT 24
Finished Jun 30 04:47:34 PM PDT 24
Peak memory 211304 kb
Host smart-9d7f9411-74b0-4e98-91f4-0ff5ec5e6104
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706768780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es
calation.1706768780
Directory /workspace/49.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/49.sram_ctrl_max_throughput.3003545606
Short name T728
Test name
Test status
Simulation time 1423295030 ps
CPU time 27.43 seconds
Started Jun 30 04:46:31 PM PDT 24
Finished Jun 30 04:46:58 PM PDT 24
Peak memory 273520 kb
Host smart-cca8caae-65e3-44c6-b877-6e2698254c58
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003545606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.sram_ctrl_max_throughput.3003545606
Directory /workspace/49.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_partial_access.2227223576
Short name T393
Test name
Test status
Simulation time 18905751411 ps
CPU time 166.29 seconds
Started Jun 30 04:46:26 PM PDT 24
Finished Jun 30 04:49:13 PM PDT 24
Peak memory 210932 kb
Host smart-41988e20-50c3-41ea-9cc5-9bcf7a761ea7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227223576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_mem_partial_access.2227223576
Directory /workspace/49.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_walk.2495678957
Short name T448
Test name
Test status
Simulation time 5593375929 ps
CPU time 306.06 seconds
Started Jun 30 04:46:27 PM PDT 24
Finished Jun 30 04:51:34 PM PDT 24
Peak memory 210904 kb
Host smart-d2a6f4a7-79ea-4b66-8b84-7217410901e4
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495678957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr
l_mem_walk.2495678957
Directory /workspace/49.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/49.sram_ctrl_multiple_keys.3719700785
Short name T884
Test name
Test status
Simulation time 5731649512 ps
CPU time 687.69 seconds
Started Jun 30 04:46:19 PM PDT 24
Finished Jun 30 04:57:48 PM PDT 24
Peak memory 375892 kb
Host smart-f377df78-0b4f-4b9e-91c9-1a4834767791
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719700785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multi
ple_keys.3719700785
Directory /workspace/49.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access.1028760701
Short name T639
Test name
Test status
Simulation time 5307231097 ps
CPU time 187.13 seconds
Started Jun 30 04:46:26 PM PDT 24
Finished Jun 30 04:49:34 PM PDT 24
Peak memory 368312 kb
Host smart-60d7d95b-865d-445f-aea9-8a7f27d0823c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028760701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
sram_ctrl_partial_access.1028760701
Directory /workspace/49.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.919470043
Short name T935
Test name
Test status
Simulation time 9073258435 ps
CPU time 283.19 seconds
Started Jun 30 04:46:27 PM PDT 24
Finished Jun 30 04:51:11 PM PDT 24
Peak memory 202712 kb
Host smart-3215a306-8d9e-4c4c-b3bb-06156ef60d60
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919470043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.sram_ctrl_partial_access_b2b.919470043
Directory /workspace/49.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/49.sram_ctrl_ram_cfg.15638255
Short name T524
Test name
Test status
Simulation time 1876604975 ps
CPU time 3.48 seconds
Started Jun 30 04:46:26 PM PDT 24
Finished Jun 30 04:46:30 PM PDT 24
Peak memory 202676 kb
Host smart-9aa8932c-434e-4081-8cfd-e839780b7e44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15638255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf
g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.15638255
Directory /workspace/49.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/49.sram_ctrl_regwen.3088887909
Short name T508
Test name
Test status
Simulation time 2468085169 ps
CPU time 556.84 seconds
Started Jun 30 04:46:26 PM PDT 24
Finished Jun 30 04:55:44 PM PDT 24
Peak memory 375408 kb
Host smart-fbc9e690-7885-489c-b4b4-3dc06a5225ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088887909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.3088887909
Directory /workspace/49.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/49.sram_ctrl_smoke.1781961759
Short name T716
Test name
Test status
Simulation time 8611851701 ps
CPU time 76.99 seconds
Started Jun 30 04:46:25 PM PDT 24
Finished Jun 30 04:47:43 PM PDT 24
Peak memory 329884 kb
Host smart-c440b4d7-a858-4362-b64d-d1ead23682d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781961759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.1781961759
Directory /workspace/49.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all.2983396032
Short name T685
Test name
Test status
Simulation time 67922126247 ps
CPU time 6244.04 seconds
Started Jun 30 04:46:26 PM PDT 24
Finished Jun 30 06:30:31 PM PDT 24
Peak memory 385192 kb
Host smart-cab8b27f-e741-4ef2-8ac7-bda78a84a0cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983396032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 49.sram_ctrl_stress_all.2983396032
Directory /workspace/49.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1445478683
Short name T52
Test name
Test status
Simulation time 2652562441 ps
CPU time 152.67 seconds
Started Jun 30 04:46:26 PM PDT 24
Finished Jun 30 04:48:59 PM PDT 24
Peak memory 351156 kb
Host smart-d7c0f70a-180a-4c28-8d42-d0f5ac021a64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1445478683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.1445478683
Directory /workspace/49.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_pipeline.2925466510
Short name T239
Test name
Test status
Simulation time 11271723199 ps
CPU time 189.95 seconds
Started Jun 30 04:46:19 PM PDT 24
Finished Jun 30 04:49:30 PM PDT 24
Peak memory 202744 kb
Host smart-b06bc08a-8962-4bbe-9548-70c59b84abe3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925466510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_stress_pipeline.2925466510
Directory /workspace/49.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1210053444
Short name T152
Test name
Test status
Simulation time 3014670251 ps
CPU time 27.57 seconds
Started Jun 30 04:46:25 PM PDT 24
Finished Jun 30 04:46:53 PM PDT 24
Peak memory 281436 kb
Host smart-dd6b8982-bc52-45a0-88ef-9bc161b4de33
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210053444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.1210053444
Directory /workspace/49.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/5.sram_ctrl_access_during_key_req.110015264
Short name T910
Test name
Test status
Simulation time 3370133900 ps
CPU time 172.93 seconds
Started Jun 30 04:43:48 PM PDT 24
Finished Jun 30 04:46:42 PM PDT 24
Peak memory 337636 kb
Host smart-779c7961-6d00-4c6c-90b3-e65d7d726681
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110015264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 5.sram_ctrl_access_during_key_req.110015264
Directory /workspace/5.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/5.sram_ctrl_alert_test.3399424969
Short name T518
Test name
Test status
Simulation time 41680632 ps
CPU time 0.63 seconds
Started Jun 30 04:43:41 PM PDT 24
Finished Jun 30 04:43:42 PM PDT 24
Peak memory 202232 kb
Host smart-98218c1b-eb35-4da0-8e79-fe0bc61d4309
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399424969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.sram_ctrl_alert_test.3399424969
Directory /workspace/5.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sram_ctrl_bijection.2766078049
Short name T491
Test name
Test status
Simulation time 248253228266 ps
CPU time 2191.41 seconds
Started Jun 30 04:43:38 PM PDT 24
Finished Jun 30 05:20:10 PM PDT 24
Peak memory 203264 kb
Host smart-f95b1a13-01dc-4116-b7bf-4a087f63375b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766078049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.
2766078049
Directory /workspace/5.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/5.sram_ctrl_executable.2775224916
Short name T314
Test name
Test status
Simulation time 87426339343 ps
CPU time 1707.48 seconds
Started Jun 30 04:43:40 PM PDT 24
Finished Jun 30 05:12:08 PM PDT 24
Peak memory 377604 kb
Host smart-c32a1bc5-0967-4b2e-9421-4c738e850e17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775224916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl
e.2775224916
Directory /workspace/5.sram_ctrl_executable/latest

Test location /workspace/coverage/default/5.sram_ctrl_lc_escalation.1049355025
Short name T21
Test name
Test status
Simulation time 43440411237 ps
CPU time 44.15 seconds
Started Jun 30 04:43:49 PM PDT 24
Finished Jun 30 04:44:34 PM PDT 24
Peak memory 210964 kb
Host smart-a390df70-3130-428b-9e62-25492f8b8752
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049355025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esc
alation.1049355025
Directory /workspace/5.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/5.sram_ctrl_max_throughput.2562908635
Short name T281
Test name
Test status
Simulation time 919080259 ps
CPU time 38.26 seconds
Started Jun 30 04:43:43 PM PDT 24
Finished Jun 30 04:44:22 PM PDT 24
Peak memory 291912 kb
Host smart-b194da72-5716-4bd8-9638-df7b5e74c33b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562908635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.sram_ctrl_max_throughput.2562908635
Directory /workspace/5.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_partial_access.1769625169
Short name T741
Test name
Test status
Simulation time 2453813468 ps
CPU time 79.32 seconds
Started Jun 30 04:43:49 PM PDT 24
Finished Jun 30 04:45:09 PM PDT 24
Peak memory 210948 kb
Host smart-5087098f-5d25-41fa-a455-0a98b8805c2b
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769625169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_mem_partial_access.1769625169
Directory /workspace/5.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_walk.2395808775
Short name T67
Test name
Test status
Simulation time 4122556768 ps
CPU time 138.55 seconds
Started Jun 30 04:43:41 PM PDT 24
Finished Jun 30 04:46:01 PM PDT 24
Peak memory 210876 kb
Host smart-62a9c899-aaee-48a8-b5f5-8cd84e0d8852
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395808775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl
_mem_walk.2395808775
Directory /workspace/5.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/5.sram_ctrl_multiple_keys.2867980289
Short name T175
Test name
Test status
Simulation time 18789503273 ps
CPU time 1558.46 seconds
Started Jun 30 04:43:48 PM PDT 24
Finished Jun 30 05:09:48 PM PDT 24
Peak memory 379644 kb
Host smart-cafc2122-f314-4294-aa00-b45b195a40d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867980289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip
le_keys.2867980289
Directory /workspace/5.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access.3748006003
Short name T855
Test name
Test status
Simulation time 1047478595 ps
CPU time 13.91 seconds
Started Jun 30 04:43:41 PM PDT 24
Finished Jun 30 04:43:56 PM PDT 24
Peak memory 202620 kb
Host smart-a294589a-a22e-4171-89f3-22716f0dfd59
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748006003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s
ram_ctrl_partial_access.3748006003
Directory /workspace/5.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2205279114
Short name T256
Test name
Test status
Simulation time 23676443711 ps
CPU time 540.81 seconds
Started Jun 30 04:43:33 PM PDT 24
Finished Jun 30 04:52:35 PM PDT 24
Peak memory 202708 kb
Host smart-e35854e6-5874-4dbd-81cb-683592eacf20
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205279114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 5.sram_ctrl_partial_access_b2b.2205279114
Directory /workspace/5.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/5.sram_ctrl_ram_cfg.817626931
Short name T564
Test name
Test status
Simulation time 1407904101 ps
CPU time 3.3 seconds
Started Jun 30 04:44:04 PM PDT 24
Finished Jun 30 04:44:10 PM PDT 24
Peak memory 202652 kb
Host smart-f1e5836b-e82f-4011-8dff-cc1ad6dcfb47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817626931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.817626931
Directory /workspace/5.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/5.sram_ctrl_regwen.663779152
Short name T194
Test name
Test status
Simulation time 1310374256 ps
CPU time 133.82 seconds
Started Jun 30 04:43:43 PM PDT 24
Finished Jun 30 04:45:57 PM PDT 24
Peak memory 355988 kb
Host smart-194eb957-ec59-4111-9455-4b5fe5145fa0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663779152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.663779152
Directory /workspace/5.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/5.sram_ctrl_smoke.719135917
Short name T168
Test name
Test status
Simulation time 407362276 ps
CPU time 30.36 seconds
Started Jun 30 04:43:51 PM PDT 24
Finished Jun 30 04:44:23 PM PDT 24
Peak memory 282272 kb
Host smart-b306c6ed-15bf-4677-aed1-1cb23a805835
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719135917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.719135917
Directory /workspace/5.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all.3305728237
Short name T544
Test name
Test status
Simulation time 783805476067 ps
CPU time 7032.23 seconds
Started Jun 30 04:43:48 PM PDT 24
Finished Jun 30 06:41:02 PM PDT 24
Peak memory 388884 kb
Host smart-fdf1af2f-f367-40d2-931a-af7e9d04a20c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305728237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 5.sram_ctrl_stress_all.3305728237
Directory /workspace/5.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.288627752
Short name T545
Test name
Test status
Simulation time 2370209269 ps
CPU time 39.77 seconds
Started Jun 30 04:43:38 PM PDT 24
Finished Jun 30 04:44:18 PM PDT 24
Peak memory 211028 kb
Host smart-07a0d60c-6e7f-4739-b055-a74e20d1e9f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=288627752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.288627752
Directory /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_pipeline.1559555259
Short name T329
Test name
Test status
Simulation time 8734201291 ps
CPU time 269.91 seconds
Started Jun 30 04:43:54 PM PDT 24
Finished Jun 30 04:48:24 PM PDT 24
Peak memory 202756 kb
Host smart-3921abf0-0a0d-47aa-a8d2-93465406ab51
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559555259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_stress_pipeline.1559555259
Directory /workspace/5.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1708963402
Short name T352
Test name
Test status
Simulation time 1386191744 ps
CPU time 10.96 seconds
Started Jun 30 04:43:42 PM PDT 24
Finished Jun 30 04:43:54 PM PDT 24
Peak memory 235316 kb
Host smart-506e4086-2f27-4b0e-b13e-83c0e8fc6eb6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708963402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.1708963402
Directory /workspace/5.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/6.sram_ctrl_access_during_key_req.920193526
Short name T45
Test name
Test status
Simulation time 83677246369 ps
CPU time 1556.42 seconds
Started Jun 30 04:43:39 PM PDT 24
Finished Jun 30 05:09:37 PM PDT 24
Peak memory 377620 kb
Host smart-8e0bf950-5bea-4c0d-8d2a-35b6fdfafb68
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920193526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 6.sram_ctrl_access_during_key_req.920193526
Directory /workspace/6.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/6.sram_ctrl_alert_test.3347008639
Short name T661
Test name
Test status
Simulation time 13339115 ps
CPU time 0.7 seconds
Started Jun 30 04:43:45 PM PDT 24
Finished Jun 30 04:43:46 PM PDT 24
Peak memory 202468 kb
Host smart-aa90c097-4695-4dad-b0cd-dd445aab7a52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347008639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.sram_ctrl_alert_test.3347008639
Directory /workspace/6.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sram_ctrl_bijection.2056652155
Short name T804
Test name
Test status
Simulation time 151626539678 ps
CPU time 2214.84 seconds
Started Jun 30 04:43:43 PM PDT 24
Finished Jun 30 05:20:39 PM PDT 24
Peak memory 203436 kb
Host smart-cb968c95-25b6-4bc0-bd4c-f52d83d3b8ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056652155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.
2056652155
Directory /workspace/6.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/6.sram_ctrl_executable.319845574
Short name T623
Test name
Test status
Simulation time 28272762467 ps
CPU time 703.91 seconds
Started Jun 30 04:43:42 PM PDT 24
Finished Jun 30 04:55:27 PM PDT 24
Peak memory 372676 kb
Host smart-bf27f7cc-b15a-412e-b622-d7fea86081c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319845574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable
.319845574
Directory /workspace/6.sram_ctrl_executable/latest

Test location /workspace/coverage/default/6.sram_ctrl_lc_escalation.1570763406
Short name T157
Test name
Test status
Simulation time 7121118697 ps
CPU time 14.68 seconds
Started Jun 30 04:43:41 PM PDT 24
Finished Jun 30 04:43:56 PM PDT 24
Peak memory 210948 kb
Host smart-2d7f3038-3a62-493e-8774-02ed02e5fbd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570763406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esc
alation.1570763406
Directory /workspace/6.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/6.sram_ctrl_max_throughput.3720060768
Short name T147
Test name
Test status
Simulation time 8204553327 ps
CPU time 83.9 seconds
Started Jun 30 04:43:48 PM PDT 24
Finished Jun 30 04:45:13 PM PDT 24
Peak memory 328584 kb
Host smart-44741ba7-2a84-4d35-a2ab-50e55cdd3b99
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720060768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.sram_ctrl_max_throughput.3720060768
Directory /workspace/6.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_partial_access.2140645519
Short name T822
Test name
Test status
Simulation time 8771384243 ps
CPU time 155.2 seconds
Started Jun 30 04:43:40 PM PDT 24
Finished Jun 30 04:46:16 PM PDT 24
Peak memory 219096 kb
Host smart-2d43ee34-3b22-4a3a-bc93-3287916a5e00
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140645519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_mem_partial_access.2140645519
Directory /workspace/6.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_walk.4094634357
Short name T227
Test name
Test status
Simulation time 24255317830 ps
CPU time 310.18 seconds
Started Jun 30 04:43:45 PM PDT 24
Finished Jun 30 04:48:56 PM PDT 24
Peak memory 210864 kb
Host smart-8ee690be-36eb-4f55-9b40-301af562474a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094634357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl
_mem_walk.4094634357
Directory /workspace/6.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/6.sram_ctrl_multiple_keys.814782457
Short name T808
Test name
Test status
Simulation time 64797512324 ps
CPU time 743.46 seconds
Started Jun 30 04:43:37 PM PDT 24
Finished Jun 30 04:56:01 PM PDT 24
Peak memory 361720 kb
Host smart-2c27c5cd-c0bd-40b9-86f9-51774ef62ae1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814782457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multipl
e_keys.814782457
Directory /workspace/6.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access.336696334
Short name T270
Test name
Test status
Simulation time 2104824385 ps
CPU time 5.04 seconds
Started Jun 30 04:43:36 PM PDT 24
Finished Jun 30 04:43:41 PM PDT 24
Peak memory 202628 kb
Host smart-7e32bacf-5e6e-4e9d-9623-d36010486603
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336696334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sr
am_ctrl_partial_access.336696334
Directory /workspace/6.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1380510638
Short name T500
Test name
Test status
Simulation time 16120747304 ps
CPU time 531.71 seconds
Started Jun 30 04:43:48 PM PDT 24
Finished Jun 30 04:52:41 PM PDT 24
Peak memory 202744 kb
Host smart-d2a34b29-f889-47ce-93c3-068779215fd7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380510638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 6.sram_ctrl_partial_access_b2b.1380510638
Directory /workspace/6.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/6.sram_ctrl_ram_cfg.525158116
Short name T539
Test name
Test status
Simulation time 345770469 ps
CPU time 3.4 seconds
Started Jun 30 04:43:41 PM PDT 24
Finished Jun 30 04:43:46 PM PDT 24
Peak memory 202640 kb
Host smart-a2d3a994-6a29-4e6f-8161-322ba4ae59ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525158116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.525158116
Directory /workspace/6.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/6.sram_ctrl_regwen.327960776
Short name T579
Test name
Test status
Simulation time 51824749837 ps
CPU time 1019.19 seconds
Started Jun 30 04:43:45 PM PDT 24
Finished Jun 30 05:00:45 PM PDT 24
Peak memory 376564 kb
Host smart-6d5fe85e-9f49-45c3-b714-86d0ef3a4ac7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327960776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.327960776
Directory /workspace/6.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/6.sram_ctrl_smoke.1095511197
Short name T925
Test name
Test status
Simulation time 4633030866 ps
CPU time 18.14 seconds
Started Jun 30 04:43:47 PM PDT 24
Finished Jun 30 04:44:05 PM PDT 24
Peak memory 202752 kb
Host smart-fbe4cffc-83e0-45d2-b497-ccda08239eda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095511197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.1095511197
Directory /workspace/6.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_all.2618767789
Short name T712
Test name
Test status
Simulation time 19432442794 ps
CPU time 1695.76 seconds
Started Jun 30 04:43:52 PM PDT 24
Finished Jun 30 05:12:09 PM PDT 24
Peak memory 381716 kb
Host smart-27425777-0aca-4b4f-9bcc-1dbec26822b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618767789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 6.sram_ctrl_stress_all.2618767789
Directory /workspace/6.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2451284188
Short name T74
Test name
Test status
Simulation time 1345711552 ps
CPU time 11.54 seconds
Started Jun 30 04:43:50 PM PDT 24
Finished Jun 30 04:44:02 PM PDT 24
Peak memory 210892 kb
Host smart-25e46830-592b-4320-b65c-1c9ffbd68338
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2451284188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.2451284188
Directory /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_pipeline.3980495529
Short name T215
Test name
Test status
Simulation time 3739634958 ps
CPU time 243.69 seconds
Started Jun 30 04:43:32 PM PDT 24
Finished Jun 30 04:47:36 PM PDT 24
Peak memory 202716 kb
Host smart-366aa378-421b-41a7-bc7d-1466a32148dc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980495529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_stress_pipeline.3980495529
Directory /workspace/6.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3769930956
Short name T720
Test name
Test status
Simulation time 4216838027 ps
CPU time 80.58 seconds
Started Jun 30 04:43:41 PM PDT 24
Finished Jun 30 04:45:02 PM PDT 24
Peak memory 339664 kb
Host smart-2e6d7e9a-be8b-46ed-9d11-45e0fe4bf6cc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769930956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.3769930956
Directory /workspace/6.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/7.sram_ctrl_access_during_key_req.595486429
Short name T543
Test name
Test status
Simulation time 33001557792 ps
CPU time 676.7 seconds
Started Jun 30 04:44:00 PM PDT 24
Finished Jun 30 04:55:18 PM PDT 24
Peak memory 377768 kb
Host smart-5497dd3d-32fe-4c04-b4eb-cc8cc4d8f45a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595486429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 7.sram_ctrl_access_during_key_req.595486429
Directory /workspace/7.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/7.sram_ctrl_alert_test.2465107138
Short name T625
Test name
Test status
Simulation time 13760066 ps
CPU time 0.63 seconds
Started Jun 30 04:43:44 PM PDT 24
Finished Jun 30 04:43:45 PM PDT 24
Peak memory 202432 kb
Host smart-94c849c2-33c6-45e9-b459-24c83263656d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465107138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.sram_ctrl_alert_test.2465107138
Directory /workspace/7.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sram_ctrl_bijection.3224103138
Short name T926
Test name
Test status
Simulation time 461459950446 ps
CPU time 1416.06 seconds
Started Jun 30 04:43:43 PM PDT 24
Finished Jun 30 05:07:20 PM PDT 24
Peak memory 202792 kb
Host smart-7c138c07-9f3c-400a-bea6-5f4ed2dd157e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224103138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.
3224103138
Directory /workspace/7.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/7.sram_ctrl_executable.580186687
Short name T775
Test name
Test status
Simulation time 17549715689 ps
CPU time 597.48 seconds
Started Jun 30 04:43:56 PM PDT 24
Finished Jun 30 04:53:55 PM PDT 24
Peak memory 344832 kb
Host smart-4ce701c0-2413-4049-a66c-e8dc7706cda8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580186687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable
.580186687
Directory /workspace/7.sram_ctrl_executable/latest

Test location /workspace/coverage/default/7.sram_ctrl_lc_escalation.1253845320
Short name T226
Test name
Test status
Simulation time 22545908719 ps
CPU time 61.12 seconds
Started Jun 30 04:43:42 PM PDT 24
Finished Jun 30 04:44:44 PM PDT 24
Peak memory 202724 kb
Host smart-baea8fcf-1b02-41e5-8a29-0dfca3c36a23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253845320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esc
alation.1253845320
Directory /workspace/7.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/7.sram_ctrl_max_throughput.57066622
Short name T155
Test name
Test status
Simulation time 676112637 ps
CPU time 5.92 seconds
Started Jun 30 04:43:49 PM PDT 24
Finished Jun 30 04:43:56 PM PDT 24
Peak memory 210700 kb
Host smart-7be7cdaf-7aac-443e-8d19-0063b978d1f8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57066622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.sram_ctrl_max_throughput.57066622
Directory /workspace/7.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_partial_access.1067426472
Short name T861
Test name
Test status
Simulation time 6293151779 ps
CPU time 167.97 seconds
Started Jun 30 04:44:03 PM PDT 24
Finished Jun 30 04:46:53 PM PDT 24
Peak memory 210980 kb
Host smart-7597c404-b131-4704-8e0d-524b464265f6
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067426472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_mem_partial_access.1067426472
Directory /workspace/7.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_walk.3747561450
Short name T586
Test name
Test status
Simulation time 20696533535 ps
CPU time 350.02 seconds
Started Jun 30 04:43:50 PM PDT 24
Finished Jun 30 04:49:41 PM PDT 24
Peak memory 210844 kb
Host smart-18773bb8-d99d-49fa-9153-4d15430121a0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747561450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl
_mem_walk.3747561450
Directory /workspace/7.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/7.sram_ctrl_multiple_keys.889437439
Short name T585
Test name
Test status
Simulation time 21555388732 ps
CPU time 1525.88 seconds
Started Jun 30 04:43:48 PM PDT 24
Finished Jun 30 05:09:15 PM PDT 24
Peak memory 376532 kb
Host smart-41bfbb5a-070b-443e-97dd-84a25dfcc1d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889437439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multipl
e_keys.889437439
Directory /workspace/7.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access.695524528
Short name T742
Test name
Test status
Simulation time 1460892565 ps
CPU time 19.74 seconds
Started Jun 30 04:43:51 PM PDT 24
Finished Jun 30 04:44:12 PM PDT 24
Peak memory 202564 kb
Host smart-3b83c7b7-10b5-44d1-aab6-e683493dc446
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695524528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sr
am_ctrl_partial_access.695524528
Directory /workspace/7.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.4170311983
Short name T784
Test name
Test status
Simulation time 15726922966 ps
CPU time 363.43 seconds
Started Jun 30 04:43:51 PM PDT 24
Finished Jun 30 04:49:56 PM PDT 24
Peak memory 202716 kb
Host smart-70d2319b-ded0-495f-811f-7bfacbbb9f5d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170311983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 7.sram_ctrl_partial_access_b2b.4170311983
Directory /workspace/7.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/7.sram_ctrl_ram_cfg.1238418420
Short name T263
Test name
Test status
Simulation time 1397784464 ps
CPU time 3.52 seconds
Started Jun 30 04:44:00 PM PDT 24
Finished Jun 30 04:44:04 PM PDT 24
Peak memory 202668 kb
Host smart-948dd418-3ce8-4764-9795-372283d75482
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238418420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.1238418420
Directory /workspace/7.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/7.sram_ctrl_regwen.1400620835
Short name T541
Test name
Test status
Simulation time 51773053498 ps
CPU time 894.66 seconds
Started Jun 30 04:43:47 PM PDT 24
Finished Jun 30 04:58:42 PM PDT 24
Peak memory 372472 kb
Host smart-0bffe006-5dc3-47d1-9c00-ce20b3f950ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400620835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.1400620835
Directory /workspace/7.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/7.sram_ctrl_smoke.1296785842
Short name T251
Test name
Test status
Simulation time 1572284897 ps
CPU time 5.16 seconds
Started Jun 30 04:43:49 PM PDT 24
Finished Jun 30 04:43:55 PM PDT 24
Peak memory 207828 kb
Host smart-41f84800-dc6b-4e5f-a09f-304aab5beae3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296785842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.1296785842
Directory /workspace/7.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all.3377065637
Short name T246
Test name
Test status
Simulation time 47547146371 ps
CPU time 2068.89 seconds
Started Jun 30 04:43:48 PM PDT 24
Finished Jun 30 05:18:18 PM PDT 24
Peak memory 379948 kb
Host smart-90850508-859b-41b0-9133-d816f30cd24a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377065637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 7.sram_ctrl_stress_all.3377065637
Directory /workspace/7.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1810381722
Short name T444
Test name
Test status
Simulation time 1497324602 ps
CPU time 94.33 seconds
Started Jun 30 04:44:01 PM PDT 24
Finished Jun 30 04:45:37 PM PDT 24
Peak memory 315148 kb
Host smart-a220c7dd-d2d8-49f0-8be6-2b6b9a21ae97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1810381722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.1810381722
Directory /workspace/7.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_pipeline.587358662
Short name T363
Test name
Test status
Simulation time 54572576023 ps
CPU time 347.43 seconds
Started Jun 30 04:43:48 PM PDT 24
Finished Jun 30 04:49:36 PM PDT 24
Peak memory 202760 kb
Host smart-f757a3b1-2ad0-4504-8e62-50d7fac2535e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587358662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
sram_ctrl_stress_pipeline.587358662
Directory /workspace/7.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3310126487
Short name T470
Test name
Test status
Simulation time 2802245033 ps
CPU time 16.1 seconds
Started Jun 30 04:43:37 PM PDT 24
Finished Jun 30 04:43:54 PM PDT 24
Peak memory 251820 kb
Host smart-c95bed65-abaa-424e-9ed5-05cb21f3b4b6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310126487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.3310126487
Directory /workspace/7.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/8.sram_ctrl_access_during_key_req.242448101
Short name T697
Test name
Test status
Simulation time 55853076688 ps
CPU time 1293.85 seconds
Started Jun 30 04:43:49 PM PDT 24
Finished Jun 30 05:05:24 PM PDT 24
Peak memory 373468 kb
Host smart-b31db7fb-1e0a-48e2-b467-a19698fd2af4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242448101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 8.sram_ctrl_access_during_key_req.242448101
Directory /workspace/8.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/8.sram_ctrl_alert_test.1496539270
Short name T14
Test name
Test status
Simulation time 46291490 ps
CPU time 0.63 seconds
Started Jun 30 04:44:10 PM PDT 24
Finished Jun 30 04:44:11 PM PDT 24
Peak memory 202220 kb
Host smart-0c9f91be-b660-46fd-94c0-13fbddb670ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496539270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.sram_ctrl_alert_test.1496539270
Directory /workspace/8.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sram_ctrl_bijection.1734557641
Short name T394
Test name
Test status
Simulation time 31783952028 ps
CPU time 2121.03 seconds
Started Jun 30 04:43:54 PM PDT 24
Finished Jun 30 05:19:16 PM PDT 24
Peak memory 203448 kb
Host smart-e156faba-663a-4ced-84e3-d1bde7517c50
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734557641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.
1734557641
Directory /workspace/8.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/8.sram_ctrl_executable.3790645696
Short name T715
Test name
Test status
Simulation time 939209435 ps
CPU time 131.98 seconds
Started Jun 30 04:44:06 PM PDT 24
Finished Jun 30 04:46:20 PM PDT 24
Peak memory 368036 kb
Host smart-f0ede843-58c5-4e15-b03e-6f075d1401a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790645696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executabl
e.3790645696
Directory /workspace/8.sram_ctrl_executable/latest

Test location /workspace/coverage/default/8.sram_ctrl_lc_escalation.1309070822
Short name T283
Test name
Test status
Simulation time 4363535428 ps
CPU time 24.63 seconds
Started Jun 30 04:43:45 PM PDT 24
Finished Jun 30 04:44:11 PM PDT 24
Peak memory 211016 kb
Host smart-028ce343-488d-4afe-833e-24915fcf7de9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309070822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esc
alation.1309070822
Directory /workspace/8.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/8.sram_ctrl_max_throughput.1994442377
Short name T802
Test name
Test status
Simulation time 3061456198 ps
CPU time 161.16 seconds
Started Jun 30 04:43:48 PM PDT 24
Finished Jun 30 04:46:30 PM PDT 24
Peak memory 370304 kb
Host smart-5dc3b443-1ead-4419-b240-a8e05a17ea8f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994442377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.sram_ctrl_max_throughput.1994442377
Directory /workspace/8.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_partial_access.3049657988
Short name T505
Test name
Test status
Simulation time 3819113085 ps
CPU time 68.37 seconds
Started Jun 30 04:43:57 PM PDT 24
Finished Jun 30 04:45:06 PM PDT 24
Peak memory 210944 kb
Host smart-6aad9142-3bbd-4420-911f-89b78b0a1270
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049657988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_mem_partial_access.3049657988
Directory /workspace/8.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_walk.3329266850
Short name T790
Test name
Test status
Simulation time 13837253977 ps
CPU time 154.63 seconds
Started Jun 30 04:44:04 PM PDT 24
Finished Jun 30 04:46:41 PM PDT 24
Peak memory 210960 kb
Host smart-5d99813e-555f-4b52-a4a1-a1173fd1cfa5
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329266850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl
_mem_walk.3329266850
Directory /workspace/8.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/8.sram_ctrl_multiple_keys.16781730
Short name T532
Test name
Test status
Simulation time 20209958375 ps
CPU time 1650.97 seconds
Started Jun 30 04:43:43 PM PDT 24
Finished Jun 30 05:11:15 PM PDT 24
Peak memory 373564 kb
Host smart-95a0183a-a454-4aae-bcb6-2bc2717b83d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16781730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip
le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multiple
_keys.16781730
Directory /workspace/8.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access.2852522568
Short name T443
Test name
Test status
Simulation time 1478912865 ps
CPU time 4.24 seconds
Started Jun 30 04:44:01 PM PDT 24
Finished Jun 30 04:44:06 PM PDT 24
Peak memory 202592 kb
Host smart-2237a435-92f1-4098-9c0f-0d8f5b2ce80f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852522568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s
ram_ctrl_partial_access.2852522568
Directory /workspace/8.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3848108939
Short name T105
Test name
Test status
Simulation time 32158803797 ps
CPU time 381.03 seconds
Started Jun 30 04:43:59 PM PDT 24
Finished Jun 30 04:50:21 PM PDT 24
Peak memory 202716 kb
Host smart-729ef21e-c023-45f6-9397-e49b4fef3e6d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848108939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 8.sram_ctrl_partial_access_b2b.3848108939
Directory /workspace/8.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/8.sram_ctrl_ram_cfg.3055703829
Short name T495
Test name
Test status
Simulation time 355117233 ps
CPU time 3.32 seconds
Started Jun 30 04:43:56 PM PDT 24
Finished Jun 30 04:44:00 PM PDT 24
Peak memory 202740 kb
Host smart-ef4e3a4d-6722-455d-8532-4e86aaadff36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055703829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.3055703829
Directory /workspace/8.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/8.sram_ctrl_regwen.73576783
Short name T131
Test name
Test status
Simulation time 61746639662 ps
CPU time 1382.32 seconds
Started Jun 30 04:43:51 PM PDT 24
Finished Jun 30 05:06:55 PM PDT 24
Peak memory 378596 kb
Host smart-3d3f379c-0fc8-49a8-9697-c48475ff3975
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73576783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.73576783
Directory /workspace/8.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/8.sram_ctrl_smoke.224576210
Short name T701
Test name
Test status
Simulation time 1399287410 ps
CPU time 7.2 seconds
Started Jun 30 04:43:51 PM PDT 24
Finished Jun 30 04:44:00 PM PDT 24
Peak memory 205112 kb
Host smart-46adcb23-a695-475f-b6a9-25ef135db4f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224576210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.224576210
Directory /workspace/8.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all.3217858457
Short name T355
Test name
Test status
Simulation time 291356677924 ps
CPU time 6810.68 seconds
Started Jun 30 04:43:59 PM PDT 24
Finished Jun 30 06:37:31 PM PDT 24
Peak memory 380672 kb
Host smart-365d1b0a-a7d2-4371-8514-9829710287b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217858457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 8.sram_ctrl_stress_all.3217858457
Directory /workspace/8.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.403565463
Short name T772
Test name
Test status
Simulation time 207401163 ps
CPU time 8.05 seconds
Started Jun 30 04:44:01 PM PDT 24
Finished Jun 30 04:44:10 PM PDT 24
Peak memory 217664 kb
Host smart-6f4cec58-8ac7-45e4-9eb5-510615c4e90d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=403565463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.403565463
Directory /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_pipeline.3338486111
Short name T512
Test name
Test status
Simulation time 3438844861 ps
CPU time 232.19 seconds
Started Jun 30 04:43:54 PM PDT 24
Finished Jun 30 04:47:47 PM PDT 24
Peak memory 202744 kb
Host smart-4738ec8b-0021-4cb4-b188-02fd1da8d272
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338486111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_stress_pipeline.3338486111
Directory /workspace/8.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2647356605
Short name T327
Test name
Test status
Simulation time 3381882126 ps
CPU time 146.6 seconds
Started Jun 30 04:43:58 PM PDT 24
Finished Jun 30 04:46:25 PM PDT 24
Peak memory 369300 kb
Host smart-ee994918-680c-49e2-a399-5e94eda54245
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647356605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.2647356605
Directory /workspace/8.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/9.sram_ctrl_access_during_key_req.2178352660
Short name T667
Test name
Test status
Simulation time 9346055521 ps
CPU time 800.19 seconds
Started Jun 30 04:43:59 PM PDT 24
Finished Jun 30 04:57:21 PM PDT 24
Peak memory 379796 kb
Host smart-fbe0d597-ce09-49ff-ab30-b34745cd4acb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178352660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.sram_ctrl_access_during_key_req.2178352660
Directory /workspace/9.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/9.sram_ctrl_alert_test.3353611279
Short name T415
Test name
Test status
Simulation time 17974797 ps
CPU time 0.64 seconds
Started Jun 30 04:43:50 PM PDT 24
Finished Jun 30 04:43:51 PM PDT 24
Peak memory 202260 kb
Host smart-e84c4cfe-f36d-4e7b-925b-b329095f5fae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353611279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.sram_ctrl_alert_test.3353611279
Directory /workspace/9.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sram_ctrl_bijection.1721728357
Short name T153
Test name
Test status
Simulation time 93094734023 ps
CPU time 565.71 seconds
Started Jun 30 04:43:58 PM PDT 24
Finished Jun 30 04:53:24 PM PDT 24
Peak memory 203208 kb
Host smart-3bf66aaa-e48b-4add-bec0-0b3f1d16443a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721728357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.
1721728357
Directory /workspace/9.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/9.sram_ctrl_executable.2875527534
Short name T199
Test name
Test status
Simulation time 9944385438 ps
CPU time 488.84 seconds
Started Jun 30 04:43:42 PM PDT 24
Finished Jun 30 04:51:52 PM PDT 24
Peak memory 376536 kb
Host smart-1e5ecaaf-d3cb-4ced-b97c-a9f81150b675
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875527534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl
e.2875527534
Directory /workspace/9.sram_ctrl_executable/latest

Test location /workspace/coverage/default/9.sram_ctrl_lc_escalation.225764244
Short name T387
Test name
Test status
Simulation time 37772989609 ps
CPU time 58.05 seconds
Started Jun 30 04:44:03 PM PDT 24
Finished Jun 30 04:45:03 PM PDT 24
Peak memory 202824 kb
Host smart-442b6410-2f2b-4919-9df4-b59325616492
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225764244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esca
lation.225764244
Directory /workspace/9.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/9.sram_ctrl_max_throughput.2081210451
Short name T786
Test name
Test status
Simulation time 722894679 ps
CPU time 25.77 seconds
Started Jun 30 04:44:05 PM PDT 24
Finished Jun 30 04:44:33 PM PDT 24
Peak memory 278284 kb
Host smart-79c532e3-0596-4c77-8258-b574ef330e8d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081210451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.sram_ctrl_max_throughput.2081210451
Directory /workspace/9.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_partial_access.1771046157
Short name T361
Test name
Test status
Simulation time 1583895471 ps
CPU time 119.74 seconds
Started Jun 30 04:43:54 PM PDT 24
Finished Jun 30 04:45:54 PM PDT 24
Peak memory 210892 kb
Host smart-ef838983-f0da-40af-881b-9e8b7521a93c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771046157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_mem_partial_access.1771046157
Directory /workspace/9.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_walk.2571890398
Short name T565
Test name
Test status
Simulation time 2019836496 ps
CPU time 130.97 seconds
Started Jun 30 04:43:56 PM PDT 24
Finished Jun 30 04:46:07 PM PDT 24
Peak memory 210732 kb
Host smart-1b46dd11-fcd2-49c6-8c5d-ad199a92ac5d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571890398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl
_mem_walk.2571890398
Directory /workspace/9.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/9.sram_ctrl_multiple_keys.2974031932
Short name T519
Test name
Test status
Simulation time 86564704565 ps
CPU time 1271 seconds
Started Jun 30 04:43:51 PM PDT 24
Finished Jun 30 05:05:03 PM PDT 24
Peak memory 380260 kb
Host smart-5355f021-1ab9-4035-8550-f3beb54f472f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974031932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip
le_keys.2974031932
Directory /workspace/9.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access.3087420576
Short name T191
Test name
Test status
Simulation time 3214595011 ps
CPU time 8.78 seconds
Started Jun 30 04:43:45 PM PDT 24
Finished Jun 30 04:43:55 PM PDT 24
Peak memory 202772 kb
Host smart-ef6c321f-3f9b-40d2-ac96-5a30b8a9c114
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087420576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s
ram_ctrl_partial_access.3087420576
Directory /workspace/9.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1896018640
Short name T206
Test name
Test status
Simulation time 45628519666 ps
CPU time 255.35 seconds
Started Jun 30 04:43:55 PM PDT 24
Finished Jun 30 04:48:11 PM PDT 24
Peak memory 202716 kb
Host smart-7970a2b9-f443-4b13-83f3-1468d4802008
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896018640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 9.sram_ctrl_partial_access_b2b.1896018640
Directory /workspace/9.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/9.sram_ctrl_ram_cfg.603324092
Short name T881
Test name
Test status
Simulation time 363100327 ps
CPU time 3.45 seconds
Started Jun 30 04:43:54 PM PDT 24
Finished Jun 30 04:43:58 PM PDT 24
Peak memory 202704 kb
Host smart-08b1a5e8-b22a-45b4-8201-812b458af34c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603324092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.603324092
Directory /workspace/9.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/9.sram_ctrl_regwen.4137101076
Short name T763
Test name
Test status
Simulation time 2265643880 ps
CPU time 155.47 seconds
Started Jun 30 04:43:51 PM PDT 24
Finished Jun 30 04:46:28 PM PDT 24
Peak memory 342708 kb
Host smart-ddcd186f-4bbc-4567-bf8b-b18eef3250c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137101076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.4137101076
Directory /workspace/9.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/9.sram_ctrl_smoke.3427659962
Short name T933
Test name
Test status
Simulation time 1112368698 ps
CPU time 18.34 seconds
Started Jun 30 04:43:58 PM PDT 24
Finished Jun 30 04:44:18 PM PDT 24
Peak memory 202648 kb
Host smart-e8afc142-cd9b-40a3-81c4-9dcc2086b428
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427659962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.3427659962
Directory /workspace/9.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all.2674152053
Short name T721
Test name
Test status
Simulation time 34675272947 ps
CPU time 3732.33 seconds
Started Jun 30 04:43:59 PM PDT 24
Finished Jun 30 05:46:13 PM PDT 24
Peak memory 384744 kb
Host smart-300e940d-953e-403b-8f99-0b2b555066fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674152053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 9.sram_ctrl_stress_all.2674152053
Directory /workspace/9.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2688176888
Short name T32
Test name
Test status
Simulation time 1405727712 ps
CPU time 37.77 seconds
Started Jun 30 04:43:50 PM PDT 24
Finished Jun 30 04:44:29 PM PDT 24
Peak memory 210992 kb
Host smart-145502d9-cda5-4576-8265-cef944beb2a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2688176888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.2688176888
Directory /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_pipeline.2890746827
Short name T474
Test name
Test status
Simulation time 4736681917 ps
CPU time 283.5 seconds
Started Jun 30 04:44:02 PM PDT 24
Finished Jun 30 04:48:47 PM PDT 24
Peak memory 202700 kb
Host smart-53c051c8-f16b-4cbd-8142-c0513e03dd7f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890746827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_stress_pipeline.2890746827
Directory /workspace/9.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1643236604
Short name T161
Test name
Test status
Simulation time 721226526 ps
CPU time 7.55 seconds
Started Jun 30 04:43:44 PM PDT 24
Finished Jun 30 04:43:52 PM PDT 24
Peak memory 218772 kb
Host smart-d5bd4cee-0f94-42fb-8e2d-687adaae441b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643236604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.1643236604
Directory /workspace/9.sram_ctrl_throughput_w_partial_write/latest
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