Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15855331	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

148590406

1

T1

325

T2

862

T3

2001

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	80830801	1			T1	953		T2	536		T3	543
values[0x0]	40227750	1			T1	310		T2	246		T3	740
values[0x1]	43387186	1			T1	606		T2	283		T3	718

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8064041	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

156381696

1

T1

1114

T2

968

T3

2001

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1512619	1			T1	4		T3	4		T4	769
valid_sources[0x01]	542281	1			T1	17		T3	8		T4	772
valid_sources[0x02]	535798	1			T1	11		T3	12		T4	778
valid_sources[0x03]	518117	1			T1	17		T2	263		T3	11
valid_sources[0x04]	535517	1			T1	3		T3	5		T4	734
valid_sources[0x05]	538476	1			T1	8		T3	6		T4	821
valid_sources[0x06]	510530	1			T1	5		T3	5		T4	785
valid_sources[0x07]	579943	1			T1	6		T3	11		T4	810
valid_sources[0x08]	503526	1			T1	6		T3	6		T4	789
valid_sources[0x09]	532263	1			T1	5		T3	6		T4	766
valid_sources[0x0a]	550115	1			T1	8		T3	3		T4	788
valid_sources[0x0b]	540926	1			T1	11		T3	10		T4	768
valid_sources[0x0c]	579245	1			T1	4		T3	8		T4	746
valid_sources[0x0d]	592446	1			T1	1		T3	4		T4	785
valid_sources[0x0e]	498138	1			T1	15		T3	6		T4	788
valid_sources[0x0f]	531737	1			T1	15		T3	9		T4	793
valid_sources[0x10]	527217	1			T1	3		T3	9		T4	765
valid_sources[0x11]	508644	1			T1	9		T3	5		T4	718
valid_sources[0x12]	514829	1			T1	1		T3	5		T4	756
valid_sources[0x13]	1634175	1			T1	5		T3	5		T4	840
valid_sources[0x14]	681219	1			T1	2		T3	4		T4	756
valid_sources[0x15]	538818	1			T1	4		T2	169		T3	6
valid_sources[0x16]	529508	1			T1	3		T3	1		T4	776
valid_sources[0x17]	1292682	1			T1	5		T3	6		T4	728
valid_sources[0x18]	553618	1			T1	11		T3	10		T4	722
valid_sources[0x19]	508608	1			T3	8		T4	749		T9	42
valid_sources[0x1a]	537110	1			T1	3		T3	3		T4	794
valid_sources[0x1b]	533164	1			T1	15		T3	9		T4	830
valid_sources[0x1c]	509852	1			T1	2		T3	6		T4	753
valid_sources[0x1d]	502044	1			T1	6		T3	14		T4	813
valid_sources[0x1e]	518999	1			T1	8		T3	3		T4	723
valid_sources[0x1f]	508330	1			T1	4		T3	5		T4	779
valid_sources[0x20]	557139	1			T1	2		T3	9		T4	793
valid_sources[0x21]	508821	1			T1	2		T3	3		T4	779
valid_sources[0x22]	526479	1			T1	10		T3	12		T4	739
valid_sources[0x23]	507353	1			T1	8		T3	9		T4	795
valid_sources[0x24]	553643	1			T1	11		T3	10		T4	732
valid_sources[0x25]	562805	1			T1	2		T3	9		T4	722
valid_sources[0x26]	512248	1			T1	13		T3	11		T4	744
valid_sources[0x27]	508919	1			T1	5		T3	5		T4	762
valid_sources[0x28]	562173	1			T1	15		T3	11		T4	751
valid_sources[0x29]	881709	1			T1	1		T3	10		T4	721
valid_sources[0x2a]	502864	1			T1	7		T3	12		T4	724
valid_sources[0x2b]	508580	1			T1	11		T3	8		T4	731
valid_sources[0x2c]	3004639	1			T1	5		T3	12		T4	719
valid_sources[0x2d]	573178	1			T1	4		T3	8		T4	734
valid_sources[0x2e]	504192	1			T1	7		T3	10		T4	765
valid_sources[0x2f]	520709	1			T3	11		T4	781		T9	33
valid_sources[0x30]	595871	1			T1	14		T3	7		T4	797
valid_sources[0x31]	576966	1			T1	2		T3	11		T4	799
valid_sources[0x32]	527035	1			T1	12		T3	14		T4	760
valid_sources[0x33]	564083	1			T1	3		T3	10		T4	836
valid_sources[0x34]	700540	1			T1	4		T3	13		T4	778
valid_sources[0x35]	757693	1			T1	2		T3	9		T4	772
valid_sources[0x36]	572079	1			T1	4		T3	11		T4	723
valid_sources[0x37]	502505	1			T1	3		T3	14		T4	782
valid_sources[0x38]	497637	1			T1	2		T3	12		T4	763
valid_sources[0x39]	516285	1			T1	11		T3	12		T4	746
valid_sources[0x3a]	543619	1			T1	8		T3	4		T4	765
valid_sources[0x3b]	498059	1			T1	7		T3	7		T4	763
valid_sources[0x3c]	560798	1			T1	22		T3	11		T4	770
valid_sources[0x3d]	516436	1			T1	14		T3	1		T4	792
valid_sources[0x3e]	609456	1			T1	13		T3	4		T4	763
valid_sources[0x3f]	535850	1			T1	3		T3	7		T4	712
valid_sources[0x40]	502001	1			T1	10		T3	6		T4	731
valid_sources[0x41]	501260	1			T1	17		T3	11		T4	728
valid_sources[0x42]	526036	1			T1	10		T3	14		T4	776
valid_sources[0x43]	1619696	1			T1	9		T3	10		T4	730
valid_sources[0x44]	526668	1			T1	7		T3	17		T4	770
valid_sources[0x45]	560458	1			T1	9		T3	5		T4	787
valid_sources[0x46]	533615	1			T1	3		T3	9		T4	720
valid_sources[0x47]	508002	1			T1	9		T3	6		T4	812
valid_sources[0x48]	607929	1			T1	16		T3	2		T4	751
valid_sources[0x49]	637467	1			T1	6		T3	14		T4	768
valid_sources[0x4a]	575392	1			T1	15		T3	7		T4	726
valid_sources[0x4b]	534106	1			T1	3		T2	98		T3	9
valid_sources[0x4c]	519602	1			T1	12		T3	10		T4	787
valid_sources[0x4d]	626882	1			T1	12		T3	10		T4	785
valid_sources[0x4e]	517268	1			T1	5		T3	6		T4	753
valid_sources[0x4f]	505019	1			T1	16		T3	6		T4	794
valid_sources[0x50]	526720	1			T1	5		T3	7		T4	723
valid_sources[0x51]	750583	1			T1	10		T3	5		T4	823
valid_sources[0x52]	508535	1			T1	4		T3	1		T4	799
valid_sources[0x53]	512509	1			T1	10		T3	8		T4	775
valid_sources[0x54]	528221	1			T1	12		T3	9		T4	793
valid_sources[0x55]	601884	1			T1	4		T3	5		T4	706
valid_sources[0x56]	528873	1			T1	13		T3	11		T4	812
valid_sources[0x57]	512609	1			T1	9		T3	8		T4	787
valid_sources[0x58]	510453	1			T1	17		T3	8		T4	748
valid_sources[0x59]	708687	1			T1	4		T3	6		T4	794
valid_sources[0x5a]	499528	1			T1	3		T3	4		T4	812
valid_sources[0x5b]	1232311	1			T1	17		T3	3		T4	785
valid_sources[0x5c]	544547	1			T1	1		T3	3		T4	760
valid_sources[0x5d]	531531	1			T1	8		T3	13		T4	744
valid_sources[0x5e]	546302	1			T1	9		T3	2		T4	738
valid_sources[0x5f]	602431	1			T1	10		T3	13		T4	681
valid_sources[0x60]	565343	1			T1	6		T3	9		T4	753
valid_sources[0x61]	525538	1			T1	7		T3	8		T4	776
valid_sources[0x62]	518955	1			T1	6		T3	7		T4	777
valid_sources[0x63]	563110	1			T1	5		T3	8		T4	722
valid_sources[0x64]	554971	1			T1	4		T3	6		T4	739
valid_sources[0x65]	558005	1			T1	4		T3	11		T4	784
valid_sources[0x66]	532681	1			T3	17		T4	754		T9	35
valid_sources[0x67]	1755629	1			T1	12		T3	8		T4	726
valid_sources[0x68]	526346	1			T1	7		T3	7		T4	759
valid_sources[0x69]	537758	1			T1	8		T3	6		T4	800
valid_sources[0x6a]	522437	1			T1	8		T3	12		T4	801
valid_sources[0x6b]	517338	1			T1	11		T3	13		T4	830
valid_sources[0x6c]	503546	1			T1	6		T3	16		T4	756
valid_sources[0x6d]	502864	1			T1	14		T3	13		T4	758
valid_sources[0x6e]	515650	1			T3	2		T4	739		T9	31
valid_sources[0x6f]	515878	1			T1	4		T3	3		T4	732
valid_sources[0x70]	547620	1			T1	4		T3	7		T4	708
valid_sources[0x71]	535817	1			T1	7		T3	14		T4	747
valid_sources[0x72]	610764	1			T1	3		T3	7		T4	787
valid_sources[0x73]	498137	1			T1	9		T3	3		T4	794
valid_sources[0x74]	586170	1			T1	14		T3	5		T4	734
valid_sources[0x75]	553259	1			T1	5		T3	10		T4	763
valid_sources[0x76]	512643	1			T1	5		T3	9		T4	792
valid_sources[0x77]	516648	1			T1	3		T3	12		T4	739
valid_sources[0x78]	545757	1			T1	7		T3	6		T4	782
valid_sources[0x79]	550626	1			T1	6		T3	13		T4	767
valid_sources[0x7a]	513837	1			T1	12		T3	9		T4	753
valid_sources[0x7b]	502843	1			T1	1		T3	10		T4	774
valid_sources[0x7c]	541832	1			T1	7		T3	2		T4	730
valid_sources[0x7d]	510057	1			T1	16		T3	6		T4	769
valid_sources[0x7e]	522415	1			T1	4		T3	8		T4	789
valid_sources[0x7f]	535829	1			T1	7		T3	7		T4	762
valid_sources[0x80]	508995	1			T3	14		T4	803		T9	31

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

72862419

1

T1

168

T2

433

T3

543

values[0x0]

all_enables

biggest_size

37860297

1

T1

89

T2

214

T3

740

values[0x1]

all_enables

biggest_size

37867690

1

T1

68

T2

215

T3

718

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46966	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

156671

1

T2

1

T3

1137

T4

92

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	55521	1			T3	340		T13	12		T6	78
values[0x0]	71465	1			T1	1		T2	1		T3	427
values[0x1]	76651	1			T1	1		T2	1		T3	457

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36410	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

167227

1

T2

1

T3

1176

T4

119

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	680	1			T23	19		T24	1		T64	17
valid_sources[0x01]	816	1			T4	1		T6	5		T23	4
valid_sources[0x02]	695	1			T4	2		T23	4		T24	3
valid_sources[0x03]	550	1			T3	2		T4	1		T6	6
valid_sources[0x04]	775	1			T7	2		T24	3		T64	26
valid_sources[0x05]	698	1			T10	1		T23	55		T64	13
valid_sources[0x06]	756	1			T24	11		T64	7		T66	9
valid_sources[0x07]	787	1			T13	1		T23	44		T24	3
valid_sources[0x08]	675	1			T4	3		T23	8		T24	1
valid_sources[0x09]	1201	1			T23	5		T24	7		T64	23
valid_sources[0x0a]	964	1			T3	133		T23	66		T24	2
valid_sources[0x0b]	678	1			T4	2		T23	1		T24	11
valid_sources[0x0c]	867	1			T4	3		T23	33		T7	2
valid_sources[0x0d]	931	1			T6	6		T23	17		T24	6
valid_sources[0x0e]	673	1			T4	2		T42	1		T64	10
valid_sources[0x0f]	722	1			T4	5		T23	1		T24	3
valid_sources[0x10]	1055	1			T6	1		T23	2		T24	2
valid_sources[0x11]	666	1			T6	1		T23	40		T24	11
valid_sources[0x12]	677	1			T6	2		T23	37		T98	3
valid_sources[0x13]	695	1			T6	1		T23	1		T24	8
valid_sources[0x14]	618	1			T4	4		T23	4		T24	2
valid_sources[0x15]	670	1			T23	25		T64	15		T71	2
valid_sources[0x16]	723	1			T4	2		T13	2		T6	1
valid_sources[0x17]	843	1			T13	3		T6	2		T23	16
valid_sources[0x18]	731	1			T4	4		T6	1		T24	7
valid_sources[0x19]	891	1			T6	4		T23	6		T24	12
valid_sources[0x1a]	721	1			T4	1		T23	10		T24	3
valid_sources[0x1b]	703	1			T4	3		T23	55		T24	1
valid_sources[0x1c]	927	1			T23	3		T137	4		T118	1
valid_sources[0x1d]	1007	1			T4	3		T13	1		T6	1
valid_sources[0x1e]	1098	1			T4	3		T24	3		T64	3
valid_sources[0x1f]	1025	1			T4	1		T23	4		T24	3
valid_sources[0x20]	969	1			T4	3		T23	1		T24	3
valid_sources[0x21]	767	1			T4	1		T6	9		T23	32
valid_sources[0x22]	790	1			T3	1		T4	1		T23	3
valid_sources[0x23]	711	1			T4	2		T24	11		T64	17
valid_sources[0x24]	573	1			T4	2		T64	10		T31	1
valid_sources[0x25]	1049	1			T4	2		T64	23		T65	2
valid_sources[0x26]	714	1			T3	1		T6	1		T23	15
valid_sources[0x27]	918	1			T4	1		T23	22		T24	2
valid_sources[0x28]	631	1			T4	6		T6	5		T23	13
valid_sources[0x29]	681	1			T4	6		T23	15		T24	4
valid_sources[0x2a]	751	1			T4	4		T6	1		T23	48
valid_sources[0x2b]	782	1			T3	3		T4	2		T6	4
valid_sources[0x2c]	666	1			T4	3		T24	8		T64	16
valid_sources[0x2d]	684	1			T4	3		T24	7		T64	4
valid_sources[0x2e]	682	1			T4	1		T23	2		T24	8
valid_sources[0x2f]	961	1			T4	2		T23	23		T24	9
valid_sources[0x30]	635	1			T6	1		T23	30		T24	3
valid_sources[0x31]	664	1			T6	3		T23	7		T24	6
valid_sources[0x32]	933	1			T13	3		T23	38		T7	2
valid_sources[0x33]	746	1			T13	3		T6	1		T23	39
valid_sources[0x34]	762	1			T4	2		T6	1		T36	2
valid_sources[0x35]	818	1			T23	6		T24	11		T64	7
valid_sources[0x36]	751	1			T23	39		T24	1		T64	15
valid_sources[0x37]	732	1			T4	2		T23	4		T24	5
valid_sources[0x38]	803	1			T13	1		T6	3		T42	1
valid_sources[0x39]	780	1			T3	10		T6	1		T23	21
valid_sources[0x3a]	831	1			T4	5		T13	1		T42	1
valid_sources[0x3b]	765	1			T24	3		T97	1		T138	1
valid_sources[0x3c]	736	1			T4	1		T7	1		T24	3
valid_sources[0x3d]	823	1			T3	72		T4	3		T6	1
valid_sources[0x3e]	702	1			T23	5		T17	1		T65	100
valid_sources[0x3f]	851	1			T6	2		T23	8		T24	1
valid_sources[0x40]	692	1			T23	2		T24	3		T64	5
valid_sources[0x41]	577	1			T4	2		T13	1		T23	15
valid_sources[0x42]	696	1			T23	61		T24	2		T64	24
valid_sources[0x43]	612	1			T23	1		T24	5		T64	28
valid_sources[0x44]	683	1			T4	2		T23	50		T24	7
valid_sources[0x45]	1016	1			T4	2		T13	1		T6	1
valid_sources[0x46]	932	1			T23	17		T24	9		T8	6
valid_sources[0x47]	525	1			T23	1		T24	2		T64	1
valid_sources[0x48]	874	1			T4	2		T13	2		T6	1
valid_sources[0x49]	802	1			T4	2		T23	1		T24	1
valid_sources[0x4a]	905	1			T4	1		T24	5		T64	8
valid_sources[0x4b]	822	1			T3	2		T4	2		T23	1
valid_sources[0x4c]	580	1			T4	2		T23	11		T24	4
valid_sources[0x4d]	674	1			T4	1		T6	2		T23	42
valid_sources[0x4e]	725	1			T4	1		T7	2		T24	2
valid_sources[0x4f]	712	1			T4	4		T6	1		T24	3
valid_sources[0x50]	827	1			T4	10		T6	1		T23	3
valid_sources[0x51]	588	1			T4	2		T6	1		T23	12
valid_sources[0x52]	1089	1			T6	9		T23	40		T7	1
valid_sources[0x53]	596	1			T4	1		T13	1		T64	3
valid_sources[0x54]	945	1			T4	6		T42	4		T23	4
valid_sources[0x55]	1167	1			T4	2		T23	31		T96	1
valid_sources[0x56]	661	1			T3	3		T4	1		T23	3
valid_sources[0x57]	583	1			T3	2		T31	1		T130	2
valid_sources[0x58]	592	1			T4	1		T6	2		T23	14
valid_sources[0x59]	818	1			T4	3		T95	1		T64	10
valid_sources[0x5a]	996	1			T4	3		T6	7		T23	9
valid_sources[0x5b]	765	1			T4	1		T23	13		T64	8
valid_sources[0x5c]	650	1			T4	2		T23	9		T24	10
valid_sources[0x5d]	695	1			T23	20		T24	7		T64	17
valid_sources[0x5e]	845	1			T4	1		T6	3		T23	4
valid_sources[0x5f]	952	1			T3	1		T23	30		T24	2
valid_sources[0x60]	633	1			T2	1		T23	4		T24	1
valid_sources[0x61]	709	1			T3	1		T4	1		T23	11
valid_sources[0x62]	771	1			T4	4		T23	14		T7	1
valid_sources[0x63]	665	1			T4	2		T23	1		T24	2
valid_sources[0x64]	850	1			T4	1		T23	57		T64	25
valid_sources[0x65]	1199	1			T23	7		T24	7		T81	1
valid_sources[0x66]	691	1			T3	1		T6	4		T23	1
valid_sources[0x67]	760	1			T13	1		T23	1		T24	1
valid_sources[0x68]	841	1			T4	1		T23	21		T24	1
valid_sources[0x69]	889	1			T4	1		T6	5		T40	8
valid_sources[0x6a]	761	1			T4	8		T23	1		T24	5
valid_sources[0x6b]	842	1			T3	130		T6	5		T23	9
valid_sources[0x6c]	626	1			T5	1		T23	16		T24	10
valid_sources[0x6d]	651	1			T23	25		T24	3		T64	15
valid_sources[0x6e]	653	1			T4	2		T23	27		T24	6
valid_sources[0x6f]	993	1			T4	4		T23	25		T7	1
valid_sources[0x70]	834	1			T23	6		T24	1		T98	1
valid_sources[0x71]	719	1			T23	13		T24	5		T64	17
valid_sources[0x72]	826	1			T4	7		T6	1		T23	18
valid_sources[0x73]	1252	1			T3	2		T4	4		T38	5
valid_sources[0x74]	720	1			T3	1		T4	1		T6	1
valid_sources[0x75]	620	1			T3	2		T13	1		T6	2
valid_sources[0x76]	671	1			T4	5		T6	2		T23	15
valid_sources[0x77]	865	1			T1	2		T23	23		T24	2
valid_sources[0x78]	929	1			T24	6		T64	14		T17	1
valid_sources[0x79]	781	1			T3	1		T23	1		T24	10
valid_sources[0x7a]	774	1			T3	25		T6	2		T23	13
valid_sources[0x7b]	1278	1			T6	1		T23	6		T24	1
valid_sources[0x7c]	1199	1			T3	80		T4	1		T6	3
valid_sources[0x7d]	874	1			T3	4		T4	3		T64	3
valid_sources[0x7e]	901	1			T4	1		T23	26		T24	1
valid_sources[0x7f]	786	1			T4	2		T23	4		T7	1
valid_sources[0x80]	796	1			T4	5		T6	4		T23	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

42128

1

T3

305

T13

6

T6

37

values[0x0]

all_enables

biggest_size

58738

1

T2

1

T3

421

T4

60

values[0x1]

all_enables

biggest_size

55805

1

T3

411

T4

32

T13

5