Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15791165

1

T1

1544

T2

203

T3

1567

full_word

145790652

1

T1

325

T2

862

T3

2187

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	161581487	1			T1	1869		T2	1065		T3	3754
auto[TlIntgErrCmd]	107	1			T59	6		T60	10		T61	4
auto[TlIntgErrData]	120	1			T59	6		T60	7		T61	2
auto[TlIntgErrBoth]	103	1			T59	8		T60	3		T61	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

77887212

1

T1

953

T2

536

T3

884

auto[1]

83694605

1

T1

916

T2

529

T3

2870

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7740329	1			T1	785		T2	103		T3	314
auto[TlIntgErrNone]	partial	auto[1]	8050528	1			T1	759		T2	100		T3	1253
auto[TlIntgErrNone]	full_word	auto[0]	70146714	1			T1	168		T2	433		T3	570
auto[TlIntgErrNone]	full_word	auto[1]	75643916	1			T1	157		T2	429		T3	1617
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T59	5		T60	9		T120	1
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T59	1		T61	4		T121	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T122	1		T123	1		T124	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T60	1		T125	1		T126	1
auto[TlIntgErrData]	partial	auto[0]	55	1			T59	2		T60	4		T121	2
auto[TlIntgErrData]	partial	auto[1]	56	1			T59	4		T60	3		T61	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T122	1		T125	2		T127	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T121	1		T120	2		T128	1
auto[TlIntgErrBoth]	partial	auto[0]	53	1			T59	5		T60	1		T61	2
auto[TlIntgErrBoth]	partial	auto[1]	43	1			T59	2		T60	2		T61	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T61	1		T123	1		T129	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T59	1		T122	1		T125	1