Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1064378	1			T6	12300		T39	1820		T40	172
auto[1]	10689856	1			T1	14		T2	533		T5	15
auto[2]	829986	1			T6	9498		T39	1196		T40	72
auto[3]	10361165	1			T1	15		T2	528		T5	16

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14405555	1			T2	701		T5	27		T9	9817
auto[1]	2163512	1			T1	4		T2	157		T5	2
auto[2]	2184464	1			T1	6		T2	172		T5	1
auto[3]	4191854	1			T1	19		T2	31		T5	1

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9326429

1

T1

29

T2

1061

T5

31

auto[1]

13618956

1

T9

1

T6

1

T37

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	430514	1			T6	10129		T40	151		T23	2
auto[0]	auto[0]	auto[1]	44299	1			T6	1036		T39	17		T40	8
auto[0]	auto[0]	auto[2]	44770	1			T6	1035		T39	14		T40	11
auto[0]	auto[0]	auto[3]	77163	1			T6	100		T39	1789		T40	2
auto[0]	auto[1]	auto[0]	3257140	1			T2	358		T5	13		T9	4878
auto[0]	auto[1]	auto[1]	344545	1			T1	2		T2	72		T5	1
auto[0]	auto[1]	auto[2]	346090	1			T1	4		T2	87		T13	295
auto[0]	auto[1]	auto[3]	309689	1			T1	8		T2	16		T5	1
auto[0]	auto[2]	auto[0]	325376	1			T6	7997		T7	12		T8	11914
auto[0]	auto[2]	auto[1]	37311	1			T6	824		T7	1		T97	1
auto[0]	auto[2]	auto[2]	35601	1			T6	614		T39	10		T40	63
auto[0]	auto[2]	auto[3]	56161	1			T6	62		T39	1186		T40	9
auto[0]	auto[3]	auto[0]	3071709	1			T2	343		T5	14		T9	4938
auto[0]	auto[3]	auto[1]	323371	1			T1	2		T2	85		T5	1
auto[0]	auto[3]	auto[2]	345185	1			T1	2		T2	85		T5	1
auto[0]	auto[3]	auto[3]	277505	1			T1	11		T2	15		T13	14
auto[1]	auto[0]	auto[0]	15390	1			T38	594		T97	275		T8	3
auto[1]	auto[0]	auto[1]	69606	1			T38	2847		T97	1294		T103	5170
auto[1]	auto[0]	auto[2]	69317	1			T38	2800		T97	1203		T103	5083
auto[1]	auto[0]	auto[3]	313319	1			T38	12290		T97	5461		T135	1
auto[1]	auto[1]	auto[0]	3648850	1			T9	1		T37	1		T42	2
auto[1]	auto[1]	auto[1]	664739	1			T38	2662		T97	1451		T103	5177
auto[1]	auto[1]	auto[2]	636432	1			T38	492		T97	740		T28	1
auto[1]	auto[1]	auto[3]	1482371	1			T38	12184		T97	6204		T102	2
auto[1]	auto[2]	auto[0]	12345	1			T6	1		T38	543		T97	164
auto[1]	auto[2]	auto[1]	55598	1			T38	2458		T97	719		T103	4883
auto[1]	auto[2]	auto[2]	55581	1			T38	1877		T97	1271		T103	4449
auto[1]	auto[2]	auto[3]	252013	1			T38	8075		T97	5843		T103	19842
auto[1]	auto[3]	auto[0]	3644231	1			T42	1		T38	57		T97	66
auto[1]	auto[3]	auto[1]	624043	1			T38	256		T97	254		T136	1
auto[1]	auto[3]	auto[2]	651488	1			T38	1744		T97	1493		T103	4429
auto[1]	auto[3]	auto[3]	1423633	1			T38	8073		T97	6786		T103	19874