Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1072452058	227167	0	0
ctrl_regwen_rd_A	1072452058	3168	0	0
exec_rd_A	1072452058	2919	0	0
exec_regwen_rd_A	1072452058	3281	0	0
readback_rd_A	1072452058	2054	0	0
readback_regwen_rd_A	1072452058	2046	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1072452058	227167	0	0
T3	27670	1521	0	0
T4	206722	0	0	0
T5	40489	0	0	0
T6	523196	0	0	0
T9	77354	0	0	0
T10	34773	0	0	0
T11	34075	0	0	0
T12	33500	0	0	0
T13	334069	0	0	0
T23	0	5534	0	0
T24	0	1572	0	0
T35	139587	0	0	0
T52	0	6208	0	0
T64	0	3389	0	0
T65	0	5173	0	0
T66	0	2223	0	0
T67	0	1221	0	0
T68	0	1978	0	0
T69	0	2945	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1072452058	3168	0	0
T14	928	0	0	0
T21	884686	0	0	0
T22	118519	0	0	0
T64	71718	366	0	0
T67	0	60	0	0
T68	0	161	0	0
T70	378823	0	0	0
T71	115403	0	0	0
T87	96735	0	0	0
T109	0	103	0	0
T110	0	81	0	0
T111	0	166	0	0
T112	0	179	0	0
T113	0	300	0	0
T114	0	277	0	0
T115	0	57	0	0
T116	78156	0	0	0
T117	68231	0	0	0
T118	108205	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1072452058	2919	0	0
T14	928	0	0	0
T21	884686	0	0	0
T22	118519	0	0	0
T64	71718	263	0	0
T67	0	45	0	0
T68	0	111	0	0
T70	378823	0	0	0
T71	115403	0	0	0
T87	96735	0	0	0
T109	0	91	0	0
T110	0	120	0	0
T111	0	182	0	0
T112	0	166	0	0
T113	0	276	0	0
T114	0	306	0	0
T115	0	26	0	0
T116	78156	0	0	0
T117	68231	0	0	0
T118	108205	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1072452058	3281	0	0
T14	928	0	0	0
T21	884686	0	0	0
T22	118519	0	0	0
T64	71718	337	0	0
T67	0	61	0	0
T68	0	164	0	0
T70	378823	0	0	0
T71	115403	0	0	0
T87	96735	0	0	0
T109	0	127	0	0
T110	0	101	0	0
T111	0	147	0	0
T112	0	175	0	0
T113	0	300	0	0
T114	0	262	0	0
T115	0	75	0	0
T116	78156	0	0	0
T117	68231	0	0	0
T118	108205	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1072452058	2054	0	0
T14	928	0	0	0
T21	884686	0	0	0
T22	118519	0	0	0
T64	71718	228	0	0
T67	0	44	0	0
T68	0	131	0	0
T70	378823	0	0	0
T71	115403	0	0	0
T87	96735	0	0	0
T109	0	48	0	0
T110	0	116	0	0
T111	0	151	0	0
T112	0	171	0	0
T113	0	228	0	0
T114	0	302	0	0
T115	0	45	0	0
T116	78156	0	0	0
T117	68231	0	0	0
T118	108205	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1072452058	2046	0	0
T14	928	0	0	0
T21	884686	0	0	0
T22	118519	0	0	0
T64	71718	264	0	0
T67	0	45	0	0
T68	0	151	0	0
T70	378823	0	0	0
T71	115403	0	0	0
T87	96735	0	0	0
T109	0	62	0	0
T110	0	80	0	0
T111	0	109	0	0
T112	0	173	0	0
T113	0	228	0	0
T114	0	331	0	0
T115	0	21	0	0
T116	78156	0	0	0
T117	68231	0	0	0
T118	108205	0	0	0