Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16120353	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

153776258

1

T1

166260

T2

381

T3

163897

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	83580471	1			T1	91575		T2	1068		T3	89849
values[0x0]	41559189	1			T1	43879		T2	333		T3	43802
values[0x1]	44756951	1			T1	47384		T2	729		T3	46725

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8207695	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

161688916

1

T1

174484

T2

1305

T3

172204

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	617742	1			T1	699		T3	651		T4	6421
valid_sources[0x01]	526924	1			T1	566		T3	769		T4	6397
valid_sources[0x02]	632032	1			T1	490		T3	709		T4	6795
valid_sources[0x03]	2159159	1			T1	905		T3	753		T4	6619
valid_sources[0x04]	541931	1			T1	1126		T3	665		T4	6581
valid_sources[0x05]	570049	1			T1	895		T3	650		T4	6411
valid_sources[0x06]	2115117	1			T1	659		T3	797		T4	6501
valid_sources[0x07]	527282	1			T1	916		T3	680		T4	6258
valid_sources[0x08]	515097	1			T1	661		T3	672		T4	6242
valid_sources[0x09]	570483	1			T1	638		T3	689		T4	6360
valid_sources[0x0a]	547209	1			T1	878		T3	605		T4	6276
valid_sources[0x0b]	569122	1			T1	709		T3	734		T4	6259
valid_sources[0x0c]	571828	1			T1	666		T3	694		T4	6357
valid_sources[0x0d]	571806	1			T1	655		T3	715		T4	6326
valid_sources[0x0e]	728180	1			T1	548		T3	690		T4	6433
valid_sources[0x0f]	543437	1			T1	660		T3	681		T4	6448
valid_sources[0x10]	553914	1			T1	425		T3	641		T4	6360
valid_sources[0x11]	568187	1			T1	738		T3	863		T4	6825
valid_sources[0x12]	531502	1			T1	774		T3	763		T4	6078
valid_sources[0x13]	540947	1			T1	713		T3	666		T4	6799
valid_sources[0x14]	552292	1			T1	624		T3	785		T4	6505
valid_sources[0x15]	932031	1			T1	618		T3	649		T4	6386
valid_sources[0x16]	528750	1			T1	837		T3	639		T4	6087
valid_sources[0x17]	636161	1			T1	642		T3	795		T4	6441
valid_sources[0x18]	572948	1			T1	567		T3	652		T4	6331
valid_sources[0x19]	620815	1			T1	588		T3	820		T4	6606
valid_sources[0x1a]	567858	1			T1	772		T3	777		T4	6550
valid_sources[0x1b]	540905	1			T1	568		T3	727		T4	6302
valid_sources[0x1c]	1580206	1			T1	889		T3	671		T4	6634
valid_sources[0x1d]	548562	1			T1	860		T3	738		T4	6307
valid_sources[0x1e]	1792848	1			T1	730		T3	774		T4	6504
valid_sources[0x1f]	535073	1			T1	521		T3	706		T4	6375
valid_sources[0x20]	1841564	1			T1	806		T3	749		T4	6636
valid_sources[0x21]	520373	1			T1	571		T3	702		T4	6428
valid_sources[0x22]	608007	1			T1	666		T3	667		T4	6432
valid_sources[0x23]	538314	1			T1	635		T3	735		T4	6570
valid_sources[0x24]	548278	1			T1	968		T3	538		T4	6510
valid_sources[0x25]	625533	1			T1	702		T3	743		T4	6356
valid_sources[0x26]	556015	1			T1	669		T3	682		T4	6143
valid_sources[0x27]	2250867	1			T1	541		T3	705		T4	6230
valid_sources[0x28]	536607	1			T1	560		T3	684		T4	6444
valid_sources[0x29]	572587	1			T1	697		T3	747		T4	6423
valid_sources[0x2a]	541050	1			T1	804		T3	635		T4	6497
valid_sources[0x2b]	584825	1			T1	676		T3	832		T4	6445
valid_sources[0x2c]	525713	1			T1	903		T3	786		T4	6601
valid_sources[0x2d]	723509	1			T1	841		T3	609		T4	6374
valid_sources[0x2e]	520472	1			T1	949		T3	723		T4	6790
valid_sources[0x2f]	542970	1			T1	797		T3	865		T4	6609
valid_sources[0x30]	569712	1			T1	732		T3	595		T4	6193
valid_sources[0x31]	642999	1			T1	456		T3	658		T4	6086
valid_sources[0x32]	549896	1			T1	1084		T3	722		T4	6456
valid_sources[0x33]	571099	1			T1	744		T3	753		T4	6395
valid_sources[0x34]	553572	1			T1	558		T3	611		T4	6717
valid_sources[0x35]	551207	1			T1	778		T3	652		T4	6283
valid_sources[0x36]	635328	1			T1	784		T3	704		T4	6378
valid_sources[0x37]	531864	1			T1	678		T3	652		T4	6326
valid_sources[0x38]	558157	1			T1	692		T3	628		T4	6303
valid_sources[0x39]	520549	1			T1	803		T3	551		T4	6774
valid_sources[0x3a]	558823	1			T1	890		T3	624		T4	6427
valid_sources[0x3b]	519876	1			T1	645		T3	634		T4	6618
valid_sources[0x3c]	559964	1			T1	728		T3	743		T4	6613
valid_sources[0x3d]	564443	1			T1	480		T3	726		T4	6197
valid_sources[0x3e]	1381280	1			T1	872		T3	680		T4	6176
valid_sources[0x3f]	544099	1			T1	766		T3	667		T4	6561
valid_sources[0x40]	520450	1			T1	481		T3	744		T4	6596
valid_sources[0x41]	629311	1			T1	596		T3	675		T4	6451
valid_sources[0x42]	555923	1			T1	781		T3	709		T4	6449
valid_sources[0x43]	772218	1			T1	865		T3	646		T4	6494
valid_sources[0x44]	1937862	1			T1	817		T3	697		T4	6625
valid_sources[0x45]	628549	1			T1	676		T3	721		T4	6393
valid_sources[0x46]	536854	1			T1	702		T3	544		T4	6355
valid_sources[0x47]	572221	1			T1	431		T3	677		T4	6080
valid_sources[0x48]	571724	1			T1	778		T3	692		T4	6374
valid_sources[0x49]	588852	1			T1	779		T3	613		T4	6622
valid_sources[0x4a]	1503085	1			T1	764		T3	758		T4	6566
valid_sources[0x4b]	519994	1			T1	560		T3	716		T4	6183
valid_sources[0x4c]	574407	1			T1	580		T3	767		T4	6730
valid_sources[0x4d]	525882	1			T1	570		T3	613		T4	6279
valid_sources[0x4e]	562338	1			T1	722		T3	699		T4	6260
valid_sources[0x4f]	549789	1			T1	422		T3	755		T4	6678
valid_sources[0x50]	516742	1			T1	945		T3	652		T4	6516
valid_sources[0x51]	607410	1			T1	712		T3	702		T4	6431
valid_sources[0x52]	518072	1			T1	863		T3	897		T4	6335
valid_sources[0x53]	548729	1			T1	723		T3	672		T4	6495
valid_sources[0x54]	565957	1			T1	727		T3	678		T4	6709
valid_sources[0x55]	554694	1			T1	558		T3	678		T4	6555
valid_sources[0x56]	558532	1			T1	594		T3	735		T4	6552
valid_sources[0x57]	527702	1			T1	594		T3	694		T4	6704
valid_sources[0x58]	566306	1			T1	830		T3	719		T4	6137
valid_sources[0x59]	549352	1			T1	604		T3	698		T4	6547
valid_sources[0x5a]	1462765	1			T1	681		T3	582		T4	6283
valid_sources[0x5b]	559846	1			T1	718		T3	696		T4	6604
valid_sources[0x5c]	549211	1			T1	780		T3	695		T4	6141
valid_sources[0x5d]	519027	1			T1	805		T3	647		T4	6236
valid_sources[0x5e]	594145	1			T1	703		T3	682		T4	6378
valid_sources[0x5f]	571234	1			T1	832		T3	642		T4	6276
valid_sources[0x60]	531918	1			T1	763		T3	622		T4	6178
valid_sources[0x61]	683702	1			T1	804		T3	720		T4	6511
valid_sources[0x62]	532544	1			T1	646		T3	726		T4	6498
valid_sources[0x63]	594655	1			T1	526		T3	768		T4	6426
valid_sources[0x64]	1622154	1			T1	551		T3	599		T4	6623
valid_sources[0x65]	554597	1			T1	769		T2	2130		T3	783
valid_sources[0x66]	590489	1			T1	702		T3	756		T4	6258
valid_sources[0x67]	562172	1			T1	847		T3	719		T4	6530
valid_sources[0x68]	565844	1			T1	476		T3	745		T4	6043
valid_sources[0x69]	563081	1			T1	625		T3	667		T4	6511
valid_sources[0x6a]	728980	1			T1	800		T3	665		T4	6566
valid_sources[0x6b]	556441	1			T1	562		T3	702		T4	6251
valid_sources[0x6c]	553566	1			T1	685		T3	753		T4	6150
valid_sources[0x6d]	545757	1			T1	466		T3	727		T4	6175
valid_sources[0x6e]	559483	1			T1	613		T3	658		T4	6176
valid_sources[0x6f]	531585	1			T1	539		T3	779		T4	6446
valid_sources[0x70]	530292	1			T1	675		T3	723		T4	6086
valid_sources[0x71]	524472	1			T1	786		T3	677		T4	6579
valid_sources[0x72]	1573744	1			T1	803		T3	673		T4	6419
valid_sources[0x73]	2122235	1			T1	520		T3	674		T4	5933
valid_sources[0x74]	1428718	1			T1	1008		T3	667		T4	6280
valid_sources[0x75]	531905	1			T1	674		T3	682		T4	6153
valid_sources[0x76]	522502	1			T1	972		T3	653		T4	6279
valid_sources[0x77]	523066	1			T1	781		T3	723		T4	6223
valid_sources[0x78]	574488	1			T1	784		T3	589		T4	6460
valid_sources[0x79]	535280	1			T1	442		T3	834		T4	6671
valid_sources[0x7a]	553945	1			T1	741		T3	770		T4	6123
valid_sources[0x7b]	2027490	1			T1	909		T3	665		T4	6552
valid_sources[0x7c]	521704	1			T1	667		T3	778		T4	6524
valid_sources[0x7d]	561709	1			T1	734		T3	767		T4	6508
valid_sources[0x7e]	517146	1			T1	480		T3	638		T4	6315
valid_sources[0x7f]	554423	1			T1	651		T3	830		T4	6458
valid_sources[0x80]	529217	1			T1	767		T3	668		T4	6370

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

75476940

1

T1

83225

T2

188

T3

81600

values[0x0]

all_enables

biggest_size

39152854

1

T1

41400

T2

84

T3

41301

values[0x1]

all_enables

biggest_size

39146464

1

T1

41635

T2

109

T3

40996

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44951	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

156274

1

T1

2

T2

1

T3

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	55319	1			T5	41		T6	29		T11	528
values[0x0]	70202	1			T1	7		T2	1		T3	24
values[0x1]	75704	1			T1	4		T2	1		T3	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34464	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

166761

1

T1

2

T2

1

T3

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	823	1			T11	2		T24	10		T25	13
valid_sources[0x01]	796	1			T4	1		T24	13		T19	1
valid_sources[0x02]	557	1			T7	1		T24	6		T22	3
valid_sources[0x03]	802	1			T24	9		T59	1		T148	1
valid_sources[0x04]	1078	1			T24	8		T105	1		T23	2
valid_sources[0x05]	758	1			T11	1		T24	16		T25	13
valid_sources[0x06]	660	1			T11	1		T24	10		T19	2
valid_sources[0x07]	666	1			T11	2		T24	11		T25	12
valid_sources[0x08]	789	1			T7	2		T24	16		T60	1
valid_sources[0x09]	1238	1			T11	117		T24	10		T149	1
valid_sources[0x0a]	693	1			T7	4		T24	9		T23	1
valid_sources[0x0b]	584	1			T11	1		T24	10		T19	2
valid_sources[0x0c]	720	1			T11	2		T24	4		T25	14
valid_sources[0x0d]	747	1			T4	2		T24	14		T23	3
valid_sources[0x0e]	584	1			T24	16		T25	34		T69	1
valid_sources[0x0f]	502	1			T40	1		T24	14		T42	1
valid_sources[0x10]	934	1			T7	1		T24	18		T150	1
valid_sources[0x11]	1005	1			T4	1		T5	12		T24	12
valid_sources[0x12]	660	1			T7	1		T24	9		T149	1
valid_sources[0x13]	1081	1			T7	5		T24	7		T148	1
valid_sources[0x14]	746	1			T7	1		T24	10		T151	1
valid_sources[0x15]	664	1			T24	8		T42	1		T25	12
valid_sources[0x16]	741	1			T11	5		T24	8		T19	1
valid_sources[0x17]	807	1			T24	6		T19	2		T59	2
valid_sources[0x18]	534	1			T24	7		T19	1		T25	20
valid_sources[0x19]	744	1			T11	9		T7	1		T24	11
valid_sources[0x1a]	689	1			T5	5		T24	9		T13	2
valid_sources[0x1b]	632	1			T4	2		T5	5		T24	8
valid_sources[0x1c]	483	1			T24	8		T152	2		T25	14
valid_sources[0x1d]	653	1			T7	1		T24	13		T22	1
valid_sources[0x1e]	634	1			T7	1		T24	12		T25	19
valid_sources[0x1f]	607	1			T6	11		T11	3		T24	7
valid_sources[0x20]	1072	1			T7	1		T24	13		T22	5
valid_sources[0x21]	894	1			T11	1		T24	11		T25	16
valid_sources[0x22]	514	1			T24	11		T59	1		T135	5
valid_sources[0x23]	666	1			T11	2		T7	1		T24	10
valid_sources[0x24]	576	1			T24	11		T153	2		T23	1
valid_sources[0x25]	914	1			T11	80		T24	15		T59	2
valid_sources[0x26]	1077	1			T24	7		T19	1		T22	1
valid_sources[0x27]	839	1			T24	5		T25	13		T50	3
valid_sources[0x28]	799	1			T52	1		T24	10		T19	1
valid_sources[0x29]	1139	1			T6	1		T24	11		T154	2
valid_sources[0x2a]	661	1			T11	5		T7	1		T24	7
valid_sources[0x2b]	696	1			T24	3		T25	8		T50	6
valid_sources[0x2c]	787	1			T3	36		T7	1		T24	9
valid_sources[0x2d]	1064	1			T7	2		T24	10		T19	1
valid_sources[0x2e]	597	1			T7	1		T24	13		T42	1
valid_sources[0x2f]	793	1			T24	15		T25	9		T20	1
valid_sources[0x30]	773	1			T4	1		T7	3		T24	5
valid_sources[0x31]	652	1			T11	2		T40	1		T41	1
valid_sources[0x32]	681	1			T7	1		T24	14		T25	21
valid_sources[0x33]	722	1			T11	1		T24	13		T23	3
valid_sources[0x34]	822	1			T11	2		T24	7		T46	69
valid_sources[0x35]	947	1			T5	1		T24	11		T42	1
valid_sources[0x36]	653	1			T24	11		T23	1		T149	1
valid_sources[0x37]	670	1			T7	1		T24	2		T59	1
valid_sources[0x38]	834	1			T4	2		T11	5		T24	7
valid_sources[0x39]	552	1			T8	4		T11	2		T24	15
valid_sources[0x3a]	775	1			T24	13		T25	18		T50	1
valid_sources[0x3b]	707	1			T6	1		T40	1		T7	6
valid_sources[0x3c]	754	1			T7	1		T24	19		T152	1
valid_sources[0x3d]	865	1			T5	2		T24	13		T60	1
valid_sources[0x3e]	984	1			T11	131		T24	12		T22	2
valid_sources[0x3f]	940	1			T11	6		T40	4		T24	16
valid_sources[0x40]	636	1			T11	1		T7	3		T24	7
valid_sources[0x41]	574	1			T11	1		T24	8		T42	1
valid_sources[0x42]	906	1			T11	78		T24	9		T19	1
valid_sources[0x43]	909	1			T24	13		T25	24		T89	1
valid_sources[0x44]	958	1			T24	3		T19	1		T25	29
valid_sources[0x45]	890	1			T24	7		T25	25		T136	1
valid_sources[0x46]	871	1			T11	1		T24	8		T22	7
valid_sources[0x47]	869	1			T7	2		T24	12		T19	1
valid_sources[0x48]	942	1			T7	2		T24	19		T42	2
valid_sources[0x49]	848	1			T11	1		T24	11		T19	1
valid_sources[0x4a]	618	1			T5	2		T24	11		T25	8
valid_sources[0x4b]	877	1			T11	1		T24	8		T149	1
valid_sources[0x4c]	1019	1			T6	7		T24	12		T112	1
valid_sources[0x4d]	792	1			T24	10		T19	1		T25	16
valid_sources[0x4e]	976	1			T10	9		T24	5		T19	1
valid_sources[0x4f]	747	1			T24	10		T25	11		T136	1
valid_sources[0x50]	544	1			T1	11		T24	9		T42	1
valid_sources[0x51]	1123	1			T4	1		T11	55		T40	1
valid_sources[0x52]	677	1			T11	2		T7	2		T24	9
valid_sources[0x53]	862	1			T24	6		T22	3		T60	1
valid_sources[0x54]	667	1			T7	3		T24	18		T25	15
valid_sources[0x55]	795	1			T7	13		T24	8		T25	8
valid_sources[0x56]	804	1			T9	32		T24	10		T25	11
valid_sources[0x57]	824	1			T24	11		T25	11		T69	28
valid_sources[0x58]	919	1			T11	4		T24	10		T19	1
valid_sources[0x59]	819	1			T4	2		T24	12		T153	1
valid_sources[0x5a]	710	1			T5	1		T6	6		T7	4
valid_sources[0x5b]	771	1			T11	190		T7	1		T24	2
valid_sources[0x5c]	666	1			T11	1		T24	14		T19	1
valid_sources[0x5d]	732	1			T7	1		T24	8		T153	1
valid_sources[0x5e]	905	1			T24	9		T149	1		T25	17
valid_sources[0x5f]	706	1			T7	2		T24	5		T23	2
valid_sources[0x60]	879	1			T40	1		T7	1		T24	7
valid_sources[0x61]	616	1			T5	1		T24	12		T23	1
valid_sources[0x62]	620	1			T5	14		T40	1		T24	9
valid_sources[0x63]	597	1			T24	5		T149	3		T25	32
valid_sources[0x64]	735	1			T24	9		T106	1		T111	1
valid_sources[0x65]	1181	1			T7	1		T24	7		T25	8
valid_sources[0x66]	698	1			T24	6		T60	1		T111	1
valid_sources[0x67]	572	1			T5	2		T24	11		T42	2
valid_sources[0x68]	672	1			T7	3		T24	10		T19	1
valid_sources[0x69]	1300	1			T11	1		T7	3		T24	12
valid_sources[0x6a]	940	1			T24	13		T23	1		T25	20
valid_sources[0x6b]	869	1			T24	10		T23	1		T25	17
valid_sources[0x6c]	557	1			T7	1		T24	11		T135	1
valid_sources[0x6d]	808	1			T6	2		T11	2		T24	6
valid_sources[0x6e]	530	1			T24	7		T19	1		T109	1
valid_sources[0x6f]	1121	1			T11	1		T52	1		T24	8
valid_sources[0x70]	589	1			T11	1		T24	13		T153	3
valid_sources[0x71]	959	1			T11	1		T24	7		T19	1
valid_sources[0x72]	787	1			T5	7		T24	9		T60	1
valid_sources[0x73]	702	1			T40	1		T24	4		T19	1
valid_sources[0x74]	804	1			T6	3		T24	12		T19	1
valid_sources[0x75]	916	1			T24	9		T109	2		T25	13
valid_sources[0x76]	928	1			T24	13		T12	11		T148	1
valid_sources[0x77]	785	1			T24	16		T25	16		T50	128
valid_sources[0x78]	758	1			T7	1		T24	21		T152	2
valid_sources[0x79]	610	1			T5	4		T11	2		T24	17
valid_sources[0x7a]	694	1			T11	3		T24	3		T19	1
valid_sources[0x7b]	789	1			T24	9		T25	22		T89	1
valid_sources[0x7c]	848	1			T24	9		T28	1		T88	3
valid_sources[0x7d]	875	1			T24	15		T153	1		T25	21
valid_sources[0x7e]	640	1			T11	2		T7	1		T24	8
valid_sources[0x7f]	700	1			T24	9		T42	2		T149	3
valid_sources[0x80]	624	1			T24	16		T42	1		T19	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

41894

1

T5

18

T6

18

T11

483

values[0x0]

all_enables

biggest_size

58562

1

T1

2

T2

1

T3

8

values[0x1]

all_enables

biggest_size

55818

1

T3

1

T4

1

T8

3