Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16042248

1

T1

16578

T2

1749

T3

16479

full_word

150711841

1

T1

166260

T2

381

T3

163897

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	166753799	1			T1	182838		T2	2130		T3	180376
auto[TlIntgErrCmd]	99	1			T62	3		T63	4		T64	3
auto[TlIntgErrData]	98	1			T62	5		T63	2		T64	1
auto[TlIntgErrBoth]	93	1			T62	2		T63	4		T64	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

80345171

1

T1

91575

T2

1068

T3

89849

auto[1]

86408918

1

T1

91263

T2

1062

T3

90527

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7851917	1			T1	8350		T2	880		T3	8249
auto[TlIntgErrNone]	partial	auto[1]	8190074	1			T1	8228		T2	869		T3	8230
auto[TlIntgErrNone]	full_word	auto[0]	72493132	1			T1	83225		T2	188		T3	81600
auto[TlIntgErrNone]	full_word	auto[1]	78218676	1			T1	83035		T2	193		T3	82297
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T62	2		T63	1		T64	1
auto[TlIntgErrCmd]	partial	auto[1]	49	1			T62	1		T63	3		T64	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T120	1		T126	1		T123	1
auto[TlIntgErrCmd]	full_word	auto[1]	11	1			T64	1		T130	1		T125	2
auto[TlIntgErrData]	partial	auto[0]	36	1			T62	3		T120	2		T128	3
auto[TlIntgErrData]	partial	auto[1]	50	1			T62	2		T63	1		T64	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T130	1		T125	1		T122	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T63	1		T121	1		T125	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T62	1		T63	2		T64	2
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T62	1		T63	1		T64	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T63	1		T131	1		T132	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T122	1		T127	2		-	-