Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	927098	1			T10	3		T6	21		T7	6703
auto[1]	10718919	1			T1	23019		T3	37332		T5	600
auto[2]	706117	1			T10	5		T6	16		T7	3762
auto[3]	10414982	1			T1	22945		T3	37796		T5	605

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14263669	1			T1	38175		T3	62728		T5	1007
auto[1]	2102730	1			T1	3766		T3	5873		T5	98
auto[2]	2153409	1			T1	3665		T3	5992		T5	93
auto[3]	4247308	1			T1	358		T3	535		T5	7

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9319500

1

T1

45962

T3

75125

T5

1205

auto[1]

13447616

1

T1

2

T3

3

T9

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	337406	1			T10	2		T6	17		T7	5537
auto[0]	auto[0]	auto[1]	35220	1			T6	1		T7	554		T24	27
auto[0]	auto[0]	auto[2]	35160	1			T10	1		T6	3		T7	544
auto[0]	auto[0]	auto[3]	56437	1			T7	68		T24	2		T58	4169
auto[0]	auto[1]	auto[0]	3226967	1			T1	19090		T3	31131		T5	504
auto[0]	auto[1]	auto[1]	338422	1			T1	1821		T3	2747		T5	46
auto[0]	auto[1]	auto[2]	361013	1			T1	1926		T3	3194		T5	45
auto[0]	auto[1]	auto[3]	445093	1			T1	182		T3	258		T5	5
auto[0]	auto[2]	auto[0]	232604	1			T6	14		T7	2909		T24	155
auto[0]	auto[2]	auto[1]	27598	1			T6	1		T7	288		T24	15
auto[0]	auto[2]	auto[2]	29305	1			T10	4		T6	1		T7	523
auto[0]	auto[2]	auto[3]	39600	1			T10	1		T7	42		T24	4
auto[0]	auto[3]	auto[0]	3055033	1			T1	19084		T3	31594		T5	503
auto[0]	auto[3]	auto[1]	339555	1			T1	1945		T3	3126		T5	52
auto[0]	auto[3]	auto[2]	355281	1			T1	1738		T3	2798		T5	48
auto[0]	auto[3]	auto[3]	404806	1			T1	176		T3	277		T5	2
auto[1]	auto[0]	auto[0]	15263	1			T105	171		T111	100		T145	487
auto[1]	auto[0]	auto[1]	68728	1			T105	681		T76	1		T111	470
auto[1]	auto[0]	auto[2]	68799	1			T105	656		T111	482		T145	2170
auto[1]	auto[0]	auto[3]	310085	1			T58	2		T105	3025		T111	2137
auto[1]	auto[1]	auto[0]	3694930	1			T3	2		T40	1		T41	66625
auto[1]	auto[1]	auto[1]	648329	1			T40	1		T41	6132		T52	1
auto[1]	auto[1]	auto[2]	611004	1			T40	1		T41	6534		T52	1
auto[1]	auto[1]	auto[3]	1393161	1			T41	574		T105	10281		T106	957
auto[1]	auto[2]	auto[0]	11459	1			T76	2		T145	282		T146	833
auto[1]	auto[2]	auto[1]	52262	1			T145	1355		T146	3835		T147	696
auto[1]	auto[2]	auto[2]	56877	1			T105	587		T111	428		T145	2072
auto[1]	auto[2]	auto[3]	256412	1			T105	2677		T111	1994		T145	9288
auto[1]	auto[3]	auto[0]	3690007	1			T1	1		T3	1		T41	66952
auto[1]	auto[3]	auto[1]	592616	1			T41	6599		T52	1		T105	558
auto[1]	auto[3]	auto[2]	635970	1			T1	1		T9	1		T40	1
auto[1]	auto[3]	auto[3]	1341714	1			T41	588		T105	10048		T106	940