Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1127257363	233083	0	0
ctrl_regwen_rd_A	1127257363	4287	0	0
exec_rd_A	1127257363	4164	0	0
exec_regwen_rd_A	1127257363	4537	0	0
readback_rd_A	1127257363	2394	0	0
readback_regwen_rd_A	1127257363	1835	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127257363	233083	0	0
T7	178654	0	0	0
T11	94878	3569	0	0
T24	168552	4031	0	0
T25	0	6746	0	0
T26	324832	0	0	0
T40	129545	0	0	0
T41	357373	0	0	0
T42	130132	0	0	0
T43	502363	0	0	0
T50	0	6584	0	0
T52	102202	0	0	0
T58	267439	0	0	0
T69	0	3843	0	0
T70	0	3570	0	0
T71	0	637	0	0
T72	0	1196	0	0
T73	0	899	0	0
T74	0	996	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127257363	4287	0	0
T7	178654	0	0	0
T11	94878	239	0	0
T24	168552	0	0	0
T26	324832	0	0	0
T40	129545	0	0	0
T41	357373	0	0	0
T42	130132	0	0	0
T43	502363	0	0	0
T44	0	275	0	0
T52	102202	0	0	0
T58	267439	0	0	0
T71	0	100	0	0
T72	0	78	0	0
T114	0	396	0	0
T115	0	130	0	0
T116	0	278	0	0
T117	0	310	0	0
T118	0	134	0	0
T119	0	377	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127257363	4164	0	0
T7	178654	0	0	0
T11	94878	279	0	0
T24	168552	0	0	0
T26	324832	0	0	0
T40	129545	0	0	0
T41	357373	0	0	0
T42	130132	0	0	0
T43	502363	0	0	0
T44	0	281	0	0
T52	102202	0	0	0
T58	267439	0	0	0
T71	0	68	0	0
T72	0	31	0	0
T114	0	392	0	0
T115	0	92	0	0
T116	0	240	0	0
T117	0	326	0	0
T118	0	136	0	0
T119	0	294	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127257363	4537	0	0
T7	178654	0	0	0
T11	94878	212	0	0
T24	168552	0	0	0
T26	324832	0	0	0
T40	129545	0	0	0
T41	357373	0	0	0
T42	130132	0	0	0
T43	502363	0	0	0
T44	0	279	0	0
T52	102202	0	0	0
T58	267439	0	0	0
T71	0	83	0	0
T72	0	64	0	0
T114	0	376	0	0
T115	0	106	0	0
T116	0	379	0	0
T117	0	317	0	0
T118	0	112	0	0
T119	0	486	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127257363	2394	0	0
T7	178654	0	0	0
T11	94878	246	0	0
T24	168552	0	0	0
T26	324832	0	0	0
T40	129545	0	0	0
T41	357373	0	0	0
T42	130132	0	0	0
T43	502363	0	0	0
T44	0	325	0	0
T52	102202	0	0	0
T58	267439	0	0	0
T71	0	38	0	0
T72	0	36	0	0
T114	0	397	0	0
T115	0	102	0	0
T116	0	267	0	0
T117	0	282	0	0
T118	0	83	0	0
T119	0	276	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127257363	1835	0	0
T7	178654	0	0	0
T11	94878	140	0	0
T24	168552	0	0	0
T26	324832	0	0	0
T40	129545	0	0	0
T41	357373	0	0	0
T42	130132	0	0	0
T43	502363	0	0	0
T44	0	146	0	0
T52	102202	0	0	0
T58	267439	0	0	0
T71	0	35	0	0
T72	0	26	0	0
T114	0	294	0	0
T115	0	104	0	0
T116	0	269	0	0
T117	0	231	0	0
T118	0	91	0	0
T119	0	217	0	0