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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44


Total test records in report: 1031
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T797 /workspace/coverage/default/0.sram_ctrl_mem_partial_access.3190746424 Jul 02 10:00:06 AM PDT 24 Jul 02 10:03:07 AM PDT 24 18570097340 ps
T798 /workspace/coverage/default/33.sram_ctrl_ram_cfg.3571821264 Jul 02 10:01:45 AM PDT 24 Jul 02 10:01:50 AM PDT 24 2092373882 ps
T799 /workspace/coverage/default/4.sram_ctrl_regwen.2090274969 Jul 02 10:00:00 AM PDT 24 Jul 02 10:02:55 AM PDT 24 1028979995 ps
T800 /workspace/coverage/default/32.sram_ctrl_max_throughput.4187966301 Jul 02 10:01:36 AM PDT 24 Jul 02 10:03:47 AM PDT 24 1520497484 ps
T801 /workspace/coverage/default/45.sram_ctrl_mem_partial_access.1059479064 Jul 02 10:03:26 AM PDT 24 Jul 02 10:05:43 AM PDT 24 6843576485 ps
T802 /workspace/coverage/default/37.sram_ctrl_mem_walk.2558651035 Jul 02 10:02:25 AM PDT 24 Jul 02 10:07:29 AM PDT 24 5260693285 ps
T803 /workspace/coverage/default/27.sram_ctrl_alert_test.3602428519 Jul 02 10:01:12 AM PDT 24 Jul 02 10:01:14 AM PDT 24 30087041 ps
T804 /workspace/coverage/default/26.sram_ctrl_alert_test.1237764101 Jul 02 10:01:06 AM PDT 24 Jul 02 10:01:08 AM PDT 24 15025601 ps
T805 /workspace/coverage/default/8.sram_ctrl_smoke.2445481054 Jul 02 10:00:22 AM PDT 24 Jul 02 10:00:29 AM PDT 24 2082456942 ps
T806 /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3149039724 Jul 02 10:00:56 AM PDT 24 Jul 02 10:03:53 AM PDT 24 2200604839 ps
T807 /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.637109613 Jul 02 10:00:27 AM PDT 24 Jul 02 10:01:37 AM PDT 24 3624008965 ps
T808 /workspace/coverage/default/4.sram_ctrl_mem_partial_access.3471048134 Jul 02 10:00:11 AM PDT 24 Jul 02 10:01:43 AM PDT 24 7890926353 ps
T809 /workspace/coverage/default/7.sram_ctrl_alert_test.3592188365 Jul 02 10:00:05 AM PDT 24 Jul 02 10:00:11 AM PDT 24 57841896 ps
T810 /workspace/coverage/default/2.sram_ctrl_stress_pipeline.2206374807 Jul 02 10:00:04 AM PDT 24 Jul 02 10:03:59 AM PDT 24 34762803209 ps
T811 /workspace/coverage/default/37.sram_ctrl_access_during_key_req.3171723289 Jul 02 10:02:16 AM PDT 24 Jul 02 10:32:49 AM PDT 24 16451305251 ps
T812 /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3658133294 Jul 02 10:04:01 AM PDT 24 Jul 02 10:07:31 AM PDT 24 31545265700 ps
T813 /workspace/coverage/default/23.sram_ctrl_multiple_keys.893102856 Jul 02 10:00:56 AM PDT 24 Jul 02 10:03:10 AM PDT 24 3279130299 ps
T814 /workspace/coverage/default/35.sram_ctrl_partial_access.621668207 Jul 02 10:01:57 AM PDT 24 Jul 02 10:02:04 AM PDT 24 779006237 ps
T815 /workspace/coverage/default/16.sram_ctrl_mem_partial_access.952939310 Jul 02 10:00:37 AM PDT 24 Jul 02 10:02:50 AM PDT 24 6355323328 ps
T816 /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3430847042 Jul 02 10:03:17 AM PDT 24 Jul 02 10:04:39 AM PDT 24 1334711329 ps
T817 /workspace/coverage/default/35.sram_ctrl_stress_pipeline.4090643277 Jul 02 10:01:58 AM PDT 24 Jul 02 10:06:17 AM PDT 24 40593022073 ps
T818 /workspace/coverage/default/40.sram_ctrl_smoke.1260466123 Jul 02 10:02:38 AM PDT 24 Jul 02 10:02:47 AM PDT 24 470817734 ps
T819 /workspace/coverage/default/47.sram_ctrl_multiple_keys.2171676796 Jul 02 10:03:41 AM PDT 24 Jul 02 10:19:26 AM PDT 24 32341610960 ps
T820 /workspace/coverage/default/44.sram_ctrl_mem_partial_access.3165794732 Jul 02 10:03:19 AM PDT 24 Jul 02 10:06:08 AM PDT 24 5244350934 ps
T821 /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.1984953924 Jul 02 10:01:15 AM PDT 24 Jul 02 10:01:28 AM PDT 24 728541185 ps
T822 /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.2487154989 Jul 02 10:02:35 AM PDT 24 Jul 02 10:05:24 AM PDT 24 1536823268 ps
T823 /workspace/coverage/default/17.sram_ctrl_bijection.2931232171 Jul 02 10:00:51 AM PDT 24 Jul 02 10:44:19 AM PDT 24 211693149356 ps
T824 /workspace/coverage/default/47.sram_ctrl_access_during_key_req.2529458164 Jul 02 10:03:46 AM PDT 24 Jul 02 10:07:21 AM PDT 24 4655823743 ps
T825 /workspace/coverage/default/16.sram_ctrl_executable.581801194 Jul 02 10:00:51 AM PDT 24 Jul 02 10:14:56 AM PDT 24 38239796318 ps
T826 /workspace/coverage/default/19.sram_ctrl_mem_walk.3534600841 Jul 02 10:00:56 AM PDT 24 Jul 02 10:03:38 AM PDT 24 6982338258 ps
T827 /workspace/coverage/default/0.sram_ctrl_smoke.1895989600 Jul 02 10:00:07 AM PDT 24 Jul 02 10:00:39 AM PDT 24 1782284417 ps
T828 /workspace/coverage/default/47.sram_ctrl_bijection.3117344238 Jul 02 10:03:40 AM PDT 24 Jul 02 10:12:36 AM PDT 24 23282130268 ps
T829 /workspace/coverage/default/20.sram_ctrl_mem_walk.3529338443 Jul 02 10:00:48 AM PDT 24 Jul 02 10:05:13 AM PDT 24 3943419236 ps
T830 /workspace/coverage/default/5.sram_ctrl_partial_access.2575044711 Jul 02 09:59:58 AM PDT 24 Jul 02 10:00:32 AM PDT 24 663624522 ps
T831 /workspace/coverage/default/32.sram_ctrl_access_during_key_req.3612363926 Jul 02 10:01:37 AM PDT 24 Jul 02 10:20:22 AM PDT 24 28689532308 ps
T118 /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3379217584 Jul 02 10:00:33 AM PDT 24 Jul 02 10:00:41 AM PDT 24 525872742 ps
T832 /workspace/coverage/default/28.sram_ctrl_max_throughput.373155488 Jul 02 10:01:14 AM PDT 24 Jul 02 10:02:32 AM PDT 24 2961773671 ps
T833 /workspace/coverage/default/21.sram_ctrl_lc_escalation.3119670586 Jul 02 10:01:01 AM PDT 24 Jul 02 10:01:50 AM PDT 24 41897857171 ps
T834 /workspace/coverage/default/4.sram_ctrl_multiple_keys.899249694 Jul 02 10:00:08 AM PDT 24 Jul 02 10:06:39 AM PDT 24 3650440308 ps
T835 /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1273760295 Jul 02 10:03:10 AM PDT 24 Jul 02 10:10:04 AM PDT 24 15919643114 ps
T836 /workspace/coverage/default/17.sram_ctrl_partial_access.464350809 Jul 02 10:00:50 AM PDT 24 Jul 02 10:00:59 AM PDT 24 407684296 ps
T837 /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.1705780651 Jul 02 10:02:04 AM PDT 24 Jul 02 10:02:15 AM PDT 24 1133336671 ps
T838 /workspace/coverage/default/28.sram_ctrl_stress_all.2454766587 Jul 02 10:01:16 AM PDT 24 Jul 02 10:22:13 AM PDT 24 185920452977 ps
T839 /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.2100325985 Jul 02 10:01:28 AM PDT 24 Jul 02 10:02:01 AM PDT 24 758525690 ps
T840 /workspace/coverage/default/12.sram_ctrl_mem_walk.3709908255 Jul 02 10:00:36 AM PDT 24 Jul 02 10:03:24 AM PDT 24 10330175478 ps
T841 /workspace/coverage/default/4.sram_ctrl_mem_walk.474111465 Jul 02 10:00:06 AM PDT 24 Jul 02 10:05:05 AM PDT 24 5474269650 ps
T842 /workspace/coverage/default/12.sram_ctrl_alert_test.2713243486 Jul 02 10:00:39 AM PDT 24 Jul 02 10:00:41 AM PDT 24 17312967 ps
T843 /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.3874313245 Jul 02 10:01:26 AM PDT 24 Jul 02 10:07:05 AM PDT 24 13492905494 ps
T844 /workspace/coverage/default/15.sram_ctrl_partial_access.2019378841 Jul 02 10:00:37 AM PDT 24 Jul 02 10:02:54 AM PDT 24 3547025936 ps
T845 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.3679533747 Jul 02 10:03:09 AM PDT 24 Jul 02 10:06:35 AM PDT 24 2999900991 ps
T846 /workspace/coverage/default/20.sram_ctrl_multiple_keys.3373038182 Jul 02 10:00:42 AM PDT 24 Jul 02 10:18:07 AM PDT 24 13387259434 ps
T847 /workspace/coverage/default/16.sram_ctrl_ram_cfg.3218315634 Jul 02 10:00:43 AM PDT 24 Jul 02 10:00:48 AM PDT 24 366089816 ps
T848 /workspace/coverage/default/10.sram_ctrl_mem_partial_access.3062625072 Jul 02 10:00:24 AM PDT 24 Jul 02 10:01:42 AM PDT 24 2363055442 ps
T849 /workspace/coverage/default/27.sram_ctrl_lc_escalation.2342579346 Jul 02 10:01:07 AM PDT 24 Jul 02 10:01:53 AM PDT 24 42150350985 ps
T850 /workspace/coverage/default/14.sram_ctrl_stress_all.2090712842 Jul 02 10:00:55 AM PDT 24 Jul 02 10:04:11 AM PDT 24 71405005481 ps
T851 /workspace/coverage/default/37.sram_ctrl_executable.3194517965 Jul 02 10:02:16 AM PDT 24 Jul 02 10:02:41 AM PDT 24 8325554310 ps
T852 /workspace/coverage/default/12.sram_ctrl_smoke.1967066574 Jul 02 10:00:27 AM PDT 24 Jul 02 10:01:08 AM PDT 24 1040847283 ps
T853 /workspace/coverage/default/18.sram_ctrl_mem_partial_access.3825387107 Jul 02 10:01:04 AM PDT 24 Jul 02 10:03:49 AM PDT 24 5020447294 ps
T854 /workspace/coverage/default/18.sram_ctrl_executable.3163119226 Jul 02 10:00:45 AM PDT 24 Jul 02 10:10:21 AM PDT 24 16600635081 ps
T855 /workspace/coverage/default/19.sram_ctrl_lc_escalation.198738787 Jul 02 10:01:01 AM PDT 24 Jul 02 10:01:52 AM PDT 24 31423457950 ps
T856 /workspace/coverage/default/24.sram_ctrl_stress_all.3783414766 Jul 02 10:00:55 AM PDT 24 Jul 02 10:22:16 AM PDT 24 100107294601 ps
T857 /workspace/coverage/default/35.sram_ctrl_lc_escalation.4257902128 Jul 02 10:02:02 AM PDT 24 Jul 02 10:02:29 AM PDT 24 4327379674 ps
T858 /workspace/coverage/default/0.sram_ctrl_max_throughput.1826874502 Jul 02 10:00:07 AM PDT 24 Jul 02 10:02:35 AM PDT 24 796094087 ps
T859 /workspace/coverage/default/26.sram_ctrl_stress_all.3824464373 Jul 02 10:01:06 AM PDT 24 Jul 02 12:49:19 PM PDT 24 1452820851580 ps
T860 /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.3853832990 Jul 02 10:01:24 AM PDT 24 Jul 02 10:01:35 AM PDT 24 1376255860 ps
T861 /workspace/coverage/default/43.sram_ctrl_partial_access.972575602 Jul 02 10:03:10 AM PDT 24 Jul 02 10:03:33 AM PDT 24 1482697251 ps
T862 /workspace/coverage/default/23.sram_ctrl_mem_walk.347411031 Jul 02 10:01:00 AM PDT 24 Jul 02 10:04:04 AM PDT 24 40657931901 ps
T863 /workspace/coverage/default/24.sram_ctrl_ram_cfg.4127513876 Jul 02 10:00:56 AM PDT 24 Jul 02 10:01:00 AM PDT 24 367530748 ps
T864 /workspace/coverage/default/41.sram_ctrl_mem_partial_access.1311576744 Jul 02 10:02:54 AM PDT 24 Jul 02 10:04:01 AM PDT 24 3991801175 ps
T865 /workspace/coverage/default/31.sram_ctrl_regwen.919342201 Jul 02 10:01:34 AM PDT 24 Jul 02 10:03:20 AM PDT 24 1239378813 ps
T866 /workspace/coverage/default/21.sram_ctrl_stress_all.3641299369 Jul 02 10:01:01 AM PDT 24 Jul 02 11:27:45 AM PDT 24 100467465926 ps
T867 /workspace/coverage/default/40.sram_ctrl_bijection.545727443 Jul 02 10:02:38 AM PDT 24 Jul 02 10:24:19 AM PDT 24 69519155618 ps
T868 /workspace/coverage/default/10.sram_ctrl_max_throughput.2906813558 Jul 02 10:00:34 AM PDT 24 Jul 02 10:02:24 AM PDT 24 793559336 ps
T869 /workspace/coverage/default/29.sram_ctrl_mem_walk.2550166172 Jul 02 10:01:21 AM PDT 24 Jul 02 10:06:59 AM PDT 24 13852392495 ps
T870 /workspace/coverage/default/45.sram_ctrl_stress_pipeline.819160679 Jul 02 10:03:20 AM PDT 24 Jul 02 10:06:47 AM PDT 24 25983161463 ps
T871 /workspace/coverage/default/25.sram_ctrl_smoke.3933227433 Jul 02 10:00:55 AM PDT 24 Jul 02 10:01:07 AM PDT 24 1028027602 ps
T872 /workspace/coverage/default/41.sram_ctrl_stress_pipeline.933979648 Jul 02 10:02:49 AM PDT 24 Jul 02 10:06:30 AM PDT 24 7853435385 ps
T873 /workspace/coverage/default/7.sram_ctrl_ram_cfg.127445160 Jul 02 10:00:07 AM PDT 24 Jul 02 10:00:16 AM PDT 24 358661416 ps
T874 /workspace/coverage/default/11.sram_ctrl_bijection.1600252249 Jul 02 10:00:39 AM PDT 24 Jul 02 10:38:54 AM PDT 24 179408786378 ps
T875 /workspace/coverage/default/41.sram_ctrl_ram_cfg.1407590690 Jul 02 10:02:55 AM PDT 24 Jul 02 10:02:58 AM PDT 24 1293787606 ps
T119 /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1794926316 Jul 02 10:00:24 AM PDT 24 Jul 02 10:01:00 AM PDT 24 5661392677 ps
T876 /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.4193247747 Jul 02 09:59:54 AM PDT 24 Jul 02 10:04:09 AM PDT 24 4487363539 ps
T877 /workspace/coverage/default/26.sram_ctrl_smoke.2179563361 Jul 02 10:01:02 AM PDT 24 Jul 02 10:03:25 AM PDT 24 3025145135 ps
T878 /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.3994010503 Jul 02 10:01:45 AM PDT 24 Jul 02 10:02:02 AM PDT 24 6350624478 ps
T879 /workspace/coverage/default/37.sram_ctrl_lc_escalation.3953692577 Jul 02 10:02:16 AM PDT 24 Jul 02 10:03:24 AM PDT 24 36483733093 ps
T31 /workspace/coverage/default/0.sram_ctrl_sec_cm.2614765876 Jul 02 09:59:57 AM PDT 24 Jul 02 10:00:03 AM PDT 24 583808192 ps
T880 /workspace/coverage/default/48.sram_ctrl_mem_partial_access.2275837334 Jul 02 10:03:52 AM PDT 24 Jul 02 10:05:55 AM PDT 24 3153137764 ps
T881 /workspace/coverage/default/47.sram_ctrl_mem_partial_access.614823476 Jul 02 10:03:46 AM PDT 24 Jul 02 10:04:55 AM PDT 24 5975790131 ps
T882 /workspace/coverage/default/48.sram_ctrl_smoke.1013360230 Jul 02 10:03:50 AM PDT 24 Jul 02 10:04:24 AM PDT 24 998461668 ps
T883 /workspace/coverage/default/16.sram_ctrl_max_throughput.773369298 Jul 02 10:00:52 AM PDT 24 Jul 02 10:01:04 AM PDT 24 1392095091 ps
T884 /workspace/coverage/default/34.sram_ctrl_ram_cfg.4225900310 Jul 02 10:01:54 AM PDT 24 Jul 02 10:01:58 AM PDT 24 3064499213 ps
T885 /workspace/coverage/default/26.sram_ctrl_mem_partial_access.1055194186 Jul 02 10:01:06 AM PDT 24 Jul 02 10:03:30 AM PDT 24 6307490258 ps
T886 /workspace/coverage/default/15.sram_ctrl_access_during_key_req.2698325309 Jul 02 10:00:38 AM PDT 24 Jul 02 10:23:51 AM PDT 24 48421089507 ps
T887 /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3212006250 Jul 02 10:00:04 AM PDT 24 Jul 02 10:07:26 AM PDT 24 131388450237 ps
T888 /workspace/coverage/default/32.sram_ctrl_mem_walk.173394487 Jul 02 10:01:39 AM PDT 24 Jul 02 10:05:44 AM PDT 24 10663662565 ps
T889 /workspace/coverage/default/28.sram_ctrl_bijection.3652939710 Jul 02 10:01:12 AM PDT 24 Jul 02 10:36:59 AM PDT 24 31865419029 ps
T890 /workspace/coverage/default/4.sram_ctrl_stress_all.2543478612 Jul 02 10:00:22 AM PDT 24 Jul 02 10:14:13 AM PDT 24 228722837154 ps
T891 /workspace/coverage/default/36.sram_ctrl_bijection.2413162425 Jul 02 10:02:08 AM PDT 24 Jul 02 10:19:42 AM PDT 24 15214810651 ps
T892 /workspace/coverage/default/40.sram_ctrl_multiple_keys.647690300 Jul 02 10:02:33 AM PDT 24 Jul 02 10:07:50 AM PDT 24 7964638209 ps
T893 /workspace/coverage/default/14.sram_ctrl_mem_partial_access.1355386194 Jul 02 10:00:34 AM PDT 24 Jul 02 10:03:27 AM PDT 24 39883230121 ps
T894 /workspace/coverage/default/2.sram_ctrl_mem_walk.1351388424 Jul 02 10:00:02 AM PDT 24 Jul 02 10:05:21 AM PDT 24 5419231586 ps
T895 /workspace/coverage/default/46.sram_ctrl_access_during_key_req.2284381194 Jul 02 10:03:34 AM PDT 24 Jul 02 10:30:50 AM PDT 24 55090348003 ps
T896 /workspace/coverage/default/40.sram_ctrl_stress_all.986611460 Jul 02 10:02:46 AM PDT 24 Jul 02 12:23:25 PM PDT 24 382285834022 ps
T897 /workspace/coverage/default/11.sram_ctrl_mem_walk.3421706163 Jul 02 10:00:35 AM PDT 24 Jul 02 10:05:35 AM PDT 24 5472568939 ps
T898 /workspace/coverage/default/17.sram_ctrl_regwen.2001753447 Jul 02 10:00:38 AM PDT 24 Jul 02 10:11:08 AM PDT 24 13574138364 ps
T899 /workspace/coverage/default/17.sram_ctrl_lc_escalation.514186335 Jul 02 10:00:50 AM PDT 24 Jul 02 10:02:14 AM PDT 24 25648625419 ps
T900 /workspace/coverage/default/45.sram_ctrl_stress_all.2183797830 Jul 02 10:03:29 AM PDT 24 Jul 02 10:38:28 AM PDT 24 290124550399 ps
T901 /workspace/coverage/default/1.sram_ctrl_max_throughput.1767588185 Jul 02 10:00:11 AM PDT 24 Jul 02 10:00:56 AM PDT 24 773942072 ps
T902 /workspace/coverage/default/8.sram_ctrl_mem_walk.1753076294 Jul 02 10:00:12 AM PDT 24 Jul 02 10:03:10 AM PDT 24 47284480845 ps
T903 /workspace/coverage/default/0.sram_ctrl_alert_test.1645821797 Jul 02 10:00:03 AM PDT 24 Jul 02 10:00:08 AM PDT 24 33964428 ps
T904 /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.1477866223 Jul 02 10:02:29 AM PDT 24 Jul 02 10:12:57 AM PDT 24 102701733704 ps
T905 /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3187882858 Jul 02 10:00:32 AM PDT 24 Jul 02 10:01:45 AM PDT 24 5961053288 ps
T906 /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.3835245208 Jul 02 10:01:22 AM PDT 24 Jul 02 10:06:03 AM PDT 24 11863952725 ps
T907 /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.560697991 Jul 02 10:01:11 AM PDT 24 Jul 02 10:01:56 AM PDT 24 5628264133 ps
T908 /workspace/coverage/default/7.sram_ctrl_executable.2434663465 Jul 02 10:00:26 AM PDT 24 Jul 02 10:05:03 AM PDT 24 3662826193 ps
T909 /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.1373598671 Jul 02 10:01:28 AM PDT 24 Jul 02 10:12:28 AM PDT 24 117975096157 ps
T910 /workspace/coverage/default/20.sram_ctrl_max_throughput.1747160613 Jul 02 10:00:46 AM PDT 24 Jul 02 10:00:55 AM PDT 24 4162531427 ps
T911 /workspace/coverage/default/27.sram_ctrl_ram_cfg.2512467734 Jul 02 10:01:06 AM PDT 24 Jul 02 10:01:11 AM PDT 24 470906403 ps
T912 /workspace/coverage/default/24.sram_ctrl_mem_partial_access.30511964 Jul 02 10:01:00 AM PDT 24 Jul 02 10:02:20 AM PDT 24 13917579059 ps
T913 /workspace/coverage/default/20.sram_ctrl_mem_partial_access.4106891043 Jul 02 10:00:50 AM PDT 24 Jul 02 10:03:22 AM PDT 24 6303086770 ps
T914 /workspace/coverage/default/35.sram_ctrl_multiple_keys.2374633616 Jul 02 10:01:57 AM PDT 24 Jul 02 10:13:01 AM PDT 24 32675196723 ps
T915 /workspace/coverage/default/13.sram_ctrl_partial_access.751700084 Jul 02 10:00:40 AM PDT 24 Jul 02 10:00:49 AM PDT 24 702007774 ps
T916 /workspace/coverage/default/2.sram_ctrl_executable.3117063437 Jul 02 10:00:01 AM PDT 24 Jul 02 10:05:56 AM PDT 24 36287813891 ps
T917 /workspace/coverage/default/43.sram_ctrl_executable.3245585116 Jul 02 10:03:14 AM PDT 24 Jul 02 10:13:28 AM PDT 24 19889476132 ps
T918 /workspace/coverage/default/40.sram_ctrl_executable.2719705259 Jul 02 10:02:37 AM PDT 24 Jul 02 10:13:42 AM PDT 24 107796106109 ps
T919 /workspace/coverage/default/31.sram_ctrl_smoke.2532071354 Jul 02 10:01:28 AM PDT 24 Jul 02 10:01:35 AM PDT 24 889089746 ps
T920 /workspace/coverage/default/12.sram_ctrl_multiple_keys.3319094823 Jul 02 10:00:40 AM PDT 24 Jul 02 10:07:53 AM PDT 24 7253820288 ps
T921 /workspace/coverage/default/33.sram_ctrl_stress_all.2806944862 Jul 02 10:01:45 AM PDT 24 Jul 02 11:41:27 AM PDT 24 195101452050 ps
T922 /workspace/coverage/default/45.sram_ctrl_partial_access.2283558840 Jul 02 10:03:22 AM PDT 24 Jul 02 10:03:38 AM PDT 24 534720098 ps
T923 /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.3025151978 Jul 02 10:01:09 AM PDT 24 Jul 02 10:07:58 AM PDT 24 64833134655 ps
T924 /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.352464261 Jul 02 10:00:43 AM PDT 24 Jul 02 10:01:11 AM PDT 24 6531089118 ps
T925 /workspace/coverage/default/39.sram_ctrl_bijection.159075462 Jul 02 10:02:33 AM PDT 24 Jul 02 10:11:25 AM PDT 24 23255478230 ps
T926 /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.2051585230 Jul 02 10:02:34 AM PDT 24 Jul 02 10:02:44 AM PDT 24 2354286392 ps
T927 /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.1504383721 Jul 02 10:02:35 AM PDT 24 Jul 02 10:11:38 AM PDT 24 116968224442 ps
T928 /workspace/coverage/default/39.sram_ctrl_lc_escalation.2871829931 Jul 02 10:02:31 AM PDT 24 Jul 02 10:04:00 AM PDT 24 69915179330 ps
T929 /workspace/coverage/default/7.sram_ctrl_access_during_key_req.3874168575 Jul 02 10:00:08 AM PDT 24 Jul 02 10:27:31 AM PDT 24 17561791228 ps
T930 /workspace/coverage/default/14.sram_ctrl_partial_access.337371673 Jul 02 10:00:40 AM PDT 24 Jul 02 10:01:54 AM PDT 24 1899707613 ps
T931 /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1765789125 Jul 02 10:00:18 AM PDT 24 Jul 02 10:00:56 AM PDT 24 4293188088 ps
T932 /workspace/coverage/default/10.sram_ctrl_access_during_key_req.1382109863 Jul 02 10:00:24 AM PDT 24 Jul 02 10:05:17 AM PDT 24 3624363639 ps
T933 /workspace/coverage/default/22.sram_ctrl_max_throughput.2318085064 Jul 02 10:01:01 AM PDT 24 Jul 02 10:03:21 AM PDT 24 5030003463 ps
T934 /workspace/coverage/default/2.sram_ctrl_multiple_keys.3459104599 Jul 02 10:00:11 AM PDT 24 Jul 02 10:13:24 AM PDT 24 11954230677 ps
T935 /workspace/coverage/default/49.sram_ctrl_stress_all.2551520189 Jul 02 10:04:01 AM PDT 24 Jul 02 10:54:12 AM PDT 24 34640590189 ps
T936 /workspace/coverage/default/47.sram_ctrl_alert_test.4131250302 Jul 02 10:03:51 AM PDT 24 Jul 02 10:03:52 AM PDT 24 16598893 ps
T937 /workspace/coverage/default/18.sram_ctrl_ram_cfg.3959039532 Jul 02 10:00:41 AM PDT 24 Jul 02 10:00:46 AM PDT 24 1874511582 ps
T938 /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2075967270 Jul 02 10:03:30 AM PDT 24 Jul 02 10:04:16 AM PDT 24 805248976 ps
T939 /workspace/coverage/default/44.sram_ctrl_ram_cfg.1647660542 Jul 02 10:03:18 AM PDT 24 Jul 02 10:03:23 AM PDT 24 3348920317 ps
T940 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.975387258 Jul 02 09:04:54 AM PDT 24 Jul 02 09:04:58 AM PDT 24 298230262 ps
T65 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2515453330 Jul 02 09:04:49 AM PDT 24 Jul 02 09:05:40 AM PDT 24 28145032657 ps
T66 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3454151489 Jul 02 09:04:39 AM PDT 24 Jul 02 09:04:41 AM PDT 24 237212132 ps
T67 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1634310510 Jul 02 09:04:51 AM PDT 24 Jul 02 09:05:19 AM PDT 24 3714143953 ps
T99 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.65888693 Jul 02 09:04:56 AM PDT 24 Jul 02 09:04:57 AM PDT 24 25279431 ps
T941 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2343771070 Jul 02 09:04:40 AM PDT 24 Jul 02 09:04:42 AM PDT 24 203775296 ps
T77 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.4229067140 Jul 02 09:04:40 AM PDT 24 Jul 02 09:04:42 AM PDT 24 64994075 ps
T113 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3605909901 Jul 02 09:04:36 AM PDT 24 Jul 02 09:04:38 AM PDT 24 129893874 ps
T100 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1412160504 Jul 02 09:04:35 AM PDT 24 Jul 02 09:04:36 AM PDT 24 42787506 ps
T101 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2411603985 Jul 02 09:04:42 AM PDT 24 Jul 02 09:04:43 AM PDT 24 96934531 ps
T62 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.401069086 Jul 02 09:04:44 AM PDT 24 Jul 02 09:04:46 AM PDT 24 122350049 ps
T63 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2149685741 Jul 02 09:04:54 AM PDT 24 Jul 02 09:04:57 AM PDT 24 83105136 ps
T942 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1727988169 Jul 02 09:04:33 AM PDT 24 Jul 02 09:04:34 AM PDT 24 64327661 ps
T102 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4288103371 Jul 02 09:04:53 AM PDT 24 Jul 02 09:04:54 AM PDT 24 74644391 ps
T943 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4268311405 Jul 02 09:04:48 AM PDT 24 Jul 02 09:04:53 AM PDT 24 219315460 ps
T78 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2373180460 Jul 02 09:04:36 AM PDT 24 Jul 02 09:04:38 AM PDT 24 31941801 ps
T64 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.546684794 Jul 02 09:04:57 AM PDT 24 Jul 02 09:05:00 AM PDT 24 206789109 ps
T103 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.564910906 Jul 02 09:05:04 AM PDT 24 Jul 02 09:05:06 AM PDT 24 59249833 ps
T79 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.630488363 Jul 02 09:04:40 AM PDT 24 Jul 02 09:05:11 AM PDT 24 3702061684 ps
T944 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1535013310 Jul 02 09:04:27 AM PDT 24 Jul 02 09:04:32 AM PDT 24 355087519 ps
T945 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2300603770 Jul 02 09:05:06 AM PDT 24 Jul 02 09:05:11 AM PDT 24 42866657 ps
T104 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.143594578 Jul 02 09:04:49 AM PDT 24 Jul 02 09:04:51 AM PDT 24 54516785 ps
T80 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3066671441 Jul 02 09:04:43 AM PDT 24 Jul 02 09:04:44 AM PDT 24 46656969 ps
T946 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.4066342252 Jul 02 09:04:26 AM PDT 24 Jul 02 09:04:28 AM PDT 24 97223129 ps
T81 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2382912806 Jul 02 09:04:42 AM PDT 24 Jul 02 09:05:30 AM PDT 24 14718362543 ps
T82 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2829830423 Jul 02 09:04:39 AM PDT 24 Jul 02 09:04:40 AM PDT 24 20240005 ps
T83 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2936541460 Jul 02 09:04:30 AM PDT 24 Jul 02 09:04:58 AM PDT 24 3971072471 ps
T947 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2579509227 Jul 02 09:04:27 AM PDT 24 Jul 02 09:04:32 AM PDT 24 42890033 ps
T948 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3452845909 Jul 02 09:04:58 AM PDT 24 Jul 02 09:05:03 AM PDT 24 69640359 ps
T949 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.435489916 Jul 02 09:04:27 AM PDT 24 Jul 02 09:05:01 AM PDT 24 19421548242 ps
T950 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2606898431 Jul 02 09:04:51 AM PDT 24 Jul 02 09:04:53 AM PDT 24 20235993 ps
T951 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.646097609 Jul 02 09:04:57 AM PDT 24 Jul 02 09:04:59 AM PDT 24 75796414 ps
T952 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1394191505 Jul 02 09:04:44 AM PDT 24 Jul 02 09:04:46 AM PDT 24 59373093 ps
T84 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2505182478 Jul 02 09:04:29 AM PDT 24 Jul 02 09:04:30 AM PDT 24 44514961 ps
T120 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1634120122 Jul 02 09:05:05 AM PDT 24 Jul 02 09:05:08 AM PDT 24 948912662 ps
T953 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1410758765 Jul 02 09:04:37 AM PDT 24 Jul 02 09:04:39 AM PDT 24 13635849 ps
T954 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.298860506 Jul 02 09:04:46 AM PDT 24 Jul 02 09:04:48 AM PDT 24 88136610 ps
T955 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1858858616 Jul 02 09:04:58 AM PDT 24 Jul 02 09:05:04 AM PDT 24 371296012 ps
T85 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.4239522822 Jul 02 09:04:45 AM PDT 24 Jul 02 09:05:47 AM PDT 24 26121402839 ps
T86 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1294409123 Jul 02 09:05:06 AM PDT 24 Jul 02 09:06:02 AM PDT 24 7614375331 ps
T956 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2038265139 Jul 02 09:04:29 AM PDT 24 Jul 02 09:04:31 AM PDT 24 36700850 ps
T957 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.4192460412 Jul 02 09:04:50 AM PDT 24 Jul 02 09:04:52 AM PDT 24 34968783 ps
T128 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.103885289 Jul 02 09:04:59 AM PDT 24 Jul 02 09:05:03 AM PDT 24 117869351 ps
T124 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3212569745 Jul 02 09:04:45 AM PDT 24 Jul 02 09:04:47 AM PDT 24 357084482 ps
T131 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1394085831 Jul 02 09:04:50 AM PDT 24 Jul 02 09:04:53 AM PDT 24 156786484 ps
T958 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.4001901918 Jul 02 09:04:37 AM PDT 24 Jul 02 09:04:42 AM PDT 24 1362458632 ps
T959 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3522507375 Jul 02 09:04:49 AM PDT 24 Jul 02 09:04:53 AM PDT 24 66124023 ps
T960 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1955327689 Jul 02 09:04:50 AM PDT 24 Jul 02 09:04:54 AM PDT 24 144345281 ps
T961 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1484744735 Jul 02 09:04:56 AM PDT 24 Jul 02 09:05:01 AM PDT 24 4928564420 ps
T962 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.438002628 Jul 02 09:04:46 AM PDT 24 Jul 02 09:04:52 AM PDT 24 261809983 ps
T87 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2225899880 Jul 02 09:04:39 AM PDT 24 Jul 02 09:04:41 AM PDT 24 12933562 ps
T93 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1936694232 Jul 02 09:04:40 AM PDT 24 Jul 02 09:05:10 AM PDT 24 4999370573 ps
T121 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3904658109 Jul 02 09:05:02 AM PDT 24 Jul 02 09:05:05 AM PDT 24 237136780 ps
T94 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.4146516993 Jul 02 09:04:50 AM PDT 24 Jul 02 09:05:44 AM PDT 24 28245961008 ps
T130 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.207922376 Jul 02 09:04:41 AM PDT 24 Jul 02 09:04:44 AM PDT 24 89415839 ps
T963 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1154066266 Jul 02 09:04:42 AM PDT 24 Jul 02 09:04:46 AM PDT 24 1535960026 ps
T964 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2132795181 Jul 02 09:04:57 AM PDT 24 Jul 02 09:05:00 AM PDT 24 17372067 ps
T965 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1958903697 Jul 02 09:05:02 AM PDT 24 Jul 02 09:05:09 AM PDT 24 4331690309 ps
T966 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2365325276 Jul 02 09:04:41 AM PDT 24 Jul 02 09:04:42 AM PDT 24 21060452 ps
T967 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.955010950 Jul 02 09:04:33 AM PDT 24 Jul 02 09:04:37 AM PDT 24 156069300 ps
T968 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1309056978 Jul 02 09:04:33 AM PDT 24 Jul 02 09:04:37 AM PDT 24 1347048407 ps
T969 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.429225072 Jul 02 09:04:25 AM PDT 24 Jul 02 09:04:27 AM PDT 24 13417952 ps
T970 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1084502788 Jul 02 09:04:57 AM PDT 24 Jul 02 09:05:04 AM PDT 24 5898605283 ps
T971 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2379048692 Jul 02 09:04:54 AM PDT 24 Jul 02 09:04:56 AM PDT 24 34429930 ps
T972 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.868148383 Jul 02 09:04:58 AM PDT 24 Jul 02 09:05:00 AM PDT 24 143164412 ps
T125 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.419427326 Jul 02 09:04:54 AM PDT 24 Jul 02 09:04:57 AM PDT 24 350421652 ps
T973 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.4202824850 Jul 02 09:04:46 AM PDT 24 Jul 02 09:04:52 AM PDT 24 371940599 ps
T95 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1288267124 Jul 02 09:05:06 AM PDT 24 Jul 02 09:06:02 AM PDT 24 28150419357 ps
T974 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2502614835 Jul 02 09:04:45 AM PDT 24 Jul 02 09:04:50 AM PDT 24 364915172 ps
T975 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3020401582 Jul 02 09:04:29 AM PDT 24 Jul 02 09:04:33 AM PDT 24 1367028050 ps
T976 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.250356768 Jul 02 09:04:32 AM PDT 24 Jul 02 09:04:33 AM PDT 24 188871238 ps
T129 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1555189056 Jul 02 09:05:01 AM PDT 24 Jul 02 09:05:06 AM PDT 24 377483102 ps
T96 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1137223235 Jul 02 09:04:50 AM PDT 24 Jul 02 09:04:52 AM PDT 24 87667062 ps
T977 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2844993090 Jul 02 09:04:36 AM PDT 24 Jul 02 09:04:39 AM PDT 24 22629086 ps
T978 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.645789973 Jul 02 09:04:28 AM PDT 24 Jul 02 09:04:30 AM PDT 24 44625113 ps
T979 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3833777076 Jul 02 09:04:34 AM PDT 24 Jul 02 09:04:37 AM PDT 24 409558062 ps
T980 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3581341811 Jul 02 09:04:46 AM PDT 24 Jul 02 09:04:49 AM PDT 24 16134208 ps
T981 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.372621720 Jul 02 09:04:48 AM PDT 24 Jul 02 09:04:54 AM PDT 24 715343023 ps
T126 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.987183059 Jul 02 09:04:33 AM PDT 24 Jul 02 09:04:36 AM PDT 24 150505131 ps
T982 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1945623571 Jul 02 09:04:48 AM PDT 24 Jul 02 09:04:52 AM PDT 24 66766905 ps
T983 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1335879393 Jul 02 09:04:42 AM PDT 24 Jul 02 09:04:47 AM PDT 24 362636060 ps
T97 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2219545204 Jul 02 09:04:58 AM PDT 24 Jul 02 09:05:00 AM PDT 24 23160665 ps
T984 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1700752750 Jul 02 09:04:50 AM PDT 24 Jul 02 09:04:52 AM PDT 24 34394496 ps
T985 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2189715469 Jul 02 09:05:12 AM PDT 24 Jul 02 09:05:15 AM PDT 24 24058851 ps
T98 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.321714803 Jul 02 09:04:43 AM PDT 24 Jul 02 09:05:23 AM PDT 24 40946581689 ps
T986 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1900178088 Jul 02 09:04:47 AM PDT 24 Jul 02 09:04:51 AM PDT 24 80349404 ps
T987 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1510836244 Jul 02 09:04:52 AM PDT 24 Jul 02 09:04:57 AM PDT 24 729035709 ps
T122 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3003478579 Jul 02 09:05:10 AM PDT 24 Jul 02 09:05:14 AM PDT 24 1019052799 ps
T988 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3048739441 Jul 02 09:04:51 AM PDT 24 Jul 02 09:05:45 AM PDT 24 7445502847 ps
T989 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.512375989 Jul 02 09:04:56 AM PDT 24 Jul 02 09:04:57 AM PDT 24 18295753 ps
T990 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1258186792 Jul 02 09:04:51 AM PDT 24 Jul 02 09:04:57 AM PDT 24 574992800 ps
T991 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2992161071 Jul 02 09:04:53 AM PDT 24 Jul 02 09:05:42 AM PDT 24 7081749065 ps
T123 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.447320526 Jul 02 09:04:30 AM PDT 24 Jul 02 09:04:32 AM PDT 24 186545910 ps
T992 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2482057208 Jul 02 09:05:07 AM PDT 24 Jul 02 09:06:07 AM PDT 24 33582931342 ps
T993 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.793103135 Jul 02 09:04:57 AM PDT 24 Jul 02 09:05:03 AM PDT 24 1388108741 ps
T994 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1896064853 Jul 02 09:04:31 AM PDT 24 Jul 02 09:04:33 AM PDT 24 117213313 ps
T995 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2096272046 Jul 02 09:04:44 AM PDT 24 Jul 02 09:05:38 AM PDT 24 7434798350 ps
T996 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1997682909 Jul 02 09:04:45 AM PDT 24 Jul 02 09:04:48 AM PDT 24 76837420 ps
T997 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2326851058 Jul 02 09:04:55 AM PDT 24 Jul 02 09:04:59 AM PDT 24 102671052 ps
T998 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1744159150 Jul 02 09:04:58 AM PDT 24 Jul 02 09:05:01 AM PDT 24 68871861 ps
T999 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2216505660 Jul 02 09:04:46 AM PDT 24 Jul 02 09:04:48 AM PDT 24 17648443 ps
T1000 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1656556560 Jul 02 09:04:47 AM PDT 24 Jul 02 09:04:50 AM PDT 24 466104719 ps
T1001 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.506311283 Jul 02 09:04:59 AM PDT 24 Jul 02 09:05:33 AM PDT 24 15439520190 ps
T1002 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2336317102 Jul 02 09:04:45 AM PDT 24 Jul 02 09:04:47 AM PDT 24 22279591 ps
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