Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16117034	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

154605161

1

T1

130763

T2

1391

T3

705

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	84039106	1			T1	71989		T2	771		T3	335
values[0x0]	41741946	1			T1	34329		T2	329		T3	173
values[0x1]	44941143	1			T1	37534		T2	445		T3	197

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8196706	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

162525489

1

T1

137445

T2

1463

T3

705

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	680718	1			T1	534		T2	4		T3	2
valid_sources[0x01]	569727	1			T1	548		T2	7		T3	1
valid_sources[0x02]	574641	1			T1	575		T2	7		T3	3
valid_sources[0x03]	565841	1			T1	569		T2	8		T3	7
valid_sources[0x04]	595046	1			T1	566		T2	8		T3	5
valid_sources[0x05]	2217662	1			T1	542		T2	5		T3	1
valid_sources[0x06]	642580	1			T1	533		T2	9		T3	3
valid_sources[0x07]	556593	1			T1	576		T2	6		T3	1
valid_sources[0x08]	600441	1			T1	583		T2	4		T3	3
valid_sources[0x09]	593785	1			T1	528		T2	4		T3	2
valid_sources[0x0a]	589058	1			T1	558		T2	9		T3	2
valid_sources[0x0b]	562014	1			T1	578		T2	8		T3	5
valid_sources[0x0c]	611334	1			T1	579		T2	8		T3	1
valid_sources[0x0d]	602329	1			T1	524		T2	1		T3	3
valid_sources[0x0e]	555169	1			T1	557		T2	3		T3	3
valid_sources[0x0f]	559150	1			T1	638		T2	5		T3	1
valid_sources[0x10]	631988	1			T1	552		T2	9		T3	3
valid_sources[0x11]	632975	1			T1	542		T2	10		T3	2
valid_sources[0x12]	570261	1			T1	551		T2	9		T3	3
valid_sources[0x13]	584592	1			T1	527		T2	12		T3	2
valid_sources[0x14]	562279	1			T1	591		T2	6		T3	2
valid_sources[0x15]	639197	1			T1	545		T2	5		T3	2
valid_sources[0x16]	575993	1			T1	531		T2	15		T3	2
valid_sources[0x17]	1873483	1			T1	619		T2	4		T3	2
valid_sources[0x18]	572077	1			T1	575		T2	4		T3	4
valid_sources[0x19]	557193	1			T1	528		T2	9		T3	4
valid_sources[0x1a]	570227	1			T1	576		T2	10		T3	3
valid_sources[0x1b]	590019	1			T1	593		T2	6		T3	1
valid_sources[0x1c]	577402	1			T1	551		T2	1		T3	5
valid_sources[0x1d]	583716	1			T1	575		T2	5		T3	4
valid_sources[0x1e]	572191	1			T1	592		T2	5		T4	1008
valid_sources[0x1f]	1523209	1			T1	592		T2	11		T3	4
valid_sources[0x20]	553054	1			T1	583		T2	7		T3	4
valid_sources[0x21]	568408	1			T1	567		T2	5		T3	1
valid_sources[0x22]	752164	1			T1	601		T2	5		T3	1
valid_sources[0x23]	596831	1			T1	522		T2	12		T3	1
valid_sources[0x24]	659259	1			T1	587		T3	4		T4	1104
valid_sources[0x25]	610970	1			T1	561		T2	3		T3	4
valid_sources[0x26]	649752	1			T1	547		T2	5		T3	5
valid_sources[0x27]	568989	1			T1	526		T2	5		T3	5
valid_sources[0x28]	590977	1			T1	518		T2	3		T3	3
valid_sources[0x29]	563538	1			T1	608		T2	8		T3	2
valid_sources[0x2a]	572573	1			T1	585		T2	6		T3	6
valid_sources[0x2b]	2766578	1			T1	525		T2	7		T3	3
valid_sources[0x2c]	621157	1			T1	580		T2	8		T3	3
valid_sources[0x2d]	610350	1			T1	584		T2	6		T3	5
valid_sources[0x2e]	580921	1			T1	551		T2	3		T3	2
valid_sources[0x2f]	561565	1			T1	539		T2	5		T3	1
valid_sources[0x30]	612654	1			T1	549		T2	6		T3	3
valid_sources[0x31]	592696	1			T1	562		T2	11		T3	3
valid_sources[0x32]	573494	1			T1	552		T2	5		T3	3
valid_sources[0x33]	583838	1			T1	560		T2	2		T3	4
valid_sources[0x34]	609445	1			T1	564		T2	9		T3	1
valid_sources[0x35]	570030	1			T1	572		T2	4		T3	2
valid_sources[0x36]	560974	1			T1	599		T2	7		T3	1
valid_sources[0x37]	790658	1			T1	580		T2	7		T3	3
valid_sources[0x38]	576685	1			T1	552		T2	5		T3	1
valid_sources[0x39]	616454	1			T1	552		T2	3		T3	1
valid_sources[0x3a]	588387	1			T1	538		T2	4		T3	1
valid_sources[0x3b]	569404	1			T1	541		T2	3		T3	2
valid_sources[0x3c]	571891	1			T1	573		T2	5		T3	3
valid_sources[0x3d]	576393	1			T1	627		T2	6		T3	2
valid_sources[0x3e]	566761	1			T1	564		T2	3		T3	1
valid_sources[0x3f]	594534	1			T1	560		T2	5		T3	1
valid_sources[0x40]	625200	1			T1	527		T2	7		T3	2
valid_sources[0x41]	624034	1			T1	552		T2	2		T3	4
valid_sources[0x42]	582570	1			T1	580		T2	11		T4	1030
valid_sources[0x43]	1607364	1			T1	569		T2	6		T3	1
valid_sources[0x44]	575326	1			T1	591		T2	5		T3	3
valid_sources[0x45]	1909514	1			T1	566		T2	3		T3	2
valid_sources[0x46]	583452	1			T1	521		T2	6		T3	1
valid_sources[0x47]	791856	1			T1	583		T2	3		T3	3
valid_sources[0x48]	657751	1			T1	598		T2	3		T3	2
valid_sources[0x49]	650139	1			T1	560		T2	1		T3	3
valid_sources[0x4a]	567100	1			T1	544		T2	4		T3	2
valid_sources[0x4b]	591210	1			T1	584		T2	3		T3	2
valid_sources[0x4c]	595174	1			T1	541		T2	7		T3	3
valid_sources[0x4d]	569813	1			T1	506		T2	7		T3	4
valid_sources[0x4e]	592889	1			T1	506		T2	4		T3	5
valid_sources[0x4f]	565251	1			T1	595		T2	5		T3	2
valid_sources[0x50]	765139	1			T1	567		T2	4		T3	4
valid_sources[0x51]	1984740	1			T1	578		T2	9		T3	2
valid_sources[0x52]	556500	1			T1	542		T2	5		T3	3
valid_sources[0x53]	561434	1			T1	522		T2	4		T3	3
valid_sources[0x54]	583147	1			T1	581		T2	5		T3	1
valid_sources[0x55]	583009	1			T1	565		T2	3		T3	2
valid_sources[0x56]	623218	1			T1	548		T2	7		T3	5
valid_sources[0x57]	595027	1			T1	571		T2	3		T4	986
valid_sources[0x58]	566651	1			T1	537		T2	8		T3	4
valid_sources[0x59]	586280	1			T1	600		T2	8		T3	1
valid_sources[0x5a]	644579	1			T1	581		T2	1		T3	3
valid_sources[0x5b]	574566	1			T1	550		T2	9		T3	2
valid_sources[0x5c]	555070	1			T1	609		T2	5		T3	2
valid_sources[0x5d]	591452	1			T1	615		T2	5		T3	5
valid_sources[0x5e]	584204	1			T1	537		T2	6		T3	4
valid_sources[0x5f]	582367	1			T1	556		T2	4		T3	2
valid_sources[0x60]	557496	1			T1	555		T2	8		T3	1
valid_sources[0x61]	562059	1			T1	588		T2	7		T4	973
valid_sources[0x62]	586041	1			T1	504		T2	7		T3	7
valid_sources[0x63]	603206	1			T1	541		T2	4		T3	5
valid_sources[0x64]	620647	1			T1	590		T2	5		T3	1
valid_sources[0x65]	677103	1			T1	622		T2	5		T3	4
valid_sources[0x66]	559548	1			T1	585		T2	7		T3	3
valid_sources[0x67]	586267	1			T1	534		T2	2		T3	4
valid_sources[0x68]	645420	1			T1	613		T2	7		T3	2
valid_sources[0x69]	1507072	1			T1	556		T2	9		T3	3
valid_sources[0x6a]	576924	1			T1	576		T2	6		T3	5
valid_sources[0x6b]	567374	1			T1	578		T2	3		T3	1
valid_sources[0x6c]	641358	1			T1	555		T2	8		T3	3
valid_sources[0x6d]	572011	1			T1	594		T2	7		T3	2
valid_sources[0x6e]	929990	1			T1	581		T2	5		T3	1
valid_sources[0x6f]	594888	1			T1	542		T2	5		T3	3
valid_sources[0x70]	605648	1			T1	615		T2	6		T3	2
valid_sources[0x71]	555583	1			T1	531		T2	3		T3	3
valid_sources[0x72]	565694	1			T1	576		T2	6		T3	3
valid_sources[0x73]	593446	1			T1	562		T2	6		T3	1
valid_sources[0x74]	563855	1			T1	534		T2	1		T4	1024
valid_sources[0x75]	663630	1			T1	559		T2	9		T3	3
valid_sources[0x76]	584950	1			T1	520		T2	6		T3	2
valid_sources[0x77]	632339	1			T1	529		T2	7		T3	3
valid_sources[0x78]	1432139	1			T1	553		T2	9		T3	2
valid_sources[0x79]	576042	1			T1	623		T2	3		T3	2
valid_sources[0x7a]	567792	1			T1	567		T2	5		T3	3
valid_sources[0x7b]	597326	1			T1	526		T2	4		T3	4
valid_sources[0x7c]	590108	1			T1	537		T2	7		T3	2
valid_sources[0x7d]	623776	1			T1	527		T2	7		T4	991
valid_sources[0x7e]	591734	1			T1	553		T2	8		T3	1
valid_sources[0x7f]	585663	1			T1	577		T2	4		T3	5
valid_sources[0x80]	567580	1			T1	578		T2	7		T3	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

75936998

1

T1

65448

T2

699

T3

335

values[0x0]

all_enables

biggest_size

39334905

1

T1

32446

T2

302

T3

173

values[0x1]

all_enables

biggest_size

39333258

1

T1

32869

T2

390

T3

197

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43371	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

164720

1

T1

5

T4

1

T11

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	56857	1			T5	228		T6	10		T7	84
values[0x0]	72949	1			T1	12		T2	1		T4	1
values[0x1]	78285	1			T1	11		T2	1		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33116	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

174975

1

T1

7

T2

1

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	879	1			T5	1		T42	3		T27	1
valid_sources[0x01]	679	1			T12	1		T42	2		T83	1
valid_sources[0x02]	991	1			T5	4		T42	4		T27	2
valid_sources[0x03]	801	1			T5	8		T42	5		T7	1
valid_sources[0x04]	848	1			T5	7		T42	1		T7	1
valid_sources[0x05]	738	1			T42	1		T7	1		T21	1
valid_sources[0x06]	707	1			T42	1		T7	1		T8	1
valid_sources[0x07]	541	1			T6	2		T42	3		T27	1
valid_sources[0x08]	1016	1			T27	2		T25	23		T70	10
valid_sources[0x09]	633	1			T7	2		T151	2		T21	3
valid_sources[0x0a]	697	1			T5	5		T42	1		T7	1
valid_sources[0x0b]	759	1			T42	1		T58	1		T25	16
valid_sources[0x0c]	1161	1			T4	1		T11	6		T5	2
valid_sources[0x0d]	669	1			T5	1		T42	2		T27	1
valid_sources[0x0e]	778	1			T5	10		T27	1		T21	3
valid_sources[0x0f]	808	1			T152	1		T25	22		T26	7
valid_sources[0x10]	669	1			T5	4		T42	2		T7	1
valid_sources[0x11]	676	1			T5	1		T6	2		T42	1
valid_sources[0x12]	1000	1			T5	4		T42	3		T7	1
valid_sources[0x13]	885	1			T11	3		T5	6		T42	1
valid_sources[0x14]	637	1			T42	1		T7	2		T83	1
valid_sources[0x15]	776	1			T5	1		T42	2		T7	2
valid_sources[0x16]	677	1			T5	2		T42	3		T8	3
valid_sources[0x17]	842	1			T40	1		T42	1		T7	1
valid_sources[0x18]	802	1			T5	3		T25	19		T26	3
valid_sources[0x19]	893	1			T5	9		T6	1		T7	1
valid_sources[0x1a]	781	1			T42	2		T7	1		T21	1
valid_sources[0x1b]	666	1			T42	1		T25	18		T26	2
valid_sources[0x1c]	1014	1			T1	3		T5	2		T6	1
valid_sources[0x1d]	580	1			T7	2		T25	21		T26	2
valid_sources[0x1e]	751	1			T13	1		T42	4		T7	1
valid_sources[0x1f]	1113	1			T42	4		T7	2		T25	26
valid_sources[0x20]	697	1			T42	4		T44	2		T143	8
valid_sources[0x21]	934	1			T42	3		T25	29		T70	37
valid_sources[0x22]	666	1			T5	2		T6	1		T25	18
valid_sources[0x23]	912	1			T5	2		T42	1		T151	3
valid_sources[0x24]	790	1			T5	2		T7	1		T9	23
valid_sources[0x25]	667	1			T42	2		T7	1		T8	1
valid_sources[0x26]	595	1			T11	5		T13	1		T21	6
valid_sources[0x27]	1169	1			T5	1		T6	2		T42	3
valid_sources[0x28]	839	1			T5	1		T42	1		T147	1
valid_sources[0x29]	671	1			T6	2		T40	1		T42	2
valid_sources[0x2a]	683	1			T1	3		T42	2		T7	1
valid_sources[0x2b]	797	1			T5	1		T42	3		T118	1
valid_sources[0x2c]	691	1			T5	2		T7	1		T153	2
valid_sources[0x2d]	625	1			T42	2		T21	1		T83	1
valid_sources[0x2e]	610	1			T5	1		T40	1		T25	25
valid_sources[0x2f]	1022	1			T40	1		T42	2		T27	1
valid_sources[0x30]	676	1			T5	6		T8	5		T141	2
valid_sources[0x31]	712	1			T1	1		T5	10		T7	2
valid_sources[0x32]	723	1			T5	6		T42	2		T7	1
valid_sources[0x33]	734	1			T5	3		T42	1		T154	1
valid_sources[0x34]	1363	1			T5	1		T8	6		T78	1
valid_sources[0x35]	1169	1			T42	1		T9	7		T141	1
valid_sources[0x36]	997	1			T5	11		T6	1		T40	1
valid_sources[0x37]	1174	1			T7	3		T25	27		T26	3
valid_sources[0x38]	827	1			T5	7		T42	2		T7	1
valid_sources[0x39]	727	1			T5	1		T6	1		T151	1
valid_sources[0x3a]	678	1			T42	3		T25	29		T26	4
valid_sources[0x3b]	917	1			T5	9		T42	1		T56	1
valid_sources[0x3c]	759	1			T4	5		T5	4		T42	3
valid_sources[0x3d]	858	1			T1	1		T5	7		T7	1
valid_sources[0x3e]	1241	1			T7	1		T56	1		T58	1
valid_sources[0x3f]	992	1			T5	2		T42	1		T7	2
valid_sources[0x40]	703	1			T5	11		T25	15		T26	5
valid_sources[0x41]	698	1			T5	2		T7	1		T27	1
valid_sources[0x42]	1135	1			T5	14		T42	3		T7	1
valid_sources[0x43]	613	1			T6	1		T42	2		T21	6
valid_sources[0x44]	1197	1			T6	1		T40	2		T42	2
valid_sources[0x45]	1116	1			T11	5		T8	1		T25	15
valid_sources[0x46]	559	1			T5	6		T42	2		T7	1
valid_sources[0x47]	984	1			T42	2		T7	1		T140	6
valid_sources[0x48]	883	1			T42	1		T7	1		T102	3
valid_sources[0x49]	682	1			T42	1		T58	1		T21	1
valid_sources[0x4a]	710	1			T56	1		T25	24		T26	3
valid_sources[0x4b]	917	1			T5	18		T42	1		T7	2
valid_sources[0x4c]	803	1			T5	2		T42	2		T7	1
valid_sources[0x4d]	685	1			T1	1		T42	3		T27	2
valid_sources[0x4e]	1156	1			T5	10		T42	2		T7	1
valid_sources[0x4f]	825	1			T1	1		T42	3		T9	31
valid_sources[0x50]	690	1			T4	1		T5	3		T13	1
valid_sources[0x51]	706	1			T5	1		T6	1		T13	1
valid_sources[0x52]	645	1			T5	9		T42	2		T141	5
valid_sources[0x53]	536	1			T5	13		T27	2		T21	1
valid_sources[0x54]	568	1			T6	1		T42	1		T7	1
valid_sources[0x55]	716	1			T5	1		T40	1		T7	1
valid_sources[0x56]	720	1			T42	2		T7	1		T100	2
valid_sources[0x57]	836	1			T5	5		T27	1		T79	3
valid_sources[0x58]	729	1			T42	4		T7	1		T83	1
valid_sources[0x59]	742	1			T5	1		T42	1		T7	1
valid_sources[0x5a]	694	1			T5	1		T42	3		T151	1
valid_sources[0x5b]	733	1			T5	3		T40	1		T42	1
valid_sources[0x5c]	608	1			T5	5		T42	3		T25	15
valid_sources[0x5d]	863	1			T5	2		T42	6		T7	2
valid_sources[0x5e]	669	1			T6	2		T42	5		T7	2
valid_sources[0x5f]	643	1			T25	15		T67	1		T69	1
valid_sources[0x60]	799	1			T1	1		T42	2		T7	3
valid_sources[0x61]	799	1			T5	3		T7	2		T20	28
valid_sources[0x62]	917	1			T5	6		T78	4		T155	1
valid_sources[0x63]	922	1			T5	4		T25	29		T26	3
valid_sources[0x64]	770	1			T5	12		T6	1		T42	1
valid_sources[0x65]	858	1			T5	9		T40	1		T7	1
valid_sources[0x66]	791	1			T5	5		T42	2		T25	14
valid_sources[0x67]	644	1			T1	1		T5	12		T27	1
valid_sources[0x68]	1379	1			T5	1		T42	5		T43	210
valid_sources[0x69]	701	1			T42	2		T7	1		T21	11
valid_sources[0x6a]	598	1			T5	8		T6	4		T8	1
valid_sources[0x6b]	745	1			T42	1		T7	3		T27	2
valid_sources[0x6c]	792	1			T5	12		T42	1		T25	14
valid_sources[0x6d]	874	1			T5	6		T42	2		T25	19
valid_sources[0x6e]	1542	1			T42	3		T95	1		T83	1
valid_sources[0x6f]	979	1			T7	2		T140	23		T95	1
valid_sources[0x70]	788	1			T5	8		T42	1		T7	1
valid_sources[0x71]	777	1			T5	2		T40	1		T27	1
valid_sources[0x72]	854	1			T5	21		T6	1		T42	2
valid_sources[0x73]	691	1			T5	2		T7	1		T119	1
valid_sources[0x74]	866	1			T6	2		T42	1		T7	1
valid_sources[0x75]	778	1			T5	5		T7	1		T101	2
valid_sources[0x76]	778	1			T5	2		T40	1		T42	3
valid_sources[0x77]	795	1			T5	4		T42	2		T7	2
valid_sources[0x78]	906	1			T5	1		T6	3		T42	1
valid_sources[0x79]	1179	1			T40	1		T42	1		T7	2
valid_sources[0x7a]	744	1			T5	1		T42	4		T44	3
valid_sources[0x7b]	777	1			T42	2		T7	2		T58	1
valid_sources[0x7c]	616	1			T11	6		T6	1		T23	5
valid_sources[0x7d]	866	1			T1	2		T42	2		T7	1
valid_sources[0x7e]	1464	1			T42	6		T7	3		T8	2
valid_sources[0x7f]	940	1			T21	1		T143	26		T25	30
valid_sources[0x80]	754	1			T7	1		T152	1		T25	21

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

43852

1

T5

199

T6

7

T7

35

values[0x0]

all_enables

biggest_size

61777

1

T1

4

T4

1

T11

15

values[0x1]

all_enables

biggest_size

59091

1

T1

1

T11

5

T5

250