Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16026149

1

T1

13089

T2

154

T4

23903

full_word

151368096

1

T1

130763

T2

1391

T3

705

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	167393915	1			T1	143852		T2	1545		T3	705
auto[TlIntgErrCmd]	111	1			T73	5		T74	6		T75	7
auto[TlIntgErrData]	126	1			T73	1		T74	7		T75	8
auto[TlIntgErrBoth]	93	1			T73	4		T74	7		T75	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

80605781

1

T1

71989

T2

771

T3

335

auto[1]

86788464

1

T1

71863

T2

774

T3

370

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7832471	1			T1	6541		T2	72		T4	12010
auto[TlIntgErrNone]	partial	auto[1]	8193374	1			T1	6548		T2	82		T4	11893
auto[TlIntgErrNone]	full_word	auto[0]	72773168	1			T1	65448		T2	699		T3	335
auto[TlIntgErrNone]	full_word	auto[1]	78594902	1			T1	65315		T2	692		T3	370
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T74	4		T75	5		T129	1
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T73	4		T74	2		T129	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T73	1		T129	1		T134	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T75	2		T130	1		T137	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T73	1		T74	3		T75	3
auto[TlIntgErrData]	partial	auto[1]	64	1			T74	3		T75	4		T129	1
auto[TlIntgErrData]	full_word	auto[0]	10	1			T74	1		T129	1		T136	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T75	1		T138	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	31	1			T73	2		T74	5		T75	1
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T73	2		T74	2		T75	4
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T139	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T133	1		T137	1		-	-