Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	800330	1			T2	2		T6	1326		T23	11
auto[1]	10731829	1			T1	13958		T2	38		T3	335
auto[2]	611095	1			T2	2		T6	1183		T23	5
auto[3]	10493658	1			T1	13835		T2	48		T3	369

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14277495	1			T1	23080		T2	58		T3	704
auto[1]	2119888	1			T1	2220		T2	10		T4	17289
auto[2]	2159997	1			T1	2252		T2	20		T4	17433
auto[3]	4079532	1			T1	241		T2	2		T4	1639

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9273789

1

T1

27792

T2

90

T3

704

auto[1]

13363123

1

T1

1

T4

219331

T40

2

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	337520	1			T2	2		T6	1091		T23	9
auto[0]	auto[0]	auto[1]	34914	1			T6	111		T7	110		T27	211
auto[0]	auto[0]	auto[2]	34789	1			T6	115		T23	2		T7	123
auto[0]	auto[0]	auto[3]	49961	1			T6	9		T7	11		T27	25
auto[0]	auto[1]	auto[0]	3255925	1			T1	11590		T2	27		T3	335
auto[0]	auto[1]	auto[1]	345336	1			T1	1104		T2	8		T6	106
auto[0]	auto[1]	auto[2]	358282	1			T1	1135		T2	3		T6	25
auto[0]	auto[1]	auto[3]	357610	1			T1	128		T6	16		T13	114
auto[0]	auto[2]	auto[0]	252447	1			T6	972		T7	480		T27	1152
auto[0]	auto[2]	auto[1]	28482	1			T6	104		T7	54		T27	128
auto[0]	auto[2]	auto[2]	28364	1			T2	1		T6	98		T23	5
auto[0]	auto[2]	auto[3]	34930	1			T2	1		T6	9		T7	8
auto[0]	auto[3]	auto[0]	3132575	1			T1	11489		T2	29		T3	369
auto[0]	auto[3]	auto[1]	341960	1			T1	1116		T2	2		T6	3
auto[0]	auto[3]	auto[2]	357396	1			T1	1117		T2	16		T6	80
auto[0]	auto[3]	auto[3]	323298	1			T1	113		T2	1		T6	6
auto[1]	auto[0]	auto[0]	11335	1			T56	138		T146	345		T147	2
auto[1]	auto[0]	auto[1]	51098	1			T56	621		T146	1680		T148	3397
auto[1]	auto[0]	auto[2]	50872	1			T56	636		T146	1671		T148	3569
auto[1]	auto[0]	auto[3]	229841	1			T56	2918		T105	2		T146	7581
auto[1]	auto[1]	auto[0]	3643338	1			T1	1		T4	91481		T40	2
auto[1]	auto[1]	auto[1]	657233	1			T4	8170		T56	2204		T59	4347
auto[1]	auto[1]	auto[2]	641760	1			T4	9185		T56	1197		T59	4858
auto[1]	auto[1]	auto[3]	1472345	1			T4	836		T56	9829		T59	422
auto[1]	auto[2]	auto[0]	7657	1			T146	215		T147	1		T148	720
auto[1]	auto[2]	auto[1]	34344	1			T146	977		T148	3122		T149	4745
auto[1]	auto[2]	auto[2]	40811	1			T56	562		T146	1556		T148	2266
auto[1]	auto[2]	auto[3]	184060	1			T56	2610		T146	7187		T148	10448
auto[1]	auto[3]	auto[0]	3636698	1			T4	91489		T41	1		T56	104
auto[1]	auto[3]	auto[1]	626521	1			T4	9119		T56	528		T59	4852
auto[1]	auto[3]	auto[2]	647723	1			T4	8248		T56	2063		T59	4306
auto[1]	auto[3]	auto[3]	1427487	1			T4	803		T56	9692		T59	430