Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1156635426	242376	0	0
ctrl_regwen_rd_A	1156635426	4184	0	0
exec_rd_A	1156635426	4082	0	0
exec_regwen_rd_A	1156635426	4396	0	0
readback_rd_A	1156635426	2757	0	0
readback_regwen_rd_A	1156635426	2204	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1156635426	242376	0	0
T5	29003	1256	0	0
T6	127565	0	0	0
T7	172486	0	0	0
T12	37107	0	0	0
T13	439964	0	0	0
T23	480082	0	0	0
T24	150090	0	0	0
T25	0	7284	0	0
T26	0	2454	0	0
T40	134014	0	0	0
T41	72376	0	0	0
T42	206864	0	0	0
T50	0	4327	0	0
T55	0	6401	0	0
T61	0	3099	0	0
T62	0	4104	0	0
T80	0	3444	0	0
T81	0	3600	0	0
T82	0	6485	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1156635426	4184	0	0
T5	29003	13	0	0
T6	127565	0	0	0
T7	172486	0	0	0
T12	37107	0	0	0
T13	439964	0	0	0
T23	480082	0	0	0
T24	150090	0	0	0
T40	134014	0	0	0
T41	72376	0	0	0
T42	206864	0	0	0
T50	0	222	0	0
T80	0	235	0	0
T121	0	148	0	0
T122	0	70	0	0
T123	0	115	0	0
T124	0	434	0	0
T125	0	77	0	0
T126	0	322	0	0
T127	0	276	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1156635426	4082	0	0
T5	29003	59	0	0
T6	127565	0	0	0
T7	172486	0	0	0
T12	37107	0	0	0
T13	439964	0	0	0
T23	480082	0	0	0
T24	150090	0	0	0
T40	134014	0	0	0
T41	72376	0	0	0
T42	206864	0	0	0
T50	0	195	0	0
T80	0	197	0	0
T121	0	194	0	0
T122	0	64	0	0
T123	0	121	0	0
T124	0	342	0	0
T125	0	70	0	0
T126	0	364	0	0
T127	0	204	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1156635426	4396	0	0
T5	29003	61	0	0
T6	127565	0	0	0
T7	172486	0	0	0
T12	37107	0	0	0
T13	439964	0	0	0
T23	480082	0	0	0
T24	150090	0	0	0
T40	134014	0	0	0
T41	72376	0	0	0
T42	206864	0	0	0
T50	0	245	0	0
T80	0	261	0	0
T121	0	162	0	0
T122	0	31	0	0
T123	0	128	0	0
T124	0	383	0	0
T125	0	82	0	0
T126	0	369	0	0
T127	0	207	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1156635426	2757	0	0
T5	29003	42	0	0
T6	127565	0	0	0
T7	172486	0	0	0
T12	37107	0	0	0
T13	439964	0	0	0
T23	480082	0	0	0
T24	150090	0	0	0
T40	134014	0	0	0
T41	72376	0	0	0
T42	206864	0	0	0
T50	0	219	0	0
T80	0	224	0	0
T121	0	193	0	0
T122	0	59	0	0
T123	0	96	0	0
T124	0	386	0	0
T125	0	98	0	0
T126	0	307	0	0
T127	0	226	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1156635426	2204	0	0
T5	29003	52	0	0
T6	127565	0	0	0
T7	172486	0	0	0
T12	37107	0	0	0
T13	439964	0	0	0
T23	480082	0	0	0
T24	150090	0	0	0
T40	134014	0	0	0
T41	72376	0	0	0
T42	206864	0	0	0
T50	0	197	0	0
T80	0	161	0	0
T121	0	226	0	0
T122	0	68	0	0
T123	0	104	0	0
T124	0	267	0	0
T125	0	99	0	0
T126	0	306	0	0
T127	0	149	0	0