Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15719283	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

152009376

1

T1

1129

T2

2414

T3

79385

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	82598983	1			T1	614		T2	1312		T3	43690
values[0x0]	41009638	1			T1	315		T2	654		T3	20919
values[0x1]	44120038	1			T1	308		T2	675		T3	22688

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8000122	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

159728537

1

T1

1179

T2

2536

T3

83379

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	574534	1			T7	40		T4	33		T9	17
valid_sources[0x01]	597658	1			T7	16		T4	8		T9	23
valid_sources[0x02]	701674	1			T7	37		T4	37		T9	29
valid_sources[0x03]	635691	1			T7	34		T4	27		T9	14
valid_sources[0x04]	636317	1			T7	23		T4	79		T9	16
valid_sources[0x05]	593745	1			T3	3143		T7	26		T4	57
valid_sources[0x06]	585653	1			T7	29		T4	16		T9	18
valid_sources[0x07]	578272	1			T7	26		T4	50		T9	10
valid_sources[0x08]	615708	1			T7	31		T4	44		T9	9
valid_sources[0x09]	662763	1			T7	25		T4	41		T9	19
valid_sources[0x0a]	587679	1			T7	26		T4	70		T9	12
valid_sources[0x0b]	569200	1			T3	935		T7	34		T4	25
valid_sources[0x0c]	589933	1			T2	9		T7	19		T4	20
valid_sources[0x0d]	588570	1			T7	24		T9	9		T11	10
valid_sources[0x0e]	611513	1			T7	22		T4	8		T9	32
valid_sources[0x0f]	637500	1			T2	13		T7	22		T4	80
valid_sources[0x10]	589255	1			T2	27		T7	23		T4	52
valid_sources[0x11]	589573	1			T7	24		T4	6		T9	11
valid_sources[0x12]	565453	1			T7	32		T4	26		T9	30
valid_sources[0x13]	595510	1			T1	619		T2	26		T7	23
valid_sources[0x14]	611607	1			T7	28		T4	80		T9	8
valid_sources[0x15]	698323	1			T7	29		T4	18		T9	24
valid_sources[0x16]	557589	1			T7	33		T4	1		T9	24
valid_sources[0x17]	605864	1			T7	26		T4	71		T9	9
valid_sources[0x18]	579943	1			T7	29		T4	16		T9	6
valid_sources[0x19]	646068	1			T7	33		T4	13		T9	10
valid_sources[0x1a]	591465	1			T2	49		T7	24		T4	1
valid_sources[0x1b]	580546	1			T7	26		T4	15		T9	3
valid_sources[0x1c]	556248	1			T7	31		T4	38		T9	21
valid_sources[0x1d]	607065	1			T7	32		T4	58		T9	37
valid_sources[0x1e]	561890	1			T7	29		T9	10		T11	2
valid_sources[0x1f]	592764	1			T7	29		T4	69		T9	35
valid_sources[0x20]	593701	1			T2	21		T7	24		T4	58
valid_sources[0x21]	603069	1			T7	18		T4	15		T9	19
valid_sources[0x22]	560208	1			T7	29		T4	46		T9	3
valid_sources[0x23]	611648	1			T3	1532		T7	34		T4	60
valid_sources[0x24]	638021	1			T7	27		T4	73		T9	27
valid_sources[0x25]	582890	1			T7	29		T4	25		T9	4
valid_sources[0x26]	607366	1			T7	28		T4	57		T11	4
valid_sources[0x27]	566062	1			T7	29		T4	33		T9	9
valid_sources[0x28]	631655	1			T7	23		T4	16		T9	27
valid_sources[0x29]	614105	1			T7	29		T4	37		T9	16
valid_sources[0x2a]	568690	1			T2	62		T7	29		T4	45
valid_sources[0x2b]	585225	1			T7	35		T4	56		T9	8
valid_sources[0x2c]	764866	1			T2	20		T7	24		T4	20
valid_sources[0x2d]	566642	1			T7	30		T4	25		T9	10
valid_sources[0x2e]	589123	1			T7	30		T4	25		T9	18
valid_sources[0x2f]	575878	1			T7	28		T4	78		T9	17
valid_sources[0x30]	610770	1			T7	32		T4	109		T9	15
valid_sources[0x31]	585404	1			T2	19		T7	26		T4	132
valid_sources[0x32]	578537	1			T7	23		T4	33		T9	4
valid_sources[0x33]	1800780	1			T2	48		T7	44		T9	1
valid_sources[0x34]	621211	1			T2	19		T3	46546		T7	29
valid_sources[0x35]	614453	1			T2	35		T7	24		T4	24
valid_sources[0x36]	617330	1			T7	33		T4	5		T9	2
valid_sources[0x37]	646901	1			T7	25		T4	15		T9	16
valid_sources[0x38]	562928	1			T7	32		T4	7		T9	10
valid_sources[0x39]	559621	1			T7	30		T4	78		T9	25
valid_sources[0x3a]	555453	1			T2	7		T7	33		T4	51
valid_sources[0x3b]	582259	1			T7	27		T4	34		T9	17
valid_sources[0x3c]	607560	1			T2	11		T7	30		T4	21
valid_sources[0x3d]	681295	1			T2	13		T7	34		T4	79
valid_sources[0x3e]	574936	1			T2	33		T7	25		T4	30
valid_sources[0x3f]	572821	1			T7	33		T4	32		T9	12
valid_sources[0x40]	568171	1			T2	12		T7	23		T4	50
valid_sources[0x41]	563141	1			T2	16		T7	37		T9	15
valid_sources[0x42]	558185	1			T7	21		T4	46		T9	14
valid_sources[0x43]	591527	1			T2	10		T7	25		T4	21
valid_sources[0x44]	630282	1			T2	15		T7	31		T4	59
valid_sources[0x45]	575719	1			T7	30		T4	19		T9	19
valid_sources[0x46]	589040	1			T7	19		T4	74		T9	21
valid_sources[0x47]	596171	1			T7	30		T4	33		T9	10
valid_sources[0x48]	1264599	1			T2	140		T7	34		T4	45
valid_sources[0x49]	603245	1			T7	19		T4	80		T9	25
valid_sources[0x4a]	565755	1			T7	38		T4	29		T9	7
valid_sources[0x4b]	610465	1			T7	29		T4	130		T9	11
valid_sources[0x4c]	627242	1			T7	35		T4	54		T9	33
valid_sources[0x4d]	600606	1			T7	20		T4	85		T9	4
valid_sources[0x4e]	563338	1			T7	25		T4	14		T9	9
valid_sources[0x4f]	572205	1			T7	29		T4	27		T9	12
valid_sources[0x50]	600990	1			T7	28		T4	17		T9	12
valid_sources[0x51]	583204	1			T2	7		T7	32		T4	75
valid_sources[0x52]	607810	1			T7	27		T4	22		T9	9
valid_sources[0x53]	585687	1			T7	36		T4	32		T9	10
valid_sources[0x54]	576189	1			T2	78		T7	11		T4	16
valid_sources[0x55]	567161	1			T2	81		T3	3726		T7	30
valid_sources[0x56]	734844	1			T7	29		T4	11		T9	18
valid_sources[0x57]	609649	1			T7	29		T4	15		T9	4
valid_sources[0x58]	593557	1			T7	34		T4	15		T9	19
valid_sources[0x59]	586175	1			T7	27		T9	25		T11	14
valid_sources[0x5a]	559871	1			T7	39		T4	129		T9	28
valid_sources[0x5b]	613900	1			T2	10		T7	19		T9	16
valid_sources[0x5c]	1590193	1			T3	1460		T7	33		T9	28
valid_sources[0x5d]	584972	1			T7	23		T4	15		T9	16
valid_sources[0x5e]	678283	1			T7	38		T4	15		T9	13
valid_sources[0x5f]	555279	1			T7	27		T4	39		T9	13
valid_sources[0x60]	2214418	1			T7	33		T4	54		T9	25
valid_sources[0x61]	1407205	1			T7	39		T4	48		T9	12
valid_sources[0x62]	619795	1			T7	27		T4	108		T9	17
valid_sources[0x63]	574916	1			T7	29		T4	57		T9	40
valid_sources[0x64]	620295	1			T2	15		T7	19		T4	41
valid_sources[0x65]	622393	1			T2	49		T7	38		T4	4
valid_sources[0x66]	570752	1			T2	94		T3	4515		T7	16
valid_sources[0x67]	563478	1			T2	29		T7	32		T4	52
valid_sources[0x68]	558228	1			T2	52		T7	27		T4	45
valid_sources[0x69]	573191	1			T2	38		T7	36		T4	1
valid_sources[0x6a]	582027	1			T7	33		T4	18		T9	25
valid_sources[0x6b]	579110	1			T7	30		T4	121		T9	14
valid_sources[0x6c]	624913	1			T7	29		T4	9		T9	26
valid_sources[0x6d]	576935	1			T2	16		T7	27		T9	28
valid_sources[0x6e]	582190	1			T7	20		T4	26		T9	30
valid_sources[0x6f]	624287	1			T2	19		T7	33		T4	87
valid_sources[0x70]	586651	1			T7	31		T4	8		T9	5
valid_sources[0x71]	567091	1			T2	8		T7	38		T4	21
valid_sources[0x72]	557351	1			T7	22		T4	48		T9	16
valid_sources[0x73]	580349	1			T2	7		T7	34		T9	2
valid_sources[0x74]	627503	1			T7	31		T4	49		T9	23
valid_sources[0x75]	577551	1			T2	145		T7	30		T4	75
valid_sources[0x76]	576931	1			T2	2		T7	34		T4	24
valid_sources[0x77]	584774	1			T7	33		T4	79		T9	15
valid_sources[0x78]	564674	1			T2	202		T7	28		T9	22
valid_sources[0x79]	631691	1			T2	58		T7	30		T4	15
valid_sources[0x7a]	1392688	1			T7	34		T4	63		T9	16
valid_sources[0x7b]	614022	1			T7	19		T4	25		T9	15
valid_sources[0x7c]	566746	1			T7	24		T4	50		T9	39
valid_sources[0x7d]	573185	1			T7	27		T4	26		T9	3
valid_sources[0x7e]	596232	1			T2	13		T7	32		T4	44
valid_sources[0x7f]	636768	1			T7	25		T4	37		T9	6
valid_sources[0x80]	558721	1			T7	25		T4	46		T9	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

74697074

1

T1

558

T2

1203

T3

39813

values[0x0]

all_enables

biggest_size

38663477

1

T1

297

T2

618

T3

19702

values[0x1]

all_enables

biggest_size

38648825

1

T1

274

T2

593

T3

19870

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44241	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

150895

1

T2

20

T3

3

T7

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	53856	1			T2	22		T11	813		T21	256
values[0x0]	68221	1			T2	9		T3	10		T7	2
values[0x1]	73059	1			T1	1		T2	8		T3	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34118	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

161018

1

T2

23

T3

7

T7

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	642	1			T11	5		T21	2		T22	5
valid_sources[0x01]	788	1			T11	22		T21	2		T22	2
valid_sources[0x02]	649	1			T11	3		T21	11		T22	13
valid_sources[0x03]	650	1			T11	3		T21	2		T22	6
valid_sources[0x04]	904	1			T11	14		T21	9		T22	8
valid_sources[0x05]	628	1			T11	8		T21	4		T22	10
valid_sources[0x06]	784	1			T11	15		T21	6		T22	6
valid_sources[0x07]	642	1			T11	14		T21	10		T22	9
valid_sources[0x08]	716	1			T11	5		T21	3		T22	6
valid_sources[0x09]	552	1			T11	17		T21	3		T22	8
valid_sources[0x0a]	805	1			T11	16		T21	6		T22	10
valid_sources[0x0b]	1036	1			T11	16		T21	3		T22	13
valid_sources[0x0c]	828	1			T3	1		T11	49		T21	1
valid_sources[0x0d]	679	1			T11	5		T21	18		T22	9
valid_sources[0x0e]	884	1			T11	49		T21	5		T22	7
valid_sources[0x0f]	1022	1			T11	3		T21	7		T22	14
valid_sources[0x10]	636	1			T11	4		T21	3		T22	14
valid_sources[0x11]	632	1			T3	1		T11	25		T21	2
valid_sources[0x12]	864	1			T11	19		T21	6		T22	6
valid_sources[0x13]	668	1			T11	28		T21	6		T22	4
valid_sources[0x14]	672	1			T11	1		T21	2		T22	11
valid_sources[0x15]	644	1			T11	19		T21	5		T22	3
valid_sources[0x16]	1053	1			T11	5		T21	3		T22	12
valid_sources[0x17]	588	1			T11	7		T21	4		T22	9
valid_sources[0x18]	785	1			T21	1		T22	21		T6	3
valid_sources[0x19]	953	1			T7	1		T11	21		T21	3
valid_sources[0x1a]	805	1			T11	5		T21	4		T22	6
valid_sources[0x1b]	614	1			T3	1		T11	4		T21	3
valid_sources[0x1c]	557	1			T8	2		T21	6		T22	11
valid_sources[0x1d]	664	1			T11	8		T21	1		T22	4
valid_sources[0x1e]	856	1			T11	17		T21	7		T22	6
valid_sources[0x1f]	647	1			T11	12		T21	9		T22	3
valid_sources[0x20]	606	1			T11	9		T21	2		T22	5
valid_sources[0x21]	546	1			T11	2		T21	3		T22	5
valid_sources[0x22]	755	1			T11	6		T21	13		T22	8
valid_sources[0x23]	586	1			T11	4		T22	19		T71	4
valid_sources[0x24]	593	1			T11	7		T21	2		T22	4
valid_sources[0x25]	659	1			T11	1		T22	4		T20	1
valid_sources[0x26]	1105	1			T11	15		T21	1		T22	3
valid_sources[0x27]	1185	1			T11	10		T21	7		T22	7
valid_sources[0x28]	601	1			T2	1		T11	10		T21	4
valid_sources[0x29]	883	1			T11	15		T21	10		T22	6
valid_sources[0x2a]	597	1			T11	13		T21	7		T22	6
valid_sources[0x2b]	743	1			T11	9		T21	1		T22	10
valid_sources[0x2c]	877	1			T11	24		T21	10		T22	6
valid_sources[0x2d]	674	1			T11	5		T21	1		T22	9
valid_sources[0x2e]	912	1			T11	4		T21	6		T22	6
valid_sources[0x2f]	761	1			T11	4		T21	1		T22	6
valid_sources[0x30]	710	1			T8	1		T11	38		T21	6
valid_sources[0x31]	725	1			T1	1		T11	6		T21	7
valid_sources[0x32]	889	1			T3	1		T11	31		T21	6
valid_sources[0x33]	781	1			T11	3		T21	1		T22	11
valid_sources[0x34]	600	1			T21	4		T22	9		T68	1
valid_sources[0x35]	897	1			T11	1		T21	5		T22	3
valid_sources[0x36]	671	1			T11	3		T21	3		T22	7
valid_sources[0x37]	910	1			T11	13		T21	6		T22	2
valid_sources[0x38]	982	1			T11	1		T21	6		T22	3
valid_sources[0x39]	964	1			T11	2		T21	4		T22	14
valid_sources[0x3a]	860	1			T11	8		T21	11		T22	5
valid_sources[0x3b]	760	1			T11	9		T21	7		T22	6
valid_sources[0x3c]	681	1			T11	18		T21	1		T22	8
valid_sources[0x3d]	906	1			T11	14		T21	3		T22	13
valid_sources[0x3e]	837	1			T11	9		T21	1		T22	9
valid_sources[0x3f]	710	1			T11	13		T21	4		T22	9
valid_sources[0x40]	949	1			T21	8		T22	6		T68	1
valid_sources[0x41]	588	1			T11	13		T21	2		T22	8
valid_sources[0x42]	593	1			T11	3		T21	7		T22	7
valid_sources[0x43]	642	1			T11	18		T22	8		T20	3
valid_sources[0x44]	751	1			T11	5		T21	7		T22	8
valid_sources[0x45]	615	1			T11	6		T21	1		T22	8
valid_sources[0x46]	580	1			T11	4		T22	4		T6	4
valid_sources[0x47]	770	1			T11	27		T21	1		T22	11
valid_sources[0x48]	973	1			T11	1		T21	5		T22	12
valid_sources[0x49]	712	1			T11	11		T22	5		T23	1
valid_sources[0x4a]	796	1			T11	12		T21	3		T22	10
valid_sources[0x4b]	883	1			T11	3		T22	9		T5	5
valid_sources[0x4c]	674	1			T11	3		T22	3		T23	1
valid_sources[0x4d]	956	1			T11	18		T21	1		T22	15
valid_sources[0x4e]	743	1			T11	10		T21	5		T22	4
valid_sources[0x4f]	686	1			T8	2		T11	16		T22	11
valid_sources[0x50]	781	1			T11	9		T21	4		T22	11
valid_sources[0x51]	652	1			T11	21		T21	1		T22	6
valid_sources[0x52]	605	1			T2	1		T11	13		T21	1
valid_sources[0x53]	1043	1			T11	3		T21	3		T22	8
valid_sources[0x54]	658	1			T11	18		T21	9		T22	3
valid_sources[0x55]	649	1			T11	57		T12	1		T21	9
valid_sources[0x56]	1052	1			T11	10		T21	1		T22	8
valid_sources[0x57]	585	1			T11	29		T21	9		T22	5
valid_sources[0x58]	642	1			T11	16		T21	4		T22	3
valid_sources[0x59]	805	1			T11	3		T21	6		T22	11
valid_sources[0x5a]	615	1			T11	4		T21	3		T22	5
valid_sources[0x5b]	642	1			T11	4		T21	9		T22	5
valid_sources[0x5c]	714	1			T2	3		T11	2		T21	1
valid_sources[0x5d]	641	1			T11	20		T21	4		T22	7
valid_sources[0x5e]	899	1			T11	7		T21	3		T22	10
valid_sources[0x5f]	618	1			T11	1		T21	5		T22	9
valid_sources[0x60]	1034	1			T11	24		T21	4		T22	7
valid_sources[0x61]	738	1			T11	6		T22	5		T20	1
valid_sources[0x62]	633	1			T11	15		T21	2		T22	8
valid_sources[0x63]	994	1			T3	1		T11	7		T21	1
valid_sources[0x64]	759	1			T11	7		T21	6		T22	3
valid_sources[0x65]	823	1			T11	5		T21	2		T22	6
valid_sources[0x66]	1240	1			T11	16		T21	3		T22	2
valid_sources[0x67]	847	1			T11	3		T21	1		T22	5
valid_sources[0x68]	677	1			T11	2		T21	2		T24	1
valid_sources[0x69]	662	1			T11	1		T21	7		T22	8
valid_sources[0x6a]	624	1			T3	1		T11	20		T21	6
valid_sources[0x6b]	716	1			T8	1		T11	10		T21	4
valid_sources[0x6c]	991	1			T11	6		T21	6		T22	8
valid_sources[0x6d]	1215	1			T11	12		T21	1		T22	7
valid_sources[0x6e]	633	1			T11	21		T21	1		T22	6
valid_sources[0x6f]	885	1			T11	23		T21	2		T22	7
valid_sources[0x70]	825	1			T11	24		T21	5		T22	10
valid_sources[0x71]	703	1			T11	25		T21	5		T22	5
valid_sources[0x72]	629	1			T11	16		T21	8		T22	10
valid_sources[0x73]	750	1			T11	7		T21	4		T22	13
valid_sources[0x74]	1123	1			T11	11		T21	2		T22	9
valid_sources[0x75]	758	1			T11	3		T21	3		T22	8
valid_sources[0x76]	606	1			T11	7		T21	1		T22	8
valid_sources[0x77]	754	1			T11	18		T21	1		T22	5
valid_sources[0x78]	1009	1			T11	10		T21	2		T22	14
valid_sources[0x79]	935	1			T21	2		T22	9		T48	5
valid_sources[0x7a]	677	1			T11	15		T21	3		T22	7
valid_sources[0x7b]	655	1			T7	1		T11	6		T21	4
valid_sources[0x7c]	706	1			T11	17		T21	2		T22	13
valid_sources[0x7d]	762	1			T11	7		T21	2		T22	7
valid_sources[0x7e]	729	1			T11	2		T21	5		T22	13
valid_sources[0x7f]	1117	1			T11	21		T12	1		T21	6
valid_sources[0x80]	910	1			T11	40		T21	5		T22	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

40769

1

T2

13

T11

746

T21

234

values[0x0]

all_enables

biggest_size

56557

1

T2

5

T3

1

T7

1

values[0x1]

all_enables

biggest_size

53569

1

T2

2

T3

2

T11

969