Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15623733

1

T1

108

T2

88

T3

7912

full_word

148918828

1

T1

1129

T2

984

T3

79385

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	164542261	1			T1	1237		T2	1072		T3	87297
auto[TlIntgErrCmd]	99	1			T65	4		T66	4		T67	3
auto[TlIntgErrData]	95	1			T65	2		T66	2		T67	4
auto[TlIntgErrBoth]	106	1			T65	4		T66	4		T67	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

79328818

1

T1

614

T2

521

T3

43690

auto[1]

85213743

1

T1

623

T2

551

T3

43607

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7644066	1			T1	56		T2	45		T3	3877
auto[TlIntgErrNone]	partial	auto[1]	7979390	1			T1	52		T2	43		T3	4035
auto[TlIntgErrNone]	full_word	auto[0]	71684619	1			T1	558		T2	476		T3	39813
auto[TlIntgErrNone]	full_word	auto[1]	77234186	1			T1	571		T2	508		T3	39572
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T65	1		T66	4		T67	1
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T65	3		T67	2		T120	5
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T121	1		T122	1		T123	2
auto[TlIntgErrData]	partial	auto[0]	47	1			T65	1		T66	2		T67	2
auto[TlIntgErrData]	partial	auto[1]	38	1			T65	1		T67	2		T124	3
auto[TlIntgErrData]	full_word	auto[0]	7	1			T124	2		T125	1		T121	2
auto[TlIntgErrData]	full_word	auto[1]	3	1			T124	1		T121	1		T126	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T66	1		T67	1		T120	3
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T65	4		T66	3		T67	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T127	2		T128	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T129	1		T127	2		T122	1