Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	704327	1			T41	2729		T42	54		T18	3851
auto[1]	10933924	1			T1	604		T2	484		T3	20613
auto[2]	533591	1			T41	1963		T42	23		T18	2203
auto[3]	10643925	1			T1	616		T2	510		T3	20549

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14405927	1			T1	1039		T2	854		T3	34294
auto[1]	2133286	1			T1	80		T2	65		T3	3278
auto[2]	2175574	1			T1	93		T2	72		T3	3294
auto[3]	4100980	1			T1	8		T2	3		T3	296

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9253524

1

T1

1220

T2

994

T3

41160

auto[1]

13562243

1

T3

2

T4

1

T5

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	282359	1			T42	2		T18	3180		T6	420
auto[0]	auto[0]	auto[1]	29318	1			T42	8		T18	311		T6	44
auto[0]	auto[0]	auto[2]	29324	1			T42	8		T18	323		T6	43
auto[0]	auto[0]	auto[3]	50515	1			T42	36		T18	37		T6	4
auto[0]	auto[1]	auto[0]	3349060	1			T1	514		T2	419		T3	17242
auto[0]	auto[1]	auto[1]	348829	1			T1	36		T2	24		T3	1517
auto[0]	auto[1]	auto[2]	361292	1			T1	52		T2	38		T3	1699
auto[0]	auto[1]	auto[3]	339787	1			T1	2		T2	3		T3	154
auto[0]	auto[2]	auto[0]	200521	1			T18	1892		T20	3568		T40	5
auto[0]	auto[2]	auto[1]	23448	1			T18	163		T20	345		T40	218
auto[0]	auto[2]	auto[2]	24625	1			T42	8		T18	136		T6	297
auto[0]	auto[2]	auto[3]	38123	1			T41	1		T42	15		T18	12
auto[0]	auto[3]	auto[0]	3170655	1			T1	525		T2	435		T3	17051
auto[0]	auto[3]	auto[1]	340217	1			T1	44		T2	41		T3	1761
auto[0]	auto[3]	auto[2]	355400	1			T1	41		T2	34		T3	1594
auto[0]	auto[3]	auto[3]	310051	1			T1	6		T3	142		T4	157
auto[1]	auto[0]	auto[0]	10391	1			T41	90		T136	109		T137	739
auto[1]	auto[0]	auto[1]	46321	1			T41	391		T136	377		T137	3132
auto[1]	auto[0]	auto[2]	46698	1			T41	421		T136	365		T137	3129
auto[1]	auto[0]	auto[3]	209401	1			T41	1827		T40	1		T136	1766
auto[1]	auto[1]	auto[0]	3696248	1			T5	1		T41	169		T43	74501
auto[1]	auto[1]	auto[1]	668473	1			T41	1380		T43	6560		T60	5601
auto[1]	auto[1]	auto[2]	660105	1			T3	1		T4	1		T41	705
auto[1]	auto[1]	auto[3]	1510130	1			T41	6291		T43	681		T60	541
auto[1]	auto[2]	auto[0]	7391	1			T137	626		T31	249		T138	1
auto[1]	auto[2]	auto[1]	32616	1			T137	2898		T31	1070		T138	1
auto[1]	auto[2]	auto[2]	37814	1			T41	375		T136	333		T137	2227
auto[1]	auto[2]	auto[3]	169053	1			T41	1587		T136	1566		T137	9529
auto[1]	auto[3]	auto[0]	3689302	1			T3	1		T41	69		T43	75037
auto[1]	auto[3]	auto[1]	644064	1			T41	355		T43	7399		T60	6375
auto[1]	auto[3]	auto[2]	660316	1			T41	1382		T43	6709		T60	5746
auto[1]	auto[3]	auto[3]	1473920	1			T41	5931		T43	647		T60	572