SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.90 | 100.00 | 88.89 | 100.00 | 100.00 | 70.59 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
89.00 | 100.00 | 100.00 | 100.00 | 95.00 | 50.00 | u_tlul_lc_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.90 | 100.00 | 88.89 | 100.00 | 100.00 | 70.59 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 2697 | 2697 | 0 | 0 |
OutputsKnown_A | 2147483647 | 2147483647 | 0 | 0 |
gen_flops.OutputDelay_A | 2147483647 | 2147483647 | 0 | 5394 |
gen_no_flops.OutputDelay_A | 1089242044 | 1089119091 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2697 | 2697 | 0 | 0 |
T1 | 3 | 3 | 0 | 0 |
T2 | 3 | 3 | 0 | 0 |
T3 | 3 | 3 | 0 | 0 |
T4 | 3 | 3 | 0 | 0 |
T7 | 3 | 3 | 0 | 0 |
T8 | 3 | 3 | 0 | 0 |
T9 | 3 | 3 | 0 | 0 |
T10 | 3 | 3 | 0 | 0 |
T11 | 3 | 3 | 0 | 0 |
T12 | 3 | 3 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 0 |
T1 | 106002 | 105792 | 0 | 0 |
T2 | 1596069 | 1595547 | 0 | 0 |
T3 | 2590017 | 2589774 | 0 | 0 |
T4 | 245247 | 245004 | 0 | 0 |
T7 | 222327 | 222096 | 0 | 0 |
T8 | 4980 | 4827 | 0 | 0 |
T9 | 216039 | 215880 | 0 | 0 |
T10 | 4851 | 4656 | 0 | 0 |
T11 | 223311 | 222951 | 0 | 0 |
T12 | 199584 | 199308 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 5394 |
T1 | 70668 | 70522 | 0 | 6 |
T2 | 1064046 | 1063524 | 0 | 6 |
T3 | 1726678 | 1726510 | 0 | 6 |
T4 | 163498 | 163330 | 0 | 6 |
T7 | 148218 | 148058 | 0 | 6 |
T8 | 3320 | 3212 | 0 | 6 |
T9 | 144026 | 143914 | 0 | 6 |
T10 | 3234 | 3098 | 0 | 6 |
T11 | 148874 | 148568 | 0 | 6 |
T12 | 133056 | 132866 | 0 | 6 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1089242044 | 1089119091 | 0 | 0 |
T1 | 35334 | 35264 | 0 | 0 |
T2 | 532023 | 531849 | 0 | 0 |
T3 | 863339 | 863258 | 0 | 0 |
T4 | 81749 | 81668 | 0 | 0 |
T7 | 74109 | 74032 | 0 | 0 |
T8 | 1660 | 1609 | 0 | 0 |
T9 | 72013 | 71960 | 0 | 0 |
T10 | 1617 | 1552 | 0 | 0 |
T11 | 74437 | 74317 | 0 | 0 |
T12 | 66528 | 66436 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 899 | 899 | 0 | 0 |
OutputsKnown_A | 1089242044 | 1089119091 | 0 | 0 |
gen_flops.OutputDelay_A | 1089242044 | 1089105945 | 0 | 2697 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 899 | 899 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1089242044 | 1089119091 | 0 | 0 |
T1 | 35334 | 35264 | 0 | 0 |
T2 | 532023 | 531849 | 0 | 0 |
T3 | 863339 | 863258 | 0 | 0 |
T4 | 81749 | 81668 | 0 | 0 |
T7 | 74109 | 74032 | 0 | 0 |
T8 | 1660 | 1609 | 0 | 0 |
T9 | 72013 | 71960 | 0 | 0 |
T10 | 1617 | 1552 | 0 | 0 |
T11 | 74437 | 74317 | 0 | 0 |
T12 | 66528 | 66436 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1089242044 | 1089105945 | 0 | 2697 |
T1 | 35334 | 35261 | 0 | 3 |
T2 | 532023 | 531762 | 0 | 3 |
T3 | 863339 | 863255 | 0 | 3 |
T4 | 81749 | 81665 | 0 | 3 |
T7 | 74109 | 74029 | 0 | 3 |
T8 | 1660 | 1606 | 0 | 3 |
T9 | 72013 | 71957 | 0 | 3 |
T10 | 1617 | 1549 | 0 | 3 |
T11 | 74437 | 74284 | 0 | 3 |
T12 | 66528 | 66433 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 899 | 899 | 0 | 0 |
OutputsKnown_A | 1089242044 | 1089119091 | 0 | 0 |
gen_no_flops.OutputDelay_A | 1089242044 | 1089119091 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 899 | 899 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1089242044 | 1089119091 | 0 | 0 |
T1 | 35334 | 35264 | 0 | 0 |
T2 | 532023 | 531849 | 0 | 0 |
T3 | 863339 | 863258 | 0 | 0 |
T4 | 81749 | 81668 | 0 | 0 |
T7 | 74109 | 74032 | 0 | 0 |
T8 | 1660 | 1609 | 0 | 0 |
T9 | 72013 | 71960 | 0 | 0 |
T10 | 1617 | 1552 | 0 | 0 |
T11 | 74437 | 74317 | 0 | 0 |
T12 | 66528 | 66436 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1089242044 | 1089119091 | 0 | 0 |
T1 | 35334 | 35264 | 0 | 0 |
T2 | 532023 | 531849 | 0 | 0 |
T3 | 863339 | 863258 | 0 | 0 |
T4 | 81749 | 81668 | 0 | 0 |
T7 | 74109 | 74032 | 0 | 0 |
T8 | 1660 | 1609 | 0 | 0 |
T9 | 72013 | 71960 | 0 | 0 |
T10 | 1617 | 1552 | 0 | 0 |
T11 | 74437 | 74317 | 0 | 0 |
T12 | 66528 | 66436 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 899 | 899 | 0 | 0 |
OutputsKnown_A | 1089242044 | 1089119091 | 0 | 0 |
gen_flops.OutputDelay_A | 1089242044 | 1089105945 | 0 | 2697 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 899 | 899 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1089242044 | 1089119091 | 0 | 0 |
T1 | 35334 | 35264 | 0 | 0 |
T2 | 532023 | 531849 | 0 | 0 |
T3 | 863339 | 863258 | 0 | 0 |
T4 | 81749 | 81668 | 0 | 0 |
T7 | 74109 | 74032 | 0 | 0 |
T8 | 1660 | 1609 | 0 | 0 |
T9 | 72013 | 71960 | 0 | 0 |
T10 | 1617 | 1552 | 0 | 0 |
T11 | 74437 | 74317 | 0 | 0 |
T12 | 66528 | 66436 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1089242044 | 1089105945 | 0 | 2697 |
T1 | 35334 | 35261 | 0 | 3 |
T2 | 532023 | 531762 | 0 | 3 |
T3 | 863339 | 863255 | 0 | 3 |
T4 | 81749 | 81665 | 0 | 3 |
T7 | 74109 | 74029 | 0 | 3 |
T8 | 1660 | 1606 | 0 | 3 |
T9 | 72013 | 71957 | 0 | 3 |
T10 | 1617 | 1549 | 0 | 3 |
T11 | 74437 | 74284 | 0 | 3 |
T12 | 66528 | 66433 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |