Line Coverage for Module :
prim_sync_reqack_data
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 0 | 0 | |
CONT_ASSIGN | 156 | 0 | 0 | |
ALWAYS | 159 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
93 |
1 |
1 |
153 |
|
unreachable |
156 |
|
unreachable |
159 |
|
unreachable |
160 |
|
unreachable |
162 |
|
unreachable |
Assert Coverage for Module :
prim_sync_reqack_data
Assertion Details
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1089242044 |
8613 |
0 |
0 |
T1 |
35334 |
1 |
0 |
0 |
T2 |
532023 |
17 |
0 |
0 |
T3 |
863339 |
22 |
0 |
0 |
T4 |
81749 |
2 |
0 |
0 |
T7 |
74109 |
2 |
0 |
0 |
T8 |
1660 |
0 |
0 |
0 |
T9 |
72013 |
2 |
0 |
0 |
T10 |
1617 |
0 |
0 |
0 |
T11 |
74437 |
10 |
0 |
0 |
T12 |
66528 |
2 |
0 |
0 |
T21 |
0 |
5 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1089242044 |
8613 |
0 |
0 |
T1 |
35334 |
1 |
0 |
0 |
T2 |
532023 |
17 |
0 |
0 |
T3 |
863339 |
22 |
0 |
0 |
T4 |
81749 |
2 |
0 |
0 |
T7 |
74109 |
2 |
0 |
0 |
T8 |
1660 |
0 |
0 |
0 |
T9 |
72013 |
2 |
0 |
0 |
T10 |
1617 |
0 |
0 |
0 |
T11 |
74437 |
10 |
0 |
0 |
T12 |
66528 |
2 |
0 |
0 |
T21 |
0 |
5 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |