SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
90.00 | 90.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
90.00 | 90.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.10 | 100.00 | 91.30 | 100.00 | gen_normal_fifo.u_fifo_cnt |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
90.00 | 90.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
90.00 | 90.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.10 | 100.00 | 91.30 | 100.00 | gen_normal_fifo.u_fifo_cnt |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
90.00 | 90.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
90.00 | 90.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
83.09 | 100.00 | 82.61 | 66.67 | gen_normal_fifo.u_fifo_cnt |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
90.00 | 90.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
90.00 | 90.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
83.09 | 100.00 | 82.61 | 66.67 | gen_normal_fifo.u_fifo_cnt |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.90 | 100.00 | 88.89 | 100.00 | 100.00 | 70.59 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | gen_normal_fifo.u_fifo_cnt |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | gen_normal_fifo.u_fifo_cnt |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | TOGGLE |
100.00 | 100.00 |
Total | Covered | Percent | |
---|---|---|---|
Totals | 7 | 7 | 100.00 |
Total Bits | 70 | 70 | 100.00 |
Total Bits 0->1 | 35 | 35 | 100.00 |
Total Bits 1->0 | 35 | 35 | 100.00 |
Ports | 7 | 7 | 100.00 |
Port Bits | 70 | 70 | 100.00 |
Port Bits 0->1 | 35 | 35 | 100.00 |
Port Bits 1->0 | 35 | 35 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T11,T21 | Yes | T1,T2,T3 | INPUT |
clr_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
set_i | Unreachable | Unreachable | Unreachable | INPUT | ||
set_cnt_i[14:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
incr_en_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
decr_en_i | Unreachable | Unreachable | Unreachable | INPUT | ||
step_i[14:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
commit_i | Unreachable | Unreachable | Unreachable | INPUT | ||
cnt_o[14:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
cnt_after_commit_o[14:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
err_o | Yes | Yes | T15,T16,T17 | Yes | T15,T16,T17 | OUTPUT |
SCORE | TOGGLE |
90.00 | 90.00 |
SCORE | TOGGLE |
90.00 | 90.00 |
SCORE | TOGGLE |
90.00 | 90.00 |
SCORE | TOGGLE |
90.00 | 90.00 |
SCORE | TOGGLE |
100.00 | 100.00 |
SCORE | TOGGLE |
100.00 | 100.00 |
Total | Covered | Percent | |
---|---|---|---|
Totals | 8 | 8 | 100.00 |
Total Bits | 20 | 20 | 100.00 |
Total Bits 0->1 | 10 | 10 | 100.00 |
Total Bits 1->0 | 10 | 10 | 100.00 |
Ports | 8 | 8 | 100.00 |
Port Bits | 20 | 20 | 100.00 |
Port Bits 0->1 | 10 | 10 | 100.00 |
Port Bits 1->0 | 10 | 10 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T11,T21 | Yes | T1,T2,T3 | INPUT |
clr_i | Unreachable | Unreachable | Unreachable | INPUT | ||
set_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
set_cnt_i[0] | Unreachable | Unreachable | Unreachable | INPUT | ||
set_cnt_i[1] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
incr_en_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
decr_en_i | Unreachable | Unreachable | Unreachable | INPUT | ||
step_i[1:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
commit_i | Unreachable | Unreachable | Unreachable | INPUT | ||
cnt_o[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
cnt_after_commit_o[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
err_o | Yes | Yes | T15,T16,T17 | Yes | T15,T16,T17 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 8 | 7 | 87.50 |
Total Bits | 20 | 18 | 90.00 |
Total Bits 0->1 | 10 | 9 | 90.00 |
Total Bits 1->0 | 10 | 9 | 90.00 |
Ports | 8 | 7 | 87.50 |
Port Bits | 20 | 18 | 90.00 |
Port Bits 0->1 | 10 | 9 | 90.00 |
Port Bits 1->0 | 10 | 9 | 90.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T11,T21 | Yes | T1,T2,T3 | INPUT |
clr_i | Unreachable | Unreachable | Unreachable | INPUT | ||
set_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
set_cnt_i[0] | Unreachable | Unreachable | Unreachable | INPUT | ||
set_cnt_i[1] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
incr_en_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
decr_en_i | Unreachable | Unreachable | Unreachable | INPUT | ||
step_i[1:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
commit_i | Unreachable | Unreachable | Unreachable | INPUT | ||
cnt_o[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
cnt_after_commit_o[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
err_o | No | No | No | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 8 | 7 | 87.50 |
Total Bits | 20 | 18 | 90.00 |
Total Bits 0->1 | 10 | 9 | 90.00 |
Total Bits 1->0 | 10 | 9 | 90.00 |
Ports | 8 | 7 | 87.50 |
Port Bits | 20 | 18 | 90.00 |
Port Bits 0->1 | 10 | 9 | 90.00 |
Port Bits 1->0 | 10 | 9 | 90.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T11,T21 | Yes | T1,T2,T3 | INPUT |
clr_i | Unreachable | Unreachable | Unreachable | INPUT | ||
set_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
set_cnt_i[0] | Unreachable | Unreachable | Unreachable | INPUT | ||
set_cnt_i[1] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
incr_en_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
decr_en_i | Unreachable | Unreachable | Unreachable | INPUT | ||
step_i[1:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
commit_i | Unreachable | Unreachable | Unreachable | INPUT | ||
cnt_o[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
cnt_after_commit_o[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
err_o | No | No | No | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 8 | 7 | 87.50 |
Total Bits | 20 | 18 | 90.00 |
Total Bits 0->1 | 10 | 9 | 90.00 |
Total Bits 1->0 | 10 | 9 | 90.00 |
Ports | 8 | 7 | 87.50 |
Port Bits | 20 | 18 | 90.00 |
Port Bits 0->1 | 10 | 9 | 90.00 |
Port Bits 1->0 | 10 | 9 | 90.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T11,T21 | Yes | T1,T2,T3 | INPUT |
clr_i | Unreachable | Unreachable | Unreachable | INPUT | ||
set_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
set_cnt_i[0] | Unreachable | Unreachable | Unreachable | INPUT | ||
set_cnt_i[1] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
incr_en_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
decr_en_i | Unreachable | Unreachable | Unreachable | INPUT | ||
step_i[1:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
commit_i | Unreachable | Unreachable | Unreachable | INPUT | ||
cnt_o[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
cnt_after_commit_o[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
err_o | No | No | No | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 8 | 7 | 87.50 |
Total Bits | 20 | 18 | 90.00 |
Total Bits 0->1 | 10 | 9 | 90.00 |
Total Bits 1->0 | 10 | 9 | 90.00 |
Ports | 8 | 7 | 87.50 |
Port Bits | 20 | 18 | 90.00 |
Port Bits 0->1 | 10 | 9 | 90.00 |
Port Bits 1->0 | 10 | 9 | 90.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T11,T21 | Yes | T1,T2,T3 | INPUT |
clr_i | Unreachable | Unreachable | Unreachable | INPUT | ||
set_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
set_cnt_i[0] | Unreachable | Unreachable | Unreachable | INPUT | ||
set_cnt_i[1] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
incr_en_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
decr_en_i | Unreachable | Unreachable | Unreachable | INPUT | ||
step_i[1:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
commit_i | Unreachable | Unreachable | Unreachable | INPUT | ||
cnt_o[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
cnt_after_commit_o[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
err_o | No | No | No | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 7 | 7 | 100.00 |
Total Bits | 70 | 70 | 100.00 |
Total Bits 0->1 | 35 | 35 | 100.00 |
Total Bits 1->0 | 35 | 35 | 100.00 |
Ports | 7 | 7 | 100.00 |
Port Bits | 70 | 70 | 100.00 |
Port Bits 0->1 | 35 | 35 | 100.00 |
Port Bits 1->0 | 35 | 35 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T11,T21 | Yes | T1,T2,T3 | INPUT |
clr_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
set_i | Unreachable | Unreachable | Unreachable | INPUT | ||
set_cnt_i[14:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
incr_en_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
decr_en_i | Unreachable | Unreachable | Unreachable | INPUT | ||
step_i[14:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
commit_i | Unreachable | Unreachable | Unreachable | INPUT | ||
cnt_o[14:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
cnt_after_commit_o[14:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
err_o | Yes | Yes | T15,T16,T17 | Yes | T15,T16,T17 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 8 | 8 | 100.00 |
Total Bits | 20 | 20 | 100.00 |
Total Bits 0->1 | 10 | 10 | 100.00 |
Total Bits 1->0 | 10 | 10 | 100.00 |
Ports | 8 | 8 | 100.00 |
Port Bits | 20 | 20 | 100.00 |
Port Bits 0->1 | 10 | 10 | 100.00 |
Port Bits 1->0 | 10 | 10 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T11,T21 | Yes | T1,T2,T3 | INPUT |
clr_i | Unreachable | Unreachable | Unreachable | INPUT | ||
set_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
set_cnt_i[0] | Unreachable | Unreachable | Unreachable | INPUT | ||
set_cnt_i[1] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
incr_en_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
decr_en_i | Unreachable | Unreachable | Unreachable | INPUT | ||
step_i[1:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
commit_i | Unreachable | Unreachable | Unreachable | INPUT | ||
cnt_o[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
cnt_after_commit_o[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
err_o | Yes | Yes | T15,T16,T17 | Yes | T15,T16,T17 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 8 | 8 | 100.00 |
Total Bits | 20 | 20 | 100.00 |
Total Bits 0->1 | 10 | 10 | 100.00 |
Total Bits 1->0 | 10 | 10 | 100.00 |
Ports | 8 | 8 | 100.00 |
Port Bits | 20 | 20 | 100.00 |
Port Bits 0->1 | 10 | 10 | 100.00 |
Port Bits 1->0 | 10 | 10 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T11,T21 | Yes | T1,T2,T3 | INPUT |
clr_i | Unreachable | Unreachable | Unreachable | INPUT | ||
set_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
set_cnt_i[0] | Unreachable | Unreachable | Unreachable | INPUT | ||
set_cnt_i[1] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
incr_en_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
decr_en_i | Unreachable | Unreachable | Unreachable | INPUT | ||
step_i[1:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
commit_i | Unreachable | Unreachable | Unreachable | INPUT | ||
cnt_o[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
cnt_after_commit_o[1:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
err_o | Yes | Yes | T15,T16,T17 | Yes | T15,T16,T17 | OUTPUT |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |