Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1100600204	225113	0	0
ctrl_regwen_rd_A	1100600204	4182	0	0
exec_rd_A	1100600204	3740	0	0
exec_regwen_rd_A	1100600204	3784	0	0
readback_rd_A	1100600204	2394	0	0
readback_regwen_rd_A	1100600204	2403	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1100600204	225113	0	0
T5	229591	0	0	0
T11	74437	3727	0	0
T12	66528	0	0	0
T21	30997	971	0	0
T22	104032	2447	0	0
T24	34406	0	0	0
T38	74075	0	0	0
T39	75085	0	0	0
T41	980919	0	0	0
T43	450496	0	0	0
T48	0	3990	0	0
T52	0	3876	0	0
T55	0	11980	0	0
T56	0	5948	0	0
T57	0	2724	0	0
T58	0	10327	0	0
T71	0	3537	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1100600204	4182	0	0
T5	229591	0	0	0
T21	30997	95	0	0
T22	104032	189	0	0
T24	34406	0	0	0
T38	74075	0	0	0
T39	75085	0	0	0
T41	980919	0	0	0
T42	44356	0	0	0
T43	450496	0	0	0
T52	0	244	0	0
T57	0	240	0	0
T60	379504	0	0	0
T112	0	141	0	0
T113	0	165	0	0
T114	0	161	0	0
T115	0	72	0	0
T116	0	89	0	0
T117	0	90	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1100600204	3740	0	0
T5	229591	0	0	0
T21	30997	105	0	0
T22	104032	180	0	0
T24	34406	0	0	0
T38	74075	0	0	0
T39	75085	0	0	0
T41	980919	0	0	0
T42	44356	0	0	0
T43	450496	0	0	0
T52	0	142	0	0
T57	0	147	0	0
T60	379504	0	0	0
T112	0	89	0	0
T113	0	142	0	0
T114	0	179	0	0
T115	0	49	0	0
T116	0	66	0	0
T117	0	83	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1100600204	3784	0	0
T5	229591	0	0	0
T21	30997	126	0	0
T22	104032	141	0	0
T24	34406	0	0	0
T38	74075	0	0	0
T39	75085	0	0	0
T41	980919	0	0	0
T42	44356	0	0	0
T43	450496	0	0	0
T52	0	194	0	0
T57	0	174	0	0
T60	379504	0	0	0
T112	0	105	0	0
T113	0	159	0	0
T114	0	164	0	0
T115	0	65	0	0
T116	0	66	0	0
T117	0	100	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1100600204	2394	0	0
T5	229591	0	0	0
T21	30997	91	0	0
T22	104032	140	0	0
T24	34406	0	0	0
T38	74075	0	0	0
T39	75085	0	0	0
T41	980919	0	0	0
T42	44356	0	0	0
T43	450496	0	0	0
T52	0	206	0	0
T57	0	218	0	0
T60	379504	0	0	0
T112	0	105	0	0
T113	0	166	0	0
T114	0	201	0	0
T115	0	32	0	0
T116	0	36	0	0
T117	0	116	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1100600204	2403	0	0
T5	229591	0	0	0
T21	30997	51	0	0
T22	104032	173	0	0
T24	34406	0	0	0
T38	74075	0	0	0
T39	75085	0	0	0
T41	980919	0	0	0
T42	44356	0	0	0
T43	450496	0	0	0
T52	0	169	0	0
T57	0	212	0	0
T60	379504	0	0	0
T112	0	113	0	0
T113	0	149	0	0
T114	0	173	0	0
T115	0	56	0	0
T116	0	49	0	0
T117	0	97	0	0