| T801 |
/workspace/coverage/default/16.sram_ctrl_smoke.4215512737 |
|
|
Jul 05 04:50:51 PM PDT 24 |
Jul 05 04:51:09 PM PDT 24 |
2416983734 ps |
| T802 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.1566929928 |
|
|
Jul 05 04:49:34 PM PDT 24 |
Jul 05 04:59:06 PM PDT 24 |
25332290214 ps |
| T803 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.4002859828 |
|
|
Jul 05 04:59:35 PM PDT 24 |
Jul 05 05:00:27 PM PDT 24 |
1177705390 ps |
| T50 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.3291352470 |
|
|
Jul 05 04:52:26 PM PDT 24 |
Jul 05 04:55:58 PM PDT 24 |
2149628821 ps |
| T804 |
/workspace/coverage/default/16.sram_ctrl_executable.717703261 |
|
|
Jul 05 04:50:59 PM PDT 24 |
Jul 05 05:00:37 PM PDT 24 |
16277099916 ps |
| T805 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.1540360020 |
|
|
Jul 05 04:48:18 PM PDT 24 |
Jul 05 04:48:46 PM PDT 24 |
28260496780 ps |
| T806 |
/workspace/coverage/default/39.sram_ctrl_smoke.2306006740 |
|
|
Jul 05 04:57:59 PM PDT 24 |
Jul 05 04:58:27 PM PDT 24 |
2971204096 ps |
| T807 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.1643139572 |
|
|
Jul 05 04:48:13 PM PDT 24 |
Jul 05 04:55:36 PM PDT 24 |
37406257029 ps |
| T808 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.701564782 |
|
|
Jul 05 04:56:08 PM PDT 24 |
Jul 05 05:01:17 PM PDT 24 |
21881020330 ps |
| T809 |
/workspace/coverage/default/45.sram_ctrl_stress_all.2792177876 |
|
|
Jul 05 05:00:11 PM PDT 24 |
Jul 05 05:45:54 PM PDT 24 |
38113758284 ps |
| T810 |
/workspace/coverage/default/37.sram_ctrl_executable.3631728797 |
|
|
Jul 05 04:57:31 PM PDT 24 |
Jul 05 05:12:38 PM PDT 24 |
22987075868 ps |
| T16 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.1463814377 |
|
|
Jul 05 04:48:34 PM PDT 24 |
Jul 05 04:48:37 PM PDT 24 |
213476361 ps |
| T811 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.3977964656 |
|
|
Jul 05 04:52:33 PM PDT 24 |
Jul 05 04:54:58 PM PDT 24 |
11870871138 ps |
| T812 |
/workspace/coverage/default/1.sram_ctrl_smoke.558478914 |
|
|
Jul 05 04:47:57 PM PDT 24 |
Jul 05 04:48:23 PM PDT 24 |
4525447149 ps |
| T813 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.2856743417 |
|
|
Jul 05 04:59:05 PM PDT 24 |
Jul 05 04:59:27 PM PDT 24 |
722191252 ps |
| T814 |
/workspace/coverage/default/6.sram_ctrl_stress_all.440157665 |
|
|
Jul 05 04:48:48 PM PDT 24 |
Jul 05 05:45:19 PM PDT 24 |
312494045987 ps |
| T815 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.3203264569 |
|
|
Jul 05 04:59:41 PM PDT 24 |
Jul 05 05:11:07 PM PDT 24 |
29970501017 ps |
| T816 |
/workspace/coverage/default/13.sram_ctrl_executable.3747716055 |
|
|
Jul 05 04:50:24 PM PDT 24 |
Jul 05 05:13:13 PM PDT 24 |
28999008119 ps |
| T817 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3203844358 |
|
|
Jul 05 04:49:46 PM PDT 24 |
Jul 05 04:54:10 PM PDT 24 |
18911534594 ps |
| T818 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.1989537322 |
|
|
Jul 05 04:48:48 PM PDT 24 |
Jul 05 04:51:16 PM PDT 24 |
10958834637 ps |
| T819 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.3781269413 |
|
|
Jul 05 04:54:59 PM PDT 24 |
Jul 05 04:56:07 PM PDT 24 |
747834954 ps |
| T820 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.1907975509 |
|
|
Jul 05 04:58:52 PM PDT 24 |
Jul 05 04:58:57 PM PDT 24 |
1986830694 ps |
| T821 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.3823360740 |
|
|
Jul 05 04:51:42 PM PDT 24 |
Jul 05 04:57:20 PM PDT 24 |
20909640800 ps |
| T822 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.1095679389 |
|
|
Jul 05 04:59:42 PM PDT 24 |
Jul 05 05:01:09 PM PDT 24 |
13470821777 ps |
| T823 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.2334662528 |
|
|
Jul 05 04:53:30 PM PDT 24 |
Jul 05 05:05:33 PM PDT 24 |
10511591298 ps |
| T824 |
/workspace/coverage/default/33.sram_ctrl_stress_all.2040364792 |
|
|
Jul 05 04:56:14 PM PDT 24 |
Jul 05 05:31:53 PM PDT 24 |
161399034246 ps |
| T825 |
/workspace/coverage/default/42.sram_ctrl_regwen.2137668968 |
|
|
Jul 05 04:59:10 PM PDT 24 |
Jul 05 05:08:22 PM PDT 24 |
2105802610 ps |
| T826 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1521407231 |
|
|
Jul 05 04:48:49 PM PDT 24 |
Jul 05 04:50:39 PM PDT 24 |
1404384009 ps |
| T827 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.693264004 |
|
|
Jul 05 04:57:18 PM PDT 24 |
Jul 05 04:59:46 PM PDT 24 |
5230101447 ps |
| T828 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.766246920 |
|
|
Jul 05 04:50:37 PM PDT 24 |
Jul 05 04:53:08 PM PDT 24 |
7591581309 ps |
| T829 |
/workspace/coverage/default/24.sram_ctrl_alert_test.3163820165 |
|
|
Jul 05 04:53:18 PM PDT 24 |
Jul 05 04:53:20 PM PDT 24 |
33546622 ps |
| T830 |
/workspace/coverage/default/9.sram_ctrl_smoke.2206733960 |
|
|
Jul 05 04:49:24 PM PDT 24 |
Jul 05 04:49:55 PM PDT 24 |
665773412 ps |
| T831 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.3036014483 |
|
|
Jul 05 04:58:29 PM PDT 24 |
Jul 05 05:01:03 PM PDT 24 |
4955107465 ps |
| T832 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.2373143223 |
|
|
Jul 05 04:52:33 PM PDT 24 |
Jul 05 05:03:47 PM PDT 24 |
5536990587 ps |
| T833 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.547614913 |
|
|
Jul 05 04:48:40 PM PDT 24 |
Jul 05 04:51:20 PM PDT 24 |
812457265 ps |
| T834 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.553360743 |
|
|
Jul 05 05:00:42 PM PDT 24 |
Jul 05 05:02:36 PM PDT 24 |
69537068553 ps |
| T835 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.1963702361 |
|
|
Jul 05 04:59:59 PM PDT 24 |
Jul 05 05:18:23 PM PDT 24 |
14064568580 ps |
| T836 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.172193518 |
|
|
Jul 05 04:52:19 PM PDT 24 |
Jul 05 04:53:56 PM PDT 24 |
9407752157 ps |
| T837 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.4076327233 |
|
|
Jul 05 04:49:46 PM PDT 24 |
Jul 05 04:51:57 PM PDT 24 |
873047294 ps |
| T838 |
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.1213522718 |
|
|
Jul 05 04:51:26 PM PDT 24 |
Jul 05 04:54:11 PM PDT 24 |
9152862713 ps |
| T839 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1534809169 |
|
|
Jul 05 04:50:22 PM PDT 24 |
Jul 05 04:51:04 PM PDT 24 |
5951792872 ps |
| T840 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.2803905995 |
|
|
Jul 05 04:58:19 PM PDT 24 |
Jul 05 05:01:30 PM PDT 24 |
10562010129 ps |
| T841 |
/workspace/coverage/default/49.sram_ctrl_executable.4123140636 |
|
|
Jul 05 05:01:21 PM PDT 24 |
Jul 05 05:09:54 PM PDT 24 |
10483112063 ps |
| T842 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.2047298791 |
|
|
Jul 05 04:59:46 PM PDT 24 |
Jul 05 04:59:50 PM PDT 24 |
708611459 ps |
| T843 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.3689327635 |
|
|
Jul 05 04:50:43 PM PDT 24 |
Jul 05 04:51:24 PM PDT 24 |
1448543237 ps |
| T844 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.776213269 |
|
|
Jul 05 04:58:12 PM PDT 24 |
Jul 05 05:02:44 PM PDT 24 |
45833750458 ps |
| T845 |
/workspace/coverage/default/26.sram_ctrl_partial_access.2242516253 |
|
|
Jul 05 04:53:44 PM PDT 24 |
Jul 05 04:53:57 PM PDT 24 |
3661788822 ps |
| T846 |
/workspace/coverage/default/21.sram_ctrl_smoke.4022074460 |
|
|
Jul 05 04:52:05 PM PDT 24 |
Jul 05 04:53:58 PM PDT 24 |
4875225016 ps |
| T847 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.2247911436 |
|
|
Jul 05 04:51:57 PM PDT 24 |
Jul 05 04:57:07 PM PDT 24 |
4209612360 ps |
| T848 |
/workspace/coverage/default/22.sram_ctrl_bijection.1189969030 |
|
|
Jul 05 04:52:35 PM PDT 24 |
Jul 05 05:02:06 PM PDT 24 |
101085265183 ps |
| T849 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2340889475 |
|
|
Jul 05 04:47:56 PM PDT 24 |
Jul 05 05:08:22 PM PDT 24 |
19475179121 ps |
| T850 |
/workspace/coverage/default/47.sram_ctrl_partial_access.565190060 |
|
|
Jul 05 05:00:41 PM PDT 24 |
Jul 05 05:00:55 PM PDT 24 |
1102692074 ps |
| T851 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.2668023377 |
|
|
Jul 05 04:50:52 PM PDT 24 |
Jul 05 04:50:56 PM PDT 24 |
359637282 ps |
| T852 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.3428941058 |
|
|
Jul 05 04:57:05 PM PDT 24 |
Jul 05 04:58:36 PM PDT 24 |
770808234 ps |
| T853 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.3319938998 |
|
|
Jul 05 04:56:50 PM PDT 24 |
Jul 05 04:58:17 PM PDT 24 |
840610545 ps |
| T854 |
/workspace/coverage/default/5.sram_ctrl_smoke.1833661404 |
|
|
Jul 05 04:48:32 PM PDT 24 |
Jul 05 04:48:45 PM PDT 24 |
3460062025 ps |
| T855 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.3054436203 |
|
|
Jul 05 04:48:55 PM PDT 24 |
Jul 05 05:20:14 PM PDT 24 |
61382899808 ps |
| T856 |
/workspace/coverage/default/18.sram_ctrl_bijection.45666087 |
|
|
Jul 05 04:51:25 PM PDT 24 |
Jul 05 05:34:30 PM PDT 24 |
300952201519 ps |
| T857 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.890036628 |
|
|
Jul 05 04:53:29 PM PDT 24 |
Jul 05 04:54:07 PM PDT 24 |
19397879312 ps |
| T858 |
/workspace/coverage/default/5.sram_ctrl_regwen.2333525989 |
|
|
Jul 05 04:48:40 PM PDT 24 |
Jul 05 04:50:03 PM PDT 24 |
20885345292 ps |
| T859 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.408320053 |
|
|
Jul 05 04:58:12 PM PDT 24 |
Jul 05 04:59:13 PM PDT 24 |
746181941 ps |
| T51 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1911708397 |
|
|
Jul 05 05:01:26 PM PDT 24 |
Jul 05 05:04:18 PM PDT 24 |
3355890982 ps |
| T860 |
/workspace/coverage/default/46.sram_ctrl_partial_access.3898743792 |
|
|
Jul 05 05:00:17 PM PDT 24 |
Jul 05 05:00:35 PM PDT 24 |
4260106345 ps |
| T861 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.3323994618 |
|
|
Jul 05 04:48:12 PM PDT 24 |
Jul 05 04:50:25 PM PDT 24 |
4935676409 ps |
| T862 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.3251916301 |
|
|
Jul 05 04:59:23 PM PDT 24 |
Jul 05 05:16:01 PM PDT 24 |
19048001605 ps |
| T863 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.1404847294 |
|
|
Jul 05 04:53:57 PM PDT 24 |
Jul 05 04:55:04 PM PDT 24 |
12160608094 ps |
| T864 |
/workspace/coverage/default/30.sram_ctrl_alert_test.3803932948 |
|
|
Jul 05 04:55:05 PM PDT 24 |
Jul 05 04:55:06 PM PDT 24 |
38505982 ps |
| T865 |
/workspace/coverage/default/47.sram_ctrl_regwen.3044977725 |
|
|
Jul 05 05:00:41 PM PDT 24 |
Jul 05 05:17:56 PM PDT 24 |
9325454245 ps |
| T866 |
/workspace/coverage/default/26.sram_ctrl_bijection.172907375 |
|
|
Jul 05 04:53:36 PM PDT 24 |
Jul 05 05:37:08 PM PDT 24 |
134673059671 ps |
| T867 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.3712185302 |
|
|
Jul 05 04:50:36 PM PDT 24 |
Jul 05 04:52:42 PM PDT 24 |
1978974448 ps |
| T868 |
/workspace/coverage/default/17.sram_ctrl_executable.3977673485 |
|
|
Jul 05 04:51:20 PM PDT 24 |
Jul 05 04:56:50 PM PDT 24 |
8067198170 ps |
| T869 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.1912398985 |
|
|
Jul 05 04:50:14 PM PDT 24 |
Jul 05 04:55:42 PM PDT 24 |
21998411869 ps |
| T870 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3795045908 |
|
|
Jul 05 04:59:04 PM PDT 24 |
Jul 05 05:00:11 PM PDT 24 |
6224153924 ps |
| T871 |
/workspace/coverage/default/42.sram_ctrl_bijection.708306508 |
|
|
Jul 05 04:58:58 PM PDT 24 |
Jul 05 05:41:20 PM PDT 24 |
629757782112 ps |
| T872 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.1882255676 |
|
|
Jul 05 04:50:31 PM PDT 24 |
Jul 05 05:03:23 PM PDT 24 |
42294939884 ps |
| T873 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.4137495170 |
|
|
Jul 05 04:49:46 PM PDT 24 |
Jul 05 04:59:54 PM PDT 24 |
59553086444 ps |
| T874 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.2519608718 |
|
|
Jul 05 04:50:58 PM PDT 24 |
Jul 05 04:51:53 PM PDT 24 |
28368558061 ps |
| T875 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1854754912 |
|
|
Jul 05 04:56:16 PM PDT 24 |
Jul 05 04:57:09 PM PDT 24 |
2105327359 ps |
| T876 |
/workspace/coverage/default/46.sram_ctrl_smoke.1027182416 |
|
|
Jul 05 05:00:11 PM PDT 24 |
Jul 05 05:00:48 PM PDT 24 |
8326989641 ps |
| T877 |
/workspace/coverage/default/20.sram_ctrl_executable.1428095545 |
|
|
Jul 05 04:52:06 PM PDT 24 |
Jul 05 05:02:20 PM PDT 24 |
53722141738 ps |
| T878 |
/workspace/coverage/default/5.sram_ctrl_executable.1131214679 |
|
|
Jul 05 04:48:40 PM PDT 24 |
Jul 05 05:02:26 PM PDT 24 |
36262486889 ps |
| T879 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.105116000 |
|
|
Jul 05 04:52:20 PM PDT 24 |
Jul 05 04:55:06 PM PDT 24 |
9345656462 ps |
| T880 |
/workspace/coverage/default/33.sram_ctrl_smoke.1784504300 |
|
|
Jul 05 04:55:58 PM PDT 24 |
Jul 05 04:56:08 PM PDT 24 |
5004994047 ps |
| T881 |
/workspace/coverage/default/21.sram_ctrl_stress_all.1437111890 |
|
|
Jul 05 04:52:26 PM PDT 24 |
Jul 05 05:40:28 PM PDT 24 |
76367202623 ps |
| T882 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.817472952 |
|
|
Jul 05 04:57:51 PM PDT 24 |
Jul 05 05:00:01 PM PDT 24 |
1700519507 ps |
| T883 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.719387771 |
|
|
Jul 05 04:47:58 PM PDT 24 |
Jul 05 04:48:44 PM PDT 24 |
43227391468 ps |
| T884 |
/workspace/coverage/default/45.sram_ctrl_alert_test.2149010571 |
|
|
Jul 05 05:00:11 PM PDT 24 |
Jul 05 05:00:13 PM PDT 24 |
39822514 ps |
| T885 |
/workspace/coverage/default/24.sram_ctrl_partial_access.834185320 |
|
|
Jul 05 04:53:08 PM PDT 24 |
Jul 05 04:53:12 PM PDT 24 |
748801800 ps |
| T886 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.4006693669 |
|
|
Jul 05 04:51:34 PM PDT 24 |
Jul 05 04:53:46 PM PDT 24 |
7893972866 ps |
| T887 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.1504993863 |
|
|
Jul 05 04:47:57 PM PDT 24 |
Jul 05 05:24:07 PM PDT 24 |
65097123434 ps |
| T888 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.3546600917 |
|
|
Jul 05 04:53:51 PM PDT 24 |
Jul 05 04:53:55 PM PDT 24 |
1974572004 ps |
| T889 |
/workspace/coverage/default/3.sram_ctrl_regwen.1034412380 |
|
|
Jul 05 04:48:26 PM PDT 24 |
Jul 05 05:04:39 PM PDT 24 |
8387515545 ps |
| T890 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.1263485350 |
|
|
Jul 05 04:56:49 PM PDT 24 |
Jul 05 04:57:44 PM PDT 24 |
771497992 ps |
| T891 |
/workspace/coverage/default/49.sram_ctrl_bijection.2684157533 |
|
|
Jul 05 05:01:14 PM PDT 24 |
Jul 05 05:17:36 PM PDT 24 |
13503319984 ps |
| T892 |
/workspace/coverage/default/12.sram_ctrl_regwen.2332721127 |
|
|
Jul 05 04:50:06 PM PDT 24 |
Jul 05 05:00:57 PM PDT 24 |
13047470091 ps |
| T893 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1594738857 |
|
|
Jul 05 04:58:59 PM PDT 24 |
Jul 05 05:06:34 PM PDT 24 |
17615842096 ps |
| T894 |
/workspace/coverage/default/33.sram_ctrl_bijection.1396618685 |
|
|
Jul 05 04:55:58 PM PDT 24 |
Jul 05 05:40:18 PM PDT 24 |
230050628060 ps |
| T17 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.524443697 |
|
|
Jul 05 04:48:06 PM PDT 24 |
Jul 05 04:48:09 PM PDT 24 |
729906958 ps |
| T895 |
/workspace/coverage/default/40.sram_ctrl_executable.3906436776 |
|
|
Jul 05 04:58:32 PM PDT 24 |
Jul 05 05:16:13 PM PDT 24 |
36689624663 ps |
| T896 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.2259488780 |
|
|
Jul 05 04:56:15 PM PDT 24 |
Jul 05 04:57:16 PM PDT 24 |
14890533720 ps |
| T897 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.175613726 |
|
|
Jul 05 04:50:15 PM PDT 24 |
Jul 05 04:58:58 PM PDT 24 |
7709588933 ps |
| T27 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.307350032 |
|
|
Jul 05 04:47:56 PM PDT 24 |
Jul 05 04:48:00 PM PDT 24 |
1058620473 ps |
| T898 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.2921812367 |
|
|
Jul 05 04:51:26 PM PDT 24 |
Jul 05 04:56:21 PM PDT 24 |
19948290187 ps |
| T899 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.4125776552 |
|
|
Jul 05 04:49:03 PM PDT 24 |
Jul 05 04:52:08 PM PDT 24 |
5910154044 ps |
| T900 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.750180117 |
|
|
Jul 05 04:51:23 PM PDT 24 |
Jul 05 04:51:26 PM PDT 24 |
1784040316 ps |
| T901 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.1666272575 |
|
|
Jul 05 04:50:00 PM PDT 24 |
Jul 05 04:51:12 PM PDT 24 |
2724141536 ps |
| T902 |
/workspace/coverage/default/28.sram_ctrl_executable.3222144380 |
|
|
Jul 05 04:54:17 PM PDT 24 |
Jul 05 04:57:35 PM PDT 24 |
8743288415 ps |
| T903 |
/workspace/coverage/default/24.sram_ctrl_regwen.3930543309 |
|
|
Jul 05 04:53:19 PM PDT 24 |
Jul 05 05:16:04 PM PDT 24 |
3016931066 ps |
| T904 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.857673691 |
|
|
Jul 05 04:53:36 PM PDT 24 |
Jul 05 04:55:57 PM PDT 24 |
8226771823 ps |
| T905 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.2122896566 |
|
|
Jul 05 04:48:27 PM PDT 24 |
Jul 05 05:02:20 PM PDT 24 |
11737057899 ps |
| T906 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.26087437 |
|
|
Jul 05 04:56:22 PM PDT 24 |
Jul 05 05:03:16 PM PDT 24 |
21719763260 ps |
| T907 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.81639168 |
|
|
Jul 05 04:49:53 PM PDT 24 |
Jul 05 04:49:57 PM PDT 24 |
1532376431 ps |
| T908 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.3943197614 |
|
|
Jul 05 04:58:32 PM PDT 24 |
Jul 05 04:58:51 PM PDT 24 |
3332061146 ps |
| T909 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2853864596 |
|
|
Jul 05 04:48:54 PM PDT 24 |
Jul 05 04:50:11 PM PDT 24 |
1647508808 ps |
| T910 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.3152434973 |
|
|
Jul 05 04:48:03 PM PDT 24 |
Jul 05 04:48:07 PM PDT 24 |
343674494 ps |
| T911 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.2813788040 |
|
|
Jul 05 04:54:51 PM PDT 24 |
Jul 05 05:01:06 PM PDT 24 |
6802304090 ps |
| T912 |
/workspace/coverage/default/47.sram_ctrl_alert_test.4189680952 |
|
|
Jul 05 05:00:50 PM PDT 24 |
Jul 05 05:00:52 PM PDT 24 |
33599737 ps |
| T913 |
/workspace/coverage/default/9.sram_ctrl_stress_all.2396058393 |
|
|
Jul 05 04:49:30 PM PDT 24 |
Jul 05 05:49:24 PM PDT 24 |
138339903428 ps |
| T914 |
/workspace/coverage/default/5.sram_ctrl_partial_access.3427275283 |
|
|
Jul 05 04:48:41 PM PDT 24 |
Jul 05 04:49:08 PM PDT 24 |
2622717029 ps |
| T915 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.4072589568 |
|
|
Jul 05 04:52:41 PM PDT 24 |
Jul 05 04:53:47 PM PDT 24 |
968166410 ps |
| T916 |
/workspace/coverage/default/36.sram_ctrl_smoke.766359097 |
|
|
Jul 05 04:57:04 PM PDT 24 |
Jul 05 04:57:23 PM PDT 24 |
2120621471 ps |
| T917 |
/workspace/coverage/default/38.sram_ctrl_bijection.1067394437 |
|
|
Jul 05 04:57:46 PM PDT 24 |
Jul 05 05:48:08 PM PDT 24 |
172418053706 ps |
| T918 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.726365635 |
|
|
Jul 05 04:52:12 PM PDT 24 |
Jul 05 04:57:54 PM PDT 24 |
8091397634 ps |
| T919 |
/workspace/coverage/default/4.sram_ctrl_executable.1094969367 |
|
|
Jul 05 04:48:34 PM PDT 24 |
Jul 05 05:05:40 PM PDT 24 |
25729214580 ps |
| T920 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.846528617 |
|
|
Jul 05 04:49:22 PM PDT 24 |
Jul 05 04:50:06 PM PDT 24 |
6043079966 ps |
| T921 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.4213267617 |
|
|
Jul 05 04:57:51 PM PDT 24 |
Jul 05 05:12:53 PM PDT 24 |
47479418193 ps |
| T922 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.970626014 |
|
|
Jul 05 04:48:26 PM PDT 24 |
Jul 05 04:50:50 PM PDT 24 |
8167127553 ps |
| T923 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.2017324895 |
|
|
Jul 05 04:59:40 PM PDT 24 |
Jul 05 05:00:41 PM PDT 24 |
21983458105 ps |
| T924 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.3026947823 |
|
|
Jul 05 05:01:03 PM PDT 24 |
Jul 05 05:05:12 PM PDT 24 |
13358240402 ps |
| T925 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.4017460745 |
|
|
Jul 05 04:48:19 PM PDT 24 |
Jul 05 05:08:53 PM PDT 24 |
148264976046 ps |
| T926 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.89187583 |
|
|
Jul 05 04:49:24 PM PDT 24 |
Jul 05 04:55:56 PM PDT 24 |
6408566858 ps |
| T927 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.1932277977 |
|
|
Jul 05 04:48:40 PM PDT 24 |
Jul 05 04:53:14 PM PDT 24 |
5034059340 ps |
| T28 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.1794822547 |
|
|
Jul 05 04:48:26 PM PDT 24 |
Jul 05 04:48:30 PM PDT 24 |
1459694147 ps |
| T928 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2749603017 |
|
|
Jul 05 05:00:42 PM PDT 24 |
Jul 05 05:05:06 PM PDT 24 |
20292930635 ps |
| T929 |
/workspace/coverage/default/10.sram_ctrl_executable.3857028372 |
|
|
Jul 05 04:49:39 PM PDT 24 |
Jul 05 04:58:47 PM PDT 24 |
15347022170 ps |
| T930 |
/workspace/coverage/default/31.sram_ctrl_executable.521964221 |
|
|
Jul 05 04:55:20 PM PDT 24 |
Jul 05 05:13:48 PM PDT 24 |
9347057367 ps |
| T931 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.4276685115 |
|
|
Jul 05 04:49:18 PM PDT 24 |
Jul 05 04:52:20 PM PDT 24 |
57677463853 ps |
| T932 |
/workspace/coverage/default/25.sram_ctrl_regwen.1594030477 |
|
|
Jul 05 04:53:29 PM PDT 24 |
Jul 05 05:03:55 PM PDT 24 |
8281423929 ps |
| T933 |
/workspace/coverage/default/41.sram_ctrl_partial_access.3156374118 |
|
|
Jul 05 04:58:44 PM PDT 24 |
Jul 05 04:59:10 PM PDT 24 |
1715975444 ps |
| T934 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.2431230652 |
|
|
Jul 05 05:00:52 PM PDT 24 |
Jul 05 05:03:20 PM PDT 24 |
17322656863 ps |
| T935 |
/workspace/coverage/default/7.sram_ctrl_alert_test.403106455 |
|
|
Jul 05 04:49:02 PM PDT 24 |
Jul 05 04:49:03 PM PDT 24 |
23128210 ps |
| T936 |
/workspace/coverage/default/31.sram_ctrl_partial_access.3243214792 |
|
|
Jul 05 04:55:13 PM PDT 24 |
Jul 05 04:55:29 PM PDT 24 |
2832797068 ps |
| T937 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.37665874 |
|
|
Jul 05 04:51:49 PM PDT 24 |
Jul 05 04:56:42 PM PDT 24 |
17527180811 ps |
| T938 |
/workspace/coverage/default/16.sram_ctrl_stress_all.1422740038 |
|
|
Jul 05 04:51:06 PM PDT 24 |
Jul 05 06:25:43 PM PDT 24 |
90762588353 ps |
| T939 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.324921694 |
|
|
Jul 05 04:52:05 PM PDT 24 |
Jul 05 04:52:09 PM PDT 24 |
357444099 ps |
| T940 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.2704488219 |
|
|
Jul 05 04:59:05 PM PDT 24 |
Jul 05 05:00:17 PM PDT 24 |
11867001134 ps |
| T941 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.77980164 |
|
|
Jul 05 04:56:41 PM PDT 24 |
Jul 05 05:02:41 PM PDT 24 |
86262775164 ps |
| T942 |
/workspace/coverage/default/12.sram_ctrl_stress_all.2068008586 |
|
|
Jul 05 04:50:17 PM PDT 24 |
Jul 05 07:06:31 PM PDT 24 |
558350633328 ps |
| T943 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2727023194 |
|
|
Jul 05 04:58:45 PM PDT 24 |
Jul 05 04:59:22 PM PDT 24 |
3020775212 ps |
| T69 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.304242725 |
|
|
Jul 05 04:26:43 PM PDT 24 |
Jul 05 04:26:45 PM PDT 24 |
31841243 ps |
| T944 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2139083969 |
|
|
Jul 05 04:27:05 PM PDT 24 |
Jul 05 04:27:10 PM PDT 24 |
729977353 ps |
| T70 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3712834279 |
|
|
Jul 05 04:27:04 PM PDT 24 |
Jul 05 04:27:05 PM PDT 24 |
26167255 ps |
| T65 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1283536756 |
|
|
Jul 05 04:27:07 PM PDT 24 |
Jul 05 04:27:10 PM PDT 24 |
564068570 ps |
| T945 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4155527554 |
|
|
Jul 05 04:26:51 PM PDT 24 |
Jul 05 04:26:56 PM PDT 24 |
1158303783 ps |
| T108 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4267983194 |
|
|
Jul 05 04:26:42 PM PDT 24 |
Jul 05 04:26:44 PM PDT 24 |
15545603 ps |
| T74 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.338449720 |
|
|
Jul 05 04:26:44 PM PDT 24 |
Jul 05 04:27:28 PM PDT 24 |
46244297376 ps |
| T946 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.12395333 |
|
|
Jul 05 04:27:07 PM PDT 24 |
Jul 05 04:27:11 PM PDT 24 |
345427547 ps |
| T947 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1270959625 |
|
|
Jul 05 04:27:08 PM PDT 24 |
Jul 05 04:27:12 PM PDT 24 |
1476791623 ps |
| T948 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2415723048 |
|
|
Jul 05 04:34:45 PM PDT 24 |
Jul 05 04:34:48 PM PDT 24 |
78037024 ps |
| T949 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.4273230416 |
|
|
Jul 05 04:26:56 PM PDT 24 |
Jul 05 04:26:59 PM PDT 24 |
756927963 ps |
| T109 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3913292074 |
|
|
Jul 05 04:27:04 PM PDT 24 |
Jul 05 04:27:05 PM PDT 24 |
37969798 ps |
| T75 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1006014783 |
|
|
Jul 05 04:27:20 PM PDT 24 |
Jul 05 04:27:21 PM PDT 24 |
18809520 ps |
| T110 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2886098411 |
|
|
Jul 05 04:27:05 PM PDT 24 |
Jul 05 04:27:07 PM PDT 24 |
22557726 ps |
| T950 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.738626613 |
|
|
Jul 05 04:26:34 PM PDT 24 |
Jul 05 04:26:38 PM PDT 24 |
352849233 ps |
| T951 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1427823855 |
|
|
Jul 05 04:27:03 PM PDT 24 |
Jul 05 04:27:06 PM PDT 24 |
362164936 ps |
| T952 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1101946066 |
|
|
Jul 05 04:26:28 PM PDT 24 |
Jul 05 04:26:33 PM PDT 24 |
1968711796 ps |
| T66 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3345253626 |
|
|
Jul 05 04:27:00 PM PDT 24 |
Jul 05 04:27:02 PM PDT 24 |
255248637 ps |
| T103 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1781628528 |
|
|
Jul 05 04:26:59 PM PDT 24 |
Jul 05 04:27:00 PM PDT 24 |
87801002 ps |
| T76 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3820293759 |
|
|
Jul 05 04:27:03 PM PDT 24 |
Jul 05 04:27:04 PM PDT 24 |
21366338 ps |
| T953 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2623717109 |
|
|
Jul 05 04:26:38 PM PDT 24 |
Jul 05 04:26:42 PM PDT 24 |
932555903 ps |
| T111 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1564694153 |
|
|
Jul 05 04:26:29 PM PDT 24 |
Jul 05 04:26:30 PM PDT 24 |
38723288 ps |
| T77 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.780290312 |
|
|
Jul 05 04:26:23 PM PDT 24 |
Jul 05 04:26:24 PM PDT 24 |
13368073 ps |
| T78 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.492229296 |
|
|
Jul 05 04:26:44 PM PDT 24 |
Jul 05 04:26:45 PM PDT 24 |
29500737 ps |
| T104 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3874529387 |
|
|
Jul 05 04:26:40 PM PDT 24 |
Jul 05 04:26:42 PM PDT 24 |
45284795 ps |
| T954 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3867107092 |
|
|
Jul 05 04:26:48 PM PDT 24 |
Jul 05 04:26:52 PM PDT 24 |
736487433 ps |
| T79 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.72377825 |
|
|
Jul 05 04:26:59 PM PDT 24 |
Jul 05 04:27:41 PM PDT 24 |
41062801526 ps |
| T80 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1203720135 |
|
|
Jul 05 04:26:54 PM PDT 24 |
Jul 05 04:26:55 PM PDT 24 |
28045349 ps |
| T67 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3961468220 |
|
|
Jul 05 04:27:07 PM PDT 24 |
Jul 05 04:27:10 PM PDT 24 |
791637023 ps |
| T955 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2871150086 |
|
|
Jul 05 04:27:10 PM PDT 24 |
Jul 05 04:27:14 PM PDT 24 |
108583362 ps |
| T956 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3859202400 |
|
|
Jul 05 04:26:46 PM PDT 24 |
Jul 05 04:26:51 PM PDT 24 |
143829536 ps |
| T81 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3849621400 |
|
|
Jul 05 04:26:32 PM PDT 24 |
Jul 05 04:26:33 PM PDT 24 |
33834873 ps |
| T957 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3740300508 |
|
|
Jul 05 04:26:21 PM PDT 24 |
Jul 05 04:26:22 PM PDT 24 |
227158507 ps |
| T958 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.4230036237 |
|
|
Jul 05 04:26:28 PM PDT 24 |
Jul 05 04:26:29 PM PDT 24 |
12621495 ps |
| T120 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.952742120 |
|
|
Jul 05 04:26:45 PM PDT 24 |
Jul 05 04:26:50 PM PDT 24 |
136938073 ps |
| T959 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3902019869 |
|
|
Jul 05 04:26:40 PM PDT 24 |
Jul 05 04:26:45 PM PDT 24 |
365808577 ps |
| T124 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2176422792 |
|
|
Jul 05 04:26:27 PM PDT 24 |
Jul 05 04:26:31 PM PDT 24 |
753972770 ps |
| T960 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.195799264 |
|
|
Jul 05 04:26:25 PM PDT 24 |
Jul 05 04:26:27 PM PDT 24 |
45054308 ps |
| T961 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1940657471 |
|
|
Jul 05 04:27:06 PM PDT 24 |
Jul 05 04:27:07 PM PDT 24 |
82335307 ps |
| T962 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2473023421 |
|
|
Jul 05 04:26:33 PM PDT 24 |
Jul 05 04:26:35 PM PDT 24 |
14546612 ps |
| T82 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1296589171 |
|
|
Jul 05 04:27:19 PM PDT 24 |
Jul 05 04:27:46 PM PDT 24 |
3770037103 ps |
| T963 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2595258601 |
|
|
Jul 05 04:27:08 PM PDT 24 |
Jul 05 04:27:12 PM PDT 24 |
435632299 ps |
| T964 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.375037720 |
|
|
Jul 05 04:26:34 PM PDT 24 |
Jul 05 04:26:37 PM PDT 24 |
541492670 ps |
| T129 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1285384942 |
|
|
Jul 05 04:27:09 PM PDT 24 |
Jul 05 04:27:11 PM PDT 24 |
217547707 ps |
| T83 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1681869077 |
|
|
Jul 05 04:26:53 PM PDT 24 |
Jul 05 04:27:47 PM PDT 24 |
28162555018 ps |
| T965 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.585116759 |
|
|
Jul 05 04:26:30 PM PDT 24 |
Jul 05 04:27:03 PM PDT 24 |
14759054697 ps |
| T966 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.896697281 |
|
|
Jul 05 04:26:47 PM PDT 24 |
Jul 05 04:26:50 PM PDT 24 |
75736486 ps |
| T967 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2536027850 |
|
|
Jul 05 04:26:53 PM PDT 24 |
Jul 05 04:26:55 PM PDT 24 |
26218021 ps |
| T968 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2827907833 |
|
|
Jul 05 04:26:35 PM PDT 24 |
Jul 05 04:26:36 PM PDT 24 |
40598683 ps |
| T969 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3631424090 |
|
|
Jul 05 04:27:04 PM PDT 24 |
Jul 05 04:27:10 PM PDT 24 |
374345314 ps |
| T970 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2132844076 |
|
|
Jul 05 04:26:37 PM PDT 24 |
Jul 05 04:26:38 PM PDT 24 |
118924197 ps |
| T971 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.588918980 |
|
|
Jul 05 04:26:37 PM PDT 24 |
Jul 05 04:26:44 PM PDT 24 |
13024169 ps |
| T972 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2133813746 |
|
|
Jul 05 04:27:02 PM PDT 24 |
Jul 05 04:27:05 PM PDT 24 |
177635701 ps |
| T84 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1344967692 |
|
|
Jul 05 04:26:39 PM PDT 24 |
Jul 05 04:26:40 PM PDT 24 |
65024164 ps |
| T132 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1777850736 |
|
|
Jul 05 04:26:47 PM PDT 24 |
Jul 05 04:26:50 PM PDT 24 |
679999595 ps |
| T973 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1744092497 |
|
|
Jul 05 04:26:49 PM PDT 24 |
Jul 05 04:26:51 PM PDT 24 |
20803031 ps |
| T85 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1062282381 |
|
|
Jul 05 04:26:59 PM PDT 24 |
Jul 05 04:27:29 PM PDT 24 |
14779883100 ps |
| T125 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2941540256 |
|
|
Jul 05 04:26:54 PM PDT 24 |
Jul 05 04:26:56 PM PDT 24 |
340950561 ps |
| T974 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2135896878 |
|
|
Jul 05 04:26:37 PM PDT 24 |
Jul 05 04:26:42 PM PDT 24 |
136511657 ps |
| T130 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1616208198 |
|
|
Jul 05 04:26:43 PM PDT 24 |
Jul 05 04:26:47 PM PDT 24 |
480391313 ps |
| T975 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3321520621 |
|
|
Jul 05 04:27:03 PM PDT 24 |
Jul 05 04:27:08 PM PDT 24 |
177873467 ps |
| T976 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2213127344 |
|
|
Jul 05 04:26:52 PM PDT 24 |
Jul 05 04:26:57 PM PDT 24 |
100436373 ps |
| T86 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2462607783 |
|
|
Jul 05 04:27:09 PM PDT 24 |
Jul 05 04:27:49 PM PDT 24 |
36991770337 ps |
| T977 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1422554759 |
|
|
Jul 05 04:26:24 PM PDT 24 |
Jul 05 04:26:27 PM PDT 24 |
38749572 ps |
| T92 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3397495094 |
|
|
Jul 05 04:26:53 PM PDT 24 |
Jul 05 04:26:54 PM PDT 24 |
21703784 ps |
| T978 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.413296904 |
|
|
Jul 05 04:27:04 PM PDT 24 |
Jul 05 04:27:11 PM PDT 24 |
34720051 ps |
| T979 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2598970596 |
|
|
Jul 05 04:27:08 PM PDT 24 |
Jul 05 04:27:10 PM PDT 24 |
64239703 ps |
| T980 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.22136421 |
|
|
Jul 05 04:26:49 PM PDT 24 |
Jul 05 04:26:51 PM PDT 24 |
85721305 ps |
| T127 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2764606645 |
|
|
Jul 05 04:26:48 PM PDT 24 |
Jul 05 04:26:50 PM PDT 24 |
252300741 ps |
| T93 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1068901095 |
|
|
Jul 05 04:26:49 PM PDT 24 |
Jul 05 04:27:38 PM PDT 24 |
7049349087 ps |
| T981 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3782538975 |
|
|
Jul 05 04:26:33 PM PDT 24 |
Jul 05 04:26:38 PM PDT 24 |
404062957 ps |
| T982 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2879736558 |
|
|
Jul 05 04:26:20 PM PDT 24 |
Jul 05 04:26:23 PM PDT 24 |
36392155 ps |
| T983 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3414942489 |
|
|
Jul 05 04:27:05 PM PDT 24 |
Jul 05 04:27:07 PM PDT 24 |
11509485 ps |
| T121 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.614784275 |
|
|
Jul 05 04:26:40 PM PDT 24 |
Jul 05 04:26:43 PM PDT 24 |
197540028 ps |
| T984 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1104325929 |
|
|
Jul 05 04:26:42 PM PDT 24 |
Jul 05 04:26:48 PM PDT 24 |
368504626 ps |
| T985 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.4111290160 |
|
|
Jul 05 04:26:38 PM PDT 24 |
Jul 05 04:26:43 PM PDT 24 |
931834375 ps |
| T131 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.247507350 |
|
|
Jul 05 04:26:51 PM PDT 24 |
Jul 05 04:26:53 PM PDT 24 |
207934250 ps |
| T94 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.976683204 |
|
|
Jul 05 04:26:33 PM PDT 24 |
Jul 05 04:27:02 PM PDT 24 |
7857709967 ps |
| T95 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1855847481 |
|
|
Jul 05 04:26:33 PM PDT 24 |
Jul 05 04:27:25 PM PDT 24 |
7039319232 ps |
| T986 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.443674067 |
|
|
Jul 05 04:26:49 PM PDT 24 |
Jul 05 04:26:52 PM PDT 24 |
131163091 ps |
| T987 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2576104605 |
|
|
Jul 05 04:26:41 PM PDT 24 |
Jul 05 04:26:43 PM PDT 24 |
37137147 ps |
| T988 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.643597613 |
|
|
Jul 05 04:26:53 PM PDT 24 |
Jul 05 04:26:58 PM PDT 24 |
1376038847 ps |
| T989 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.471844513 |
|
|
Jul 05 04:26:23 PM PDT 24 |
Jul 05 04:26:49 PM PDT 24 |
4002691098 ps |
| T990 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1691998753 |
|
|
Jul 05 04:27:06 PM PDT 24 |
Jul 05 04:27:08 PM PDT 24 |
39427131 ps |
| T991 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3081468999 |
|
|
Jul 05 04:26:48 PM PDT 24 |
Jul 05 04:26:52 PM PDT 24 |
699053920 ps |
| T128 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1565675840 |
|
|
Jul 05 04:26:47 PM PDT 24 |
Jul 05 04:26:49 PM PDT 24 |
222617803 ps |
| T992 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3146243749 |
|
|
Jul 05 04:26:55 PM PDT 24 |
Jul 05 04:26:56 PM PDT 24 |
49100877 ps |
| T993 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2960302397 |
|
|
Jul 05 04:26:52 PM PDT 24 |
Jul 05 04:27:52 PM PDT 24 |
7485265442 ps |
| T994 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1680574232 |
|
|
Jul 05 04:26:43 PM PDT 24 |
Jul 05 04:26:48 PM PDT 24 |
558106168 ps |
| T96 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2530197592 |
|
|
Jul 05 04:26:53 PM PDT 24 |
Jul 05 04:26:54 PM PDT 24 |
23410403 ps |
| T995 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.306472056 |
|
|
Jul 05 04:27:15 PM PDT 24 |
Jul 05 04:27:18 PM PDT 24 |
460971152 ps |
| T996 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2007709517 |
|
|
Jul 05 04:27:01 PM PDT 24 |
Jul 05 04:27:06 PM PDT 24 |
904381510 ps |
| T997 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3657336876 |
|
|
Jul 05 04:26:52 PM PDT 24 |
Jul 05 04:26:58 PM PDT 24 |
16754518 ps |
| T126 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1987731045 |
|
|
Jul 05 04:26:58 PM PDT 24 |
Jul 05 04:27:01 PM PDT 24 |
293397656 ps |
| T97 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2545307630 |
|
|
Jul 05 04:26:51 PM PDT 24 |
Jul 05 04:27:42 PM PDT 24 |
8292046224 ps |
| T998 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2143801453 |
|
|
Jul 05 04:26:35 PM PDT 24 |
Jul 05 04:26:36 PM PDT 24 |
126742377 ps |
| T999 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1477880995 |
|
|
Jul 05 04:26:51 PM PDT 24 |
Jul 05 04:26:57 PM PDT 24 |
67433713 ps |
| T1000 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1392487298 |
|
|
Jul 05 04:26:41 PM PDT 24 |
Jul 05 04:26:43 PM PDT 24 |
85293327 ps |
| T1001 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.4199325241 |
|
|
Jul 05 04:26:49 PM PDT 24 |
Jul 05 04:26:51 PM PDT 24 |
18078094 ps |
| T101 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2369462572 |
|
|
Jul 05 04:27:04 PM PDT 24 |
Jul 05 04:27:37 PM PDT 24 |
4677028001 ps |
| T1002 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.392196362 |
|
|
Jul 05 04:26:26 PM PDT 24 |
Jul 05 04:26:27 PM PDT 24 |
12836877 ps |