Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15499504	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

149818441

1

T1

3115

T2

174305

T3

24247

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	81391984	1			T1	32132		T2	95841		T3	10812
values[0x0]	40423764	1			T1	10167		T2	46383		T3	7426
values[0x1]	43502197	1			T1	21631		T2	49476		T3	7580

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7886879	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

157431066

1

T1

28735

T2

183008

T3

25028

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	548626	1			T1	225		T2	765		T3	112
valid_sources[0x01]	536356	1			T1	254		T2	628		T3	110
valid_sources[0x02]	549127	1			T1	286		T2	873		T3	77
valid_sources[0x03]	554272	1			T1	243		T2	757		T3	101
valid_sources[0x04]	548481	1			T1	202		T2	714		T3	85
valid_sources[0x05]	546353	1			T1	245		T2	786		T3	105
valid_sources[0x06]	528608	1			T1	256		T2	693		T3	111
valid_sources[0x07]	3585049	1			T1	255		T2	734		T3	115
valid_sources[0x08]	532365	1			T1	295		T2	621		T3	99
valid_sources[0x09]	3275067	1			T1	265		T2	868		T3	103
valid_sources[0x0a]	536051	1			T1	227		T2	743		T3	100
valid_sources[0x0b]	554136	1			T1	265		T2	882		T3	94
valid_sources[0x0c]	533820	1			T1	237		T2	727		T3	110
valid_sources[0x0d]	616823	1			T1	261		T2	746		T3	105
valid_sources[0x0e]	566348	1			T1	214		T2	791		T3	89
valid_sources[0x0f]	528258	1			T1	276		T2	715		T3	98
valid_sources[0x10]	540733	1			T1	254		T2	828		T3	105
valid_sources[0x11]	566502	1			T1	243		T2	757		T3	100
valid_sources[0x12]	582440	1			T1	220		T2	720		T3	96
valid_sources[0x13]	535695	1			T1	282		T2	733		T3	107
valid_sources[0x14]	609293	1			T1	251		T2	779		T3	96
valid_sources[0x15]	555359	1			T1	282		T2	765		T3	106
valid_sources[0x16]	608686	1			T1	246		T2	739		T3	115
valid_sources[0x17]	586370	1			T1	254		T2	782		T3	94
valid_sources[0x18]	627273	1			T1	251		T2	826		T3	102
valid_sources[0x19]	583208	1			T1	245		T2	668		T3	97
valid_sources[0x1a]	533772	1			T1	272		T2	870		T3	99
valid_sources[0x1b]	537548	1			T1	277		T2	751		T3	92
valid_sources[0x1c]	556215	1			T1	262		T2	722		T3	90
valid_sources[0x1d]	528248	1			T1	240		T2	677		T3	100
valid_sources[0x1e]	572550	1			T1	231		T2	741		T3	106
valid_sources[0x1f]	582664	1			T1	234		T2	721		T3	91
valid_sources[0x20]	562265	1			T1	227		T2	601		T3	91
valid_sources[0x21]	562318	1			T1	273		T2	691		T3	101
valid_sources[0x22]	553061	1			T1	269		T2	795		T3	100
valid_sources[0x23]	520602	1			T1	257		T2	797		T3	125
valid_sources[0x24]	533957	1			T1	240		T2	739		T3	108
valid_sources[0x25]	624367	1			T1	257		T2	842		T3	114
valid_sources[0x26]	519354	1			T1	249		T2	728		T3	99
valid_sources[0x27]	560278	1			T1	222		T2	652		T3	128
valid_sources[0x28]	532971	1			T1	252		T2	807		T3	97
valid_sources[0x29]	559247	1			T1	270		T2	746		T3	112
valid_sources[0x2a]	585495	1			T1	238		T2	834		T3	103
valid_sources[0x2b]	545065	1			T1	236		T2	860		T3	105
valid_sources[0x2c]	572113	1			T1	270		T2	768		T3	111
valid_sources[0x2d]	547663	1			T1	228		T2	702		T3	93
valid_sources[0x2e]	532752	1			T1	210		T2	705		T3	96
valid_sources[0x2f]	535764	1			T1	246		T2	873		T3	108
valid_sources[0x30]	599241	1			T1	269		T2	775		T3	107
valid_sources[0x31]	551283	1			T1	236		T2	710		T3	107
valid_sources[0x32]	543869	1			T1	250		T2	733		T3	102
valid_sources[0x33]	552807	1			T1	249		T2	709		T3	105
valid_sources[0x34]	534094	1			T1	240		T2	664		T3	83
valid_sources[0x35]	557040	1			T1	263		T2	820		T3	92
valid_sources[0x36]	604125	1			T1	236		T2	761		T3	102
valid_sources[0x37]	585794	1			T1	240		T2	829		T3	120
valid_sources[0x38]	531352	1			T1	246		T2	925		T3	104
valid_sources[0x39]	547923	1			T1	296		T2	836		T3	91
valid_sources[0x3a]	1937335	1			T1	235		T2	706		T3	109
valid_sources[0x3b]	557452	1			T1	270		T2	871		T3	101
valid_sources[0x3c]	546385	1			T1	226		T2	774		T3	114
valid_sources[0x3d]	520439	1			T1	257		T2	868		T3	120
valid_sources[0x3e]	630783	1			T1	272		T2	801		T3	102
valid_sources[0x3f]	567897	1			T1	295		T2	779		T3	115
valid_sources[0x40]	1896808	1			T1	236		T2	711		T3	108
valid_sources[0x41]	604903	1			T1	260		T2	874		T3	97
valid_sources[0x42]	518544	1			T1	234		T2	770		T3	113
valid_sources[0x43]	558093	1			T1	275		T2	801		T3	91
valid_sources[0x44]	551946	1			T1	235		T2	793		T3	99
valid_sources[0x45]	1294784	1			T1	251		T2	703		T3	97
valid_sources[0x46]	537882	1			T1	242		T2	833		T3	101
valid_sources[0x47]	532501	1			T1	242		T2	686		T3	99
valid_sources[0x48]	599519	1			T1	278		T2	749		T3	95
valid_sources[0x49]	567006	1			T1	227		T2	715		T3	100
valid_sources[0x4a]	534969	1			T1	258		T2	729		T3	103
valid_sources[0x4b]	530212	1			T1	250		T2	735		T3	102
valid_sources[0x4c]	522254	1			T1	221		T2	782		T3	83
valid_sources[0x4d]	552705	1			T1	286		T2	723		T3	94
valid_sources[0x4e]	597770	1			T1	236		T2	956		T3	97
valid_sources[0x4f]	535054	1			T1	256		T2	885		T3	102
valid_sources[0x50]	518012	1			T1	270		T2	681		T3	99
valid_sources[0x51]	540282	1			T1	230		T2	859		T3	97
valid_sources[0x52]	559631	1			T1	250		T2	721		T3	97
valid_sources[0x53]	614617	1			T1	232		T2	685		T3	109
valid_sources[0x54]	1352104	1			T1	244		T2	904		T3	82
valid_sources[0x55]	1496092	1			T1	245		T2	741		T3	92
valid_sources[0x56]	562392	1			T1	251		T2	705		T3	106
valid_sources[0x57]	556992	1			T1	260		T2	755		T3	107
valid_sources[0x58]	553198	1			T1	232		T2	896		T3	94
valid_sources[0x59]	574326	1			T1	266		T2	715		T3	95
valid_sources[0x5a]	602505	1			T1	234		T2	619		T3	99
valid_sources[0x5b]	591346	1			T1	253		T2	755		T3	99
valid_sources[0x5c]	1132924	1			T1	250		T2	797		T3	94
valid_sources[0x5d]	623308	1			T1	272		T2	825		T3	103
valid_sources[0x5e]	582655	1			T1	235		T2	629		T3	90
valid_sources[0x5f]	526498	1			T1	267		T2	611		T3	134
valid_sources[0x60]	603341	1			T1	248		T2	699		T3	91
valid_sources[0x61]	631241	1			T1	247		T2	866		T3	81
valid_sources[0x62]	525554	1			T1	262		T2	696		T3	90
valid_sources[0x63]	527141	1			T1	302		T2	735		T3	97
valid_sources[0x64]	533879	1			T1	290		T2	664		T3	97
valid_sources[0x65]	544387	1			T1	250		T2	789		T3	99
valid_sources[0x66]	2151134	1			T1	232		T2	838		T3	95
valid_sources[0x67]	537751	1			T1	283		T2	694		T3	116
valid_sources[0x68]	518213	1			T1	257		T2	705		T3	101
valid_sources[0x69]	625550	1			T1	251		T2	760		T3	86
valid_sources[0x6a]	559975	1			T1	254		T2	702		T3	111
valid_sources[0x6b]	727569	1			T1	263		T2	667		T3	91
valid_sources[0x6c]	583825	1			T1	230		T2	627		T3	106
valid_sources[0x6d]	524935	1			T1	278		T2	631		T3	107
valid_sources[0x6e]	617678	1			T1	263		T2	810		T3	113
valid_sources[0x6f]	550397	1			T1	261		T2	690		T3	103
valid_sources[0x70]	553379	1			T1	267		T2	703		T3	110
valid_sources[0x71]	538512	1			T1	240		T2	754		T3	100
valid_sources[0x72]	601472	1			T1	255		T2	690		T3	82
valid_sources[0x73]	541711	1			T1	237		T2	875		T3	92
valid_sources[0x74]	860715	1			T1	253		T2	781		T3	92
valid_sources[0x75]	578039	1			T1	270		T2	759		T3	124
valid_sources[0x76]	529880	1			T1	278		T2	675		T3	96
valid_sources[0x77]	546010	1			T1	242		T2	759		T3	91
valid_sources[0x78]	556029	1			T1	228		T2	691		T3	108
valid_sources[0x79]	554057	1			T1	244		T2	743		T3	82
valid_sources[0x7a]	526915	1			T1	247		T2	852		T3	117
valid_sources[0x7b]	570594	1			T1	260		T2	873		T3	112
valid_sources[0x7c]	528271	1			T1	264		T2	609		T3	86
valid_sources[0x7d]	535057	1			T1	266		T2	773		T3	111
valid_sources[0x7e]	552663	1			T1	250		T2	718		T3	109
valid_sources[0x7f]	554481	1			T1	258		T2	828		T3	107
valid_sources[0x80]	555113	1			T1	257		T2	692		T3	90

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

73602099

1

T1

248

T2

87116

T3

10011

values[0x0]

all_enables

biggest_size

38110730

1

T1

1448

T2

43811

T3

7159

values[0x1]

all_enables

biggest_size

38105612

1

T1

1419

T2

43378

T3

7077

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45373	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

152197

1

T2

8

T3

4160

T6

56

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	54362	1			T3	1220		T6	58		T7	30
values[0x0]	68861	1			T1	2		T2	17		T3	1576
values[0x1]	74347	1			T1	1		T2	17		T3	1799

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35073	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

162497

1

T2

9

T3

4336

T6

68

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1022	1			T3	18		T6	1		T5	1
valid_sources[0x01]	788	1			T3	25		T22	4		T26	1
valid_sources[0x02]	655	1			T3	11		T22	1		T8	1
valid_sources[0x03]	748	1			T3	11		T22	3		T8	1
valid_sources[0x04]	898	1			T3	14		T6	2		T22	1
valid_sources[0x05]	799	1			T3	15		T22	6		T18	1
valid_sources[0x06]	462	1			T3	16		T6	2		T8	1
valid_sources[0x07]	681	1			T3	12		T22	3		T8	2
valid_sources[0x08]	877	1			T3	31		T22	7		T18	1
valid_sources[0x09]	551	1			T3	15		T40	2		T75	5
valid_sources[0x0a]	608	1			T3	17		T22	1		T8	1
valid_sources[0x0b]	672	1			T2	1		T3	21		T22	6
valid_sources[0x0c]	791	1			T3	15		T11	1		T22	4
valid_sources[0x0d]	874	1			T3	14		T6	2		T79	2
valid_sources[0x0e]	641	1			T3	21		T22	2		T8	2
valid_sources[0x0f]	887	1			T3	16		T22	12		T8	1
valid_sources[0x10]	853	1			T3	17		T24	3		T22	4
valid_sources[0x11]	548	1			T3	16		T22	2		T8	2
valid_sources[0x12]	575	1			T3	9		T6	1		T22	1
valid_sources[0x13]	791	1			T1	2		T3	25		T6	1
valid_sources[0x14]	860	1			T3	13		T6	1		T8	1
valid_sources[0x15]	560	1			T3	23		T22	5		T153	1
valid_sources[0x16]	905	1			T3	19		T22	3		T40	1
valid_sources[0x17]	541	1			T2	2		T3	19		T6	3
valid_sources[0x18]	583	1			T3	32		T6	1		T22	6
valid_sources[0x19]	650	1			T1	1		T3	20		T6	2
valid_sources[0x1a]	501	1			T3	8		T22	7		T8	1
valid_sources[0x1b]	895	1			T3	20		T22	1		T39	1
valid_sources[0x1c]	596	1			T3	8		T22	7		T8	1
valid_sources[0x1d]	1029	1			T3	12		T6	1		T22	1
valid_sources[0x1e]	630	1			T3	24		T4	1		T22	3
valid_sources[0x1f]	671	1			T3	13		T6	2		T22	2
valid_sources[0x20]	694	1			T3	16		T22	5		T39	14
valid_sources[0x21]	535	1			T3	21		T22	7		T40	4
valid_sources[0x22]	853	1			T3	22		T6	1		T22	3
valid_sources[0x23]	924	1			T3	14		T6	1		T22	3
valid_sources[0x24]	621	1			T3	14		T6	1		T22	3
valid_sources[0x25]	788	1			T3	9		T6	1		T22	8
valid_sources[0x26]	1148	1			T3	27		T5	1		T22	7
valid_sources[0x27]	575	1			T3	11		T22	1		T40	3
valid_sources[0x28]	938	1			T3	12		T22	3		T40	3
valid_sources[0x29]	517	1			T3	16		T6	1		T22	3
valid_sources[0x2a]	796	1			T3	21		T22	1		T23	14
valid_sources[0x2b]	741	1			T3	17		T22	4		T39	1
valid_sources[0x2c]	847	1			T3	14		T6	2		T22	1
valid_sources[0x2d]	800	1			T3	33		T6	1		T9	1
valid_sources[0x2e]	668	1			T3	14		T22	14		T40	4
valid_sources[0x2f]	586	1			T3	1		T6	3		T22	11
valid_sources[0x30]	701	1			T3	18		T40	2		T23	7
valid_sources[0x31]	789	1			T3	16		T6	2		T22	1
valid_sources[0x32]	1138	1			T3	27		T22	9		T8	1
valid_sources[0x33]	1527	1			T3	29		T7	4		T12	1
valid_sources[0x34]	879	1			T3	10		T8	1		T40	1
valid_sources[0x35]	637	1			T3	14		T6	2		T22	4
valid_sources[0x36]	554	1			T3	14		T153	1		T23	14
valid_sources[0x37]	774	1			T3	17		T22	1		T74	1
valid_sources[0x38]	596	1			T3	22		T6	1		T24	1
valid_sources[0x39]	607	1			T3	25		T6	1		T22	3
valid_sources[0x3a]	715	1			T3	18		T24	1		T22	2
valid_sources[0x3b]	862	1			T3	12		T22	3		T18	1
valid_sources[0x3c]	715	1			T3	26		T22	2		T154	1
valid_sources[0x3d]	461	1			T3	19		T22	1		T40	1
valid_sources[0x3e]	705	1			T3	7		T6	1		T22	2
valid_sources[0x3f]	953	1			T3	28		T6	1		T22	8
valid_sources[0x40]	545	1			T3	19		T22	5		T40	4
valid_sources[0x41]	632	1			T3	19		T6	1		T22	1
valid_sources[0x42]	1070	1			T3	19		T22	5		T39	5
valid_sources[0x43]	705	1			T3	18		T6	2		T40	1
valid_sources[0x44]	606	1			T3	17		T4	1		T22	1
valid_sources[0x45]	853	1			T3	16		T22	4		T23	40
valid_sources[0x46]	699	1			T3	23		T6	1		T22	14
valid_sources[0x47]	1135	1			T3	21		T22	8		T40	1
valid_sources[0x48]	698	1			T2	3		T3	12		T22	5
valid_sources[0x49]	795	1			T3	19		T22	4		T39	1
valid_sources[0x4a]	992	1			T3	12		T6	1		T10	3
valid_sources[0x4b]	749	1			T3	18		T6	2		T22	8
valid_sources[0x4c]	860	1			T3	25		T6	3		T22	3
valid_sources[0x4d]	855	1			T3	26		T6	1		T22	2
valid_sources[0x4e]	631	1			T3	22		T24	2		T22	3
valid_sources[0x4f]	607	1			T3	15		T22	7		T40	4
valid_sources[0x50]	1145	1			T3	29		T6	3		T40	1
valid_sources[0x51]	666	1			T3	14		T22	5		T40	4
valid_sources[0x52]	1323	1			T3	13		T22	1		T8	2
valid_sources[0x53]	1056	1			T3	15		T6	1		T24	1
valid_sources[0x54]	741	1			T3	17		T22	7		T39	4
valid_sources[0x55]	891	1			T3	20		T22	1		T40	3
valid_sources[0x56]	653	1			T3	12		T6	2		T24	2
valid_sources[0x57]	514	1			T3	18		T6	2		T22	12
valid_sources[0x58]	921	1			T3	26		T6	2		T22	3
valid_sources[0x59]	598	1			T3	24		T6	1		T22	3
valid_sources[0x5a]	748	1			T2	1		T3	14		T6	2
valid_sources[0x5b]	1181	1			T3	38		T22	3		T8	1
valid_sources[0x5c]	865	1			T3	14		T22	3		T40	3
valid_sources[0x5d]	1656	1			T3	18		T22	3		T40	1
valid_sources[0x5e]	589	1			T3	12		T24	1		T22	2
valid_sources[0x5f]	990	1			T3	10		T22	6		T40	3
valid_sources[0x60]	759	1			T2	2		T3	25		T22	3
valid_sources[0x61]	942	1			T3	15		T6	2		T22	1
valid_sources[0x62]	539	1			T3	18		T6	3		T22	4
valid_sources[0x63]	933	1			T3	10		T22	5		T40	6
valid_sources[0x64]	845	1			T3	16		T6	2		T22	3
valid_sources[0x65]	485	1			T3	19		T22	3		T8	1
valid_sources[0x66]	863	1			T3	19		T24	2		T22	18
valid_sources[0x67]	592	1			T3	17		T6	2		T22	2
valid_sources[0x68]	812	1			T3	22		T6	2		T22	5
valid_sources[0x69]	617	1			T3	19		T22	5		T18	1
valid_sources[0x6a]	552	1			T3	14		T22	2		T39	2
valid_sources[0x6b]	872	1			T3	12		T22	6		T23	26
valid_sources[0x6c]	811	1			T3	27		T6	2		T22	1
valid_sources[0x6d]	586	1			T3	26		T6	2		T24	1
valid_sources[0x6e]	1000	1			T3	9		T22	2		T8	1
valid_sources[0x6f]	549	1			T3	17		T22	4		T40	1
valid_sources[0x70]	1078	1			T3	22		T23	6		T76	9
valid_sources[0x71]	579	1			T3	13		T22	5		T115	1
valid_sources[0x72]	616	1			T3	20		T22	7		T23	44
valid_sources[0x73]	560	1			T3	6		T23	1		T76	3
valid_sources[0x74]	1237	1			T3	20		T6	3		T8	1
valid_sources[0x75]	747	1			T2	2		T3	15		T6	1
valid_sources[0x76]	744	1			T3	17		T6	1		T115	1
valid_sources[0x77]	872	1			T3	18		T6	4		T4	1
valid_sources[0x78]	993	1			T3	22		T22	3		T23	58
valid_sources[0x79]	655	1			T3	26		T6	2		T10	7
valid_sources[0x7a]	784	1			T3	18		T22	9		T8	1
valid_sources[0x7b]	726	1			T3	14		T6	1		T22	3
valid_sources[0x7c]	758	1			T3	16		T6	2		T22	1
valid_sources[0x7d]	580	1			T3	17		T22	1		T74	2
valid_sources[0x7e]	746	1			T3	20		T24	3		T40	4
valid_sources[0x7f]	965	1			T3	16		T22	1		T74	2
valid_sources[0x80]	633	1			T3	16		T22	1		T8	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

41311

1

T3

1088

T6

30

T7

14

values[0x0]

all_enables

biggest_size

56819

1

T2

5

T3

1522

T6

20

values[0x1]

all_enables

biggest_size

54067

1

T2

3

T3

1550

T6

6