Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15424873

1

T1

60815

T2

17395

T3

9660

full_word

146947816

1

T1

3115

T2

174305

T3

25199

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	162372429	1			T1	63930		T2	191700		T3	34859
auto[TlIntgErrCmd]	79	1			T68	3		T69	5		T70	9
auto[TlIntgErrData]	95	1			T68	3		T69	1		T70	5
auto[TlIntgErrBoth]	86	1			T68	4		T69	4		T70	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

78362570

1

T1

32132

T2

95841

T3

12709

auto[1]

84010119

1

T1

31798

T2

95859

T3

22150

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7552866	1			T1	31884		T2	8725		T3	2498
auto[TlIntgErrNone]	partial	auto[1]	7871771	1			T1	28931		T2	8670		T3	7162
auto[TlIntgErrNone]	full_word	auto[0]	70809580	1			T1	248		T2	87116		T3	10211
auto[TlIntgErrNone]	full_word	auto[1]	76138212	1			T1	2867		T2	87189		T3	14988
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T68	1		T69	2		T70	4
auto[TlIntgErrCmd]	partial	auto[1]	33	1			T68	1		T69	2		T70	5
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T68	1		T69	1		T137	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T136	1		T143	1		T144	1
auto[TlIntgErrData]	partial	auto[0]	37	1			T68	1		T70	1		T141	2
auto[TlIntgErrData]	partial	auto[1]	51	1			T68	1		T69	1		T70	4
auto[TlIntgErrData]	full_word	auto[0]	4	1			T68	1		T135	1		T137	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T140	1		T144	1		T145	1
auto[TlIntgErrBoth]	partial	auto[0]	32	1			T68	1		T70	3		T141	1
auto[TlIntgErrBoth]	partial	auto[1]	45	1			T68	2		T69	2		T70	1
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T68	1		T69	2		T70	2
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T138	1		-	-		-	-