Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	779120	1			T5	29878		T24	69		T41	75
auto[1]	10589845	1			T1	30559		T2	40055		T3	1080
auto[2]	582224	1			T6	1		T5	25575		T24	43
auto[3]	10346993	1			T1	30193		T2	39764		T3	566

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14064076	1			T1	291		T2	66599		T3	1360
auto[1]	2067933	1			T1	2811		T2	6328		T3	128
auto[2]	2117958	1			T1	5265		T2	6293		T3	144
auto[3]	4048215	1			T1	52385		T2	599		T3	14

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8778169

1

T1

60749

T2

79817

T3

1646

auto[1]

13520013

1

T1

3

T2

2

T6

2

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	320205	1			T24	55		T41	64		T39	2950
auto[0]	auto[0]	auto[1]	33276	1			T24	8		T41	3		T39	295
auto[0]	auto[0]	auto[2]	33378	1			T24	6		T41	8		T39	297
auto[0]	auto[0]	auto[3]	54433	1			T39	30		T43	1		T94	917
auto[0]	auto[1]	auto[0]	3009162	1			T1	19		T2	33399		T3	900
auto[0]	auto[1]	auto[1]	321119	1			T1	216		T2	3025		T3	76
auto[0]	auto[1]	auto[2]	336841	1			T1	2811		T2	3303		T3	98
auto[0]	auto[1]	auto[3]	424588	1			T1	27511		T2	327		T3	6
auto[0]	auto[2]	auto[0]	224875	1			T6	1		T39	1920		T146	175
auto[0]	auto[2]	auto[1]	26257	1			T39	174		T146	20		T19	578
auto[0]	auto[2]	auto[2]	29921	1			T24	39		T41	22		T39	172
auto[0]	auto[2]	auto[3]	38860	1			T24	4		T41	2		T39	17
auto[0]	auto[3]	auto[0]	2876780	1			T1	272		T2	33198		T3	460
auto[0]	auto[3]	auto[1]	320181	1			T1	2595		T2	3303		T3	52
auto[0]	auto[3]	auto[2]	341665	1			T1	2454		T2	2990		T3	46
auto[0]	auto[3]	auto[3]	386628	1			T1	24871		T2	272		T3	8
auto[1]	auto[0]	auto[0]	11151	1			T5	957		T19	1		T150	728
auto[1]	auto[0]	auto[1]	50117	1			T5	4440		T150	3261		T151	1895
auto[1]	auto[0]	auto[2]	50230	1			T5	4429		T150	3197		T151	2062
auto[1]	auto[0]	auto[3]	226330	1			T5	20052		T150	14603		T151	9207
auto[1]	auto[1]	auto[0]	3809599	1			T2	1		T5	155		T54	58785
auto[1]	auto[1]	auto[1]	652583	1			T5	4570		T54	5142		T108	2584
auto[1]	auto[1]	auto[2]	644102	1			T5	686		T54	5891		T108	2494
auto[1]	auto[1]	auto[3]	1391851	1			T1	2		T4	1		T5	20088
auto[1]	auto[2]	auto[0]	8068	1			T5	907		T150	709		T151	293
auto[1]	auto[2]	auto[1]	35641	1			T5	3979		T150	2993		T151	1225
auto[1]	auto[2]	auto[2]	39581	1			T5	3831		T150	2174		T151	2180
auto[1]	auto[2]	auto[3]	179021	1			T5	16858		T150	9782		T151	10041
auto[1]	auto[3]	auto[0]	3804236	1			T2	1		T6	2		T10	1
auto[1]	auto[3]	auto[1]	628759	1			T5	328		T54	5804		T108	2527
auto[1]	auto[3]	auto[2]	642240	1			T5	3787		T54	5236		T108	2474
auto[1]	auto[3]	auto[3]	1346504	1			T1	1		T4	6		T5	17336