Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1104773011	229556	0	0
ctrl_regwen_rd_A	1104773011	3879	0	0
exec_rd_A	1104773011	3777	0	0
exec_regwen_rd_A	1104773011	4283	0	0
readback_rd_A	1104773011	2798	0	0
readback_regwen_rd_A	1104773011	2522	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1104773011	229556	0	0
T3	161756	9557	0	0
T4	157977	0	0	0
T5	196141	0	0	0
T6	476461	0	0	0
T7	109589	0	0	0
T9	51946	0	0	0
T10	126578	0	0	0
T11	72151	0	0	0
T22	0	1905	0	0
T23	0	8770	0	0
T24	182577	0	0	0
T44	0	7886	0	0
T47	0	4098	0	0
T48	0	6135	0	0
T54	329072	0	0	0
T64	0	4888	0	0
T76	0	2383	0	0
T77	0	1454	0	0
T78	0	1133	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1104773011	3879	0	0
T48	179085	396	0	0
T49	138874	0	0	0
T97	390056	0	0	0
T113	264868	0	0	0
T116	0	177	0	0
T117	0	248	0	0
T118	0	193	0	0
T119	0	229	0	0
T120	0	165	0	0
T121	0	231	0	0
T122	0	142	0	0
T123	0	325	0	0
T124	0	150	0	0
T125	820325	0	0	0
T126	174848	0	0	0
T127	84617	0	0	0
T128	157995	0	0	0
T129	967251	0	0	0
T130	183810	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1104773011	3777	0	0
T48	179085	346	0	0
T49	138874	0	0	0
T97	390056	0	0	0
T113	264868	0	0	0
T116	0	134	0	0
T117	0	181	0	0
T118	0	251	0	0
T119	0	222	0	0
T120	0	145	0	0
T121	0	172	0	0
T122	0	155	0	0
T123	0	390	0	0
T124	0	74	0	0
T125	820325	0	0	0
T126	174848	0	0	0
T127	84617	0	0	0
T128	157995	0	0	0
T129	967251	0	0	0
T130	183810	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1104773011	4283	0	0
T48	179085	600	0	0
T49	138874	0	0	0
T97	390056	0	0	0
T113	264868	0	0	0
T116	0	167	0	0
T117	0	243	0	0
T118	0	191	0	0
T119	0	251	0	0
T120	0	185	0	0
T121	0	238	0	0
T122	0	101	0	0
T123	0	509	0	0
T124	0	127	0	0
T125	820325	0	0	0
T126	174848	0	0	0
T127	84617	0	0	0
T128	157995	0	0	0
T129	967251	0	0	0
T130	183810	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1104773011	2798	0	0
T48	179085	402	0	0
T49	138874	0	0	0
T97	390056	0	0	0
T113	264868	0	0	0
T116	0	121	0	0
T117	0	222	0	0
T118	0	235	0	0
T119	0	185	0	0
T120	0	126	0	0
T121	0	226	0	0
T122	0	106	0	0
T123	0	346	0	0
T124	0	76	0	0
T125	820325	0	0	0
T126	174848	0	0	0
T127	84617	0	0	0
T128	157995	0	0	0
T129	967251	0	0	0
T130	183810	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1104773011	2522	0	0
T48	179085	294	0	0
T49	138874	0	0	0
T97	390056	0	0	0
T113	264868	0	0	0
T116	0	126	0	0
T117	0	162	0	0
T118	0	191	0	0
T119	0	154	0	0
T120	0	103	0	0
T121	0	161	0	0
T122	0	91	0	0
T123	0	519	0	0
T124	0	66	0	0
T125	820325	0	0	0
T126	174848	0	0	0
T127	84617	0	0	0
T128	157995	0	0	0
T129	967251	0	0	0
T130	183810	0	0	0