| T793 |
/workspace/coverage/default/43.sram_ctrl_alert_test.1916626464 |
|
|
Jul 07 05:00:10 PM PDT 24 |
Jul 07 05:00:11 PM PDT 24 |
27083463 ps |
| T794 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.2111608469 |
|
|
Jul 07 04:55:27 PM PDT 24 |
Jul 07 04:57:37 PM PDT 24 |
24768863296 ps |
| T795 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.2103469574 |
|
|
Jul 07 04:59:50 PM PDT 24 |
Jul 07 05:05:43 PM PDT 24 |
4648897756 ps |
| T796 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1983292672 |
|
|
Jul 07 04:56:32 PM PDT 24 |
Jul 07 04:57:03 PM PDT 24 |
1081677596 ps |
| T797 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.3158535479 |
|
|
Jul 07 04:58:58 PM PDT 24 |
Jul 07 04:59:53 PM PDT 24 |
43847939248 ps |
| T798 |
/workspace/coverage/default/44.sram_ctrl_smoke.1754716641 |
|
|
Jul 07 05:00:09 PM PDT 24 |
Jul 07 05:00:28 PM PDT 24 |
3925571210 ps |
| T799 |
/workspace/coverage/default/17.sram_ctrl_smoke.1552607110 |
|
|
Jul 07 04:54:22 PM PDT 24 |
Jul 07 04:55:54 PM PDT 24 |
2633033038 ps |
| T800 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.2164243729 |
|
|
Jul 07 04:58:41 PM PDT 24 |
Jul 07 04:58:48 PM PDT 24 |
2719549117 ps |
| T801 |
/workspace/coverage/default/10.sram_ctrl_regwen.458488056 |
|
|
Jul 07 04:53:41 PM PDT 24 |
Jul 07 05:06:38 PM PDT 24 |
49601402824 ps |
| T802 |
/workspace/coverage/default/2.sram_ctrl_smoke.2327721274 |
|
|
Jul 07 04:53:22 PM PDT 24 |
Jul 07 04:53:31 PM PDT 24 |
460145072 ps |
| T803 |
/workspace/coverage/default/30.sram_ctrl_smoke.1433318339 |
|
|
Jul 07 04:56:58 PM PDT 24 |
Jul 07 04:57:04 PM PDT 24 |
370980668 ps |
| T804 |
/workspace/coverage/default/35.sram_ctrl_alert_test.1882716593 |
|
|
Jul 07 04:58:27 PM PDT 24 |
Jul 07 04:58:28 PM PDT 24 |
40769237 ps |
| T805 |
/workspace/coverage/default/5.sram_ctrl_partial_access.3433247374 |
|
|
Jul 07 04:53:32 PM PDT 24 |
Jul 07 04:53:57 PM PDT 24 |
3945818165 ps |
| T806 |
/workspace/coverage/default/34.sram_ctrl_smoke.781893672 |
|
|
Jul 07 04:57:57 PM PDT 24 |
Jul 07 04:58:03 PM PDT 24 |
2843661974 ps |
| T807 |
/workspace/coverage/default/6.sram_ctrl_alert_test.1375873513 |
|
|
Jul 07 04:53:35 PM PDT 24 |
Jul 07 04:53:36 PM PDT 24 |
32493662 ps |
| T808 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.816611490 |
|
|
Jul 07 04:57:40 PM PDT 24 |
Jul 07 04:57:43 PM PDT 24 |
1400245939 ps |
| T809 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.3333409768 |
|
|
Jul 07 04:53:31 PM PDT 24 |
Jul 07 05:06:55 PM PDT 24 |
8898537327 ps |
| T810 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.3296395194 |
|
|
Jul 07 05:01:23 PM PDT 24 |
Jul 07 05:01:27 PM PDT 24 |
682545365 ps |
| T811 |
/workspace/coverage/default/47.sram_ctrl_stress_all.219604081 |
|
|
Jul 07 05:01:10 PM PDT 24 |
Jul 07 07:11:33 PM PDT 24 |
517265374626 ps |
| T812 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.2606823538 |
|
|
Jul 07 05:01:05 PM PDT 24 |
Jul 07 05:01:09 PM PDT 24 |
1400960170 ps |
| T813 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.81327387 |
|
|
Jul 07 05:00:47 PM PDT 24 |
Jul 07 05:01:53 PM PDT 24 |
11551747344 ps |
| T814 |
/workspace/coverage/default/3.sram_ctrl_stress_all.1957652109 |
|
|
Jul 07 04:53:24 PM PDT 24 |
Jul 07 06:01:32 PM PDT 24 |
19311264361 ps |
| T815 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.295697104 |
|
|
Jul 07 04:54:11 PM PDT 24 |
Jul 07 04:54:15 PM PDT 24 |
1410267343 ps |
| T816 |
/workspace/coverage/default/36.sram_ctrl_stress_all.1415561698 |
|
|
Jul 07 04:58:37 PM PDT 24 |
Jul 07 05:18:40 PM PDT 24 |
42329080049 ps |
| T817 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.1427076511 |
|
|
Jul 07 04:54:29 PM PDT 24 |
Jul 07 04:57:38 PM PDT 24 |
34553077478 ps |
| T818 |
/workspace/coverage/default/41.sram_ctrl_partial_access.3286262727 |
|
|
Jul 07 04:59:35 PM PDT 24 |
Jul 07 05:00:00 PM PDT 24 |
4136633903 ps |
| T819 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.2303917679 |
|
|
Jul 07 05:00:17 PM PDT 24 |
Jul 07 05:00:20 PM PDT 24 |
1375440295 ps |
| T820 |
/workspace/coverage/default/18.sram_ctrl_partial_access.2644326470 |
|
|
Jul 07 04:54:32 PM PDT 24 |
Jul 07 04:55:00 PM PDT 24 |
7461556276 ps |
| T821 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.4169985819 |
|
|
Jul 07 04:55:30 PM PDT 24 |
Jul 07 04:55:34 PM PDT 24 |
1404509540 ps |
| T822 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.1925554072 |
|
|
Jul 07 04:55:51 PM PDT 24 |
Jul 07 04:58:14 PM PDT 24 |
7491747171 ps |
| T823 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.3210400821 |
|
|
Jul 07 04:56:10 PM PDT 24 |
Jul 07 04:56:14 PM PDT 24 |
1865193254 ps |
| T824 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.4245783506 |
|
|
Jul 07 04:54:42 PM PDT 24 |
Jul 07 05:05:28 PM PDT 24 |
120613852980 ps |
| T825 |
/workspace/coverage/default/38.sram_ctrl_partial_access.312536130 |
|
|
Jul 07 04:59:00 PM PDT 24 |
Jul 07 04:59:12 PM PDT 24 |
1919953363 ps |
| T826 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.1799074909 |
|
|
Jul 07 04:57:53 PM PDT 24 |
Jul 07 04:57:57 PM PDT 24 |
346539773 ps |
| T827 |
/workspace/coverage/default/38.sram_ctrl_executable.167303227 |
|
|
Jul 07 04:59:04 PM PDT 24 |
Jul 07 05:01:22 PM PDT 24 |
31591821737 ps |
| T828 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2365713768 |
|
|
Jul 07 04:53:37 PM PDT 24 |
Jul 07 04:54:13 PM PDT 24 |
8655008787 ps |
| T829 |
/workspace/coverage/default/25.sram_ctrl_regwen.1266375208 |
|
|
Jul 07 04:56:10 PM PDT 24 |
Jul 07 05:11:16 PM PDT 24 |
6585253939 ps |
| T830 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.2095732552 |
|
|
Jul 07 04:58:32 PM PDT 24 |
Jul 07 05:03:16 PM PDT 24 |
29124163648 ps |
| T831 |
/workspace/coverage/default/11.sram_ctrl_regwen.575746096 |
|
|
Jul 07 04:53:48 PM PDT 24 |
Jul 07 05:08:30 PM PDT 24 |
47281276701 ps |
| T832 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.963729359 |
|
|
Jul 07 04:53:14 PM PDT 24 |
Jul 07 04:58:53 PM PDT 24 |
4378694493 ps |
| T833 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.701105098 |
|
|
Jul 07 04:54:32 PM PDT 24 |
Jul 07 05:08:55 PM PDT 24 |
11771470594 ps |
| T834 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.1754845969 |
|
|
Jul 07 04:59:41 PM PDT 24 |
Jul 07 04:59:45 PM PDT 24 |
709684768 ps |
| T835 |
/workspace/coverage/default/0.sram_ctrl_stress_all.3617458329 |
|
|
Jul 07 04:53:14 PM PDT 24 |
Jul 07 05:55:35 PM PDT 24 |
123247904371 ps |
| T836 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.3195549783 |
|
|
Jul 07 04:54:19 PM PDT 24 |
Jul 07 05:06:32 PM PDT 24 |
14616521719 ps |
| T837 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.1804348797 |
|
|
Jul 07 04:53:20 PM PDT 24 |
Jul 07 04:53:44 PM PDT 24 |
3117279006 ps |
| T838 |
/workspace/coverage/default/20.sram_ctrl_alert_test.1033415473 |
|
|
Jul 07 04:55:04 PM PDT 24 |
Jul 07 04:55:05 PM PDT 24 |
76553937 ps |
| T839 |
/workspace/coverage/default/37.sram_ctrl_stress_all.2844177002 |
|
|
Jul 07 04:58:54 PM PDT 24 |
Jul 07 05:49:26 PM PDT 24 |
271557800047 ps |
| T840 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2315617944 |
|
|
Jul 07 05:01:23 PM PDT 24 |
Jul 07 05:04:18 PM PDT 24 |
19611737601 ps |
| T841 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.2034366785 |
|
|
Jul 07 04:54:02 PM PDT 24 |
Jul 07 04:54:34 PM PDT 24 |
1751169037 ps |
| T842 |
/workspace/coverage/default/36.sram_ctrl_regwen.3077447411 |
|
|
Jul 07 04:58:31 PM PDT 24 |
Jul 07 05:10:29 PM PDT 24 |
8942400372 ps |
| T843 |
/workspace/coverage/default/42.sram_ctrl_regwen.1280880746 |
|
|
Jul 07 04:59:51 PM PDT 24 |
Jul 07 05:03:01 PM PDT 24 |
3568566838 ps |
| T844 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.863546342 |
|
|
Jul 07 04:59:04 PM PDT 24 |
Jul 07 04:59:41 PM PDT 24 |
2531153863 ps |
| T845 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2810094435 |
|
|
Jul 07 04:53:41 PM PDT 24 |
Jul 07 04:57:37 PM PDT 24 |
7750613315 ps |
| T846 |
/workspace/coverage/default/16.sram_ctrl_regwen.7908520 |
|
|
Jul 07 04:54:20 PM PDT 24 |
Jul 07 05:09:47 PM PDT 24 |
21898117955 ps |
| T847 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.3069835843 |
|
|
Jul 07 04:53:49 PM PDT 24 |
Jul 07 04:56:49 PM PDT 24 |
9561991888 ps |
| T848 |
/workspace/coverage/default/4.sram_ctrl_stress_all.900933228 |
|
|
Jul 07 04:53:38 PM PDT 24 |
Jul 07 06:07:46 PM PDT 24 |
487868273064 ps |
| T849 |
/workspace/coverage/default/45.sram_ctrl_stress_all.3075233766 |
|
|
Jul 07 05:00:39 PM PDT 24 |
Jul 07 06:10:36 PM PDT 24 |
261891544044 ps |
| T850 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.1606730228 |
|
|
Jul 07 04:55:38 PM PDT 24 |
Jul 07 04:58:04 PM PDT 24 |
786179926 ps |
| T851 |
/workspace/coverage/default/18.sram_ctrl_regwen.341553587 |
|
|
Jul 07 04:54:37 PM PDT 24 |
Jul 07 05:12:02 PM PDT 24 |
18084235231 ps |
| T852 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.750888231 |
|
|
Jul 07 04:54:50 PM PDT 24 |
Jul 07 05:00:41 PM PDT 24 |
51831860892 ps |
| T853 |
/workspace/coverage/default/48.sram_ctrl_smoke.2607425604 |
|
|
Jul 07 05:01:13 PM PDT 24 |
Jul 07 05:01:26 PM PDT 24 |
895521978 ps |
| T854 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.1366172111 |
|
|
Jul 07 04:57:01 PM PDT 24 |
Jul 07 04:57:29 PM PDT 24 |
730711669 ps |
| T855 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.1541065958 |
|
|
Jul 07 04:54:54 PM PDT 24 |
Jul 07 04:56:36 PM PDT 24 |
10787134669 ps |
| T856 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.3064564773 |
|
|
Jul 07 05:00:13 PM PDT 24 |
Jul 07 05:06:54 PM PDT 24 |
5909541906 ps |
| T857 |
/workspace/coverage/default/13.sram_ctrl_executable.1446745648 |
|
|
Jul 07 04:53:52 PM PDT 24 |
Jul 07 05:03:07 PM PDT 24 |
99651888516 ps |
| T858 |
/workspace/coverage/default/1.sram_ctrl_regwen.697298949 |
|
|
Jul 07 04:53:16 PM PDT 24 |
Jul 07 05:00:14 PM PDT 24 |
5257979672 ps |
| T859 |
/workspace/coverage/default/29.sram_ctrl_partial_access.2994093723 |
|
|
Jul 07 04:56:47 PM PDT 24 |
Jul 07 04:57:06 PM PDT 24 |
884495991 ps |
| T860 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.2278015703 |
|
|
Jul 07 04:53:29 PM PDT 24 |
Jul 07 04:53:38 PM PDT 24 |
2710900849 ps |
| T861 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2165841571 |
|
|
Jul 07 05:00:38 PM PDT 24 |
Jul 07 05:01:01 PM PDT 24 |
1570574722 ps |
| T862 |
/workspace/coverage/default/15.sram_ctrl_smoke.61207014 |
|
|
Jul 07 04:54:07 PM PDT 24 |
Jul 07 04:55:36 PM PDT 24 |
3810270127 ps |
| T863 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.3332039859 |
|
|
Jul 07 04:59:27 PM PDT 24 |
Jul 07 05:03:04 PM PDT 24 |
7921587444 ps |
| T864 |
/workspace/coverage/default/13.sram_ctrl_bijection.592494128 |
|
|
Jul 07 04:53:51 PM PDT 24 |
Jul 07 05:12:16 PM PDT 24 |
48175097682 ps |
| T865 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.738408027 |
|
|
Jul 07 04:59:30 PM PDT 24 |
Jul 07 05:00:57 PM PDT 24 |
3201375140 ps |
| T866 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.3103373266 |
|
|
Jul 07 04:54:42 PM PDT 24 |
Jul 07 05:05:06 PM PDT 24 |
12920497994 ps |
| T867 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.2578844292 |
|
|
Jul 07 04:56:26 PM PDT 24 |
Jul 07 04:58:28 PM PDT 24 |
798796531 ps |
| T868 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.2220801890 |
|
|
Jul 07 04:53:52 PM PDT 24 |
Jul 07 04:57:00 PM PDT 24 |
35879434967 ps |
| T869 |
/workspace/coverage/default/25.sram_ctrl_bijection.2115109422 |
|
|
Jul 07 04:56:01 PM PDT 24 |
Jul 07 05:18:08 PM PDT 24 |
315565395216 ps |
| T870 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.957113280 |
|
|
Jul 07 04:53:47 PM PDT 24 |
Jul 07 04:59:03 PM PDT 24 |
4763835278 ps |
| T871 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.1298070471 |
|
|
Jul 07 04:53:41 PM PDT 24 |
Jul 07 04:56:08 PM PDT 24 |
4865048302 ps |
| T872 |
/workspace/coverage/default/14.sram_ctrl_partial_access.718403342 |
|
|
Jul 07 04:54:02 PM PDT 24 |
Jul 07 04:54:12 PM PDT 24 |
616412954 ps |
| T873 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.61352048 |
|
|
Jul 07 04:53:50 PM PDT 24 |
Jul 07 04:54:36 PM PDT 24 |
1389759883 ps |
| T874 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1608476883 |
|
|
Jul 07 04:53:17 PM PDT 24 |
Jul 07 04:55:37 PM PDT 24 |
1169690791 ps |
| T875 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3303735463 |
|
|
Jul 07 04:53:57 PM PDT 24 |
Jul 07 04:57:30 PM PDT 24 |
3668128958 ps |
| T876 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.2871178451 |
|
|
Jul 07 04:53:24 PM PDT 24 |
Jul 07 04:56:59 PM PDT 24 |
3188767217 ps |
| T877 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2662636267 |
|
|
Jul 07 04:57:54 PM PDT 24 |
Jul 07 04:58:13 PM PDT 24 |
531741296 ps |
| T878 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.3787052028 |
|
|
Jul 07 04:57:01 PM PDT 24 |
Jul 07 05:07:25 PM PDT 24 |
55746180465 ps |
| T879 |
/workspace/coverage/default/13.sram_ctrl_regwen.2041493708 |
|
|
Jul 07 04:53:52 PM PDT 24 |
Jul 07 05:03:42 PM PDT 24 |
6907071877 ps |
| T880 |
/workspace/coverage/default/23.sram_ctrl_alert_test.4056278260 |
|
|
Jul 07 04:55:42 PM PDT 24 |
Jul 07 04:55:43 PM PDT 24 |
18551007 ps |
| T881 |
/workspace/coverage/default/46.sram_ctrl_alert_test.389201046 |
|
|
Jul 07 05:00:53 PM PDT 24 |
Jul 07 05:00:53 PM PDT 24 |
31661481 ps |
| T882 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.2372422184 |
|
|
Jul 07 04:55:34 PM PDT 24 |
Jul 07 05:00:29 PM PDT 24 |
4272909636 ps |
| T883 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.2716602289 |
|
|
Jul 07 04:54:49 PM PDT 24 |
Jul 07 05:19:19 PM PDT 24 |
127448369523 ps |
| T884 |
/workspace/coverage/default/48.sram_ctrl_partial_access.2455981101 |
|
|
Jul 07 05:01:16 PM PDT 24 |
Jul 07 05:01:47 PM PDT 24 |
461636611 ps |
| T885 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.1813318044 |
|
|
Jul 07 04:55:23 PM PDT 24 |
Jul 07 04:55:51 PM PDT 24 |
3442903210 ps |
| T886 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.3939352999 |
|
|
Jul 07 04:54:53 PM PDT 24 |
Jul 07 04:55:11 PM PDT 24 |
2813370833 ps |
| T887 |
/workspace/coverage/default/20.sram_ctrl_regwen.3796895631 |
|
|
Jul 07 04:54:55 PM PDT 24 |
Jul 07 05:16:01 PM PDT 24 |
29218612410 ps |
| T888 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1072860044 |
|
|
Jul 07 05:01:01 PM PDT 24 |
Jul 07 05:01:19 PM PDT 24 |
732197425 ps |
| T889 |
/workspace/coverage/default/48.sram_ctrl_executable.331527165 |
|
|
Jul 07 05:01:24 PM PDT 24 |
Jul 07 05:02:54 PM PDT 24 |
2300278015 ps |
| T890 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.3948629745 |
|
|
Jul 07 04:56:20 PM PDT 24 |
Jul 07 04:56:24 PM PDT 24 |
1988140776 ps |
| T891 |
/workspace/coverage/default/16.sram_ctrl_executable.3202672634 |
|
|
Jul 07 04:54:20 PM PDT 24 |
Jul 07 05:14:40 PM PDT 24 |
47944039028 ps |
| T892 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.873645448 |
|
|
Jul 07 04:59:39 PM PDT 24 |
Jul 07 05:01:30 PM PDT 24 |
796427774 ps |
| T893 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.4034438787 |
|
|
Jul 07 05:00:13 PM PDT 24 |
Jul 07 05:00:48 PM PDT 24 |
3316386186 ps |
| T894 |
/workspace/coverage/default/6.sram_ctrl_bijection.1474429765 |
|
|
Jul 07 04:53:26 PM PDT 24 |
Jul 07 05:36:59 PM PDT 24 |
158314700415 ps |
| T895 |
/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.2480209724 |
|
|
Jul 07 04:57:16 PM PDT 24 |
Jul 07 04:58:07 PM PDT 24 |
1532045878 ps |
| T896 |
/workspace/coverage/default/22.sram_ctrl_access_during_key_req.4025684467 |
|
|
Jul 07 04:55:25 PM PDT 24 |
Jul 07 05:19:44 PM PDT 24 |
63254724961 ps |
| T897 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.106160312 |
|
|
Jul 07 05:01:08 PM PDT 24 |
Jul 07 05:01:51 PM PDT 24 |
4791765302 ps |
| T898 |
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.1038711718 |
|
|
Jul 07 04:57:46 PM PDT 24 |
Jul 07 05:15:48 PM PDT 24 |
13881706779 ps |
| T899 |
/workspace/coverage/default/32.sram_ctrl_executable.2859026062 |
|
|
Jul 07 04:57:34 PM PDT 24 |
Jul 07 05:14:13 PM PDT 24 |
71587652536 ps |
| T900 |
/workspace/coverage/default/3.sram_ctrl_bijection.2181419714 |
|
|
Jul 07 04:53:24 PM PDT 24 |
Jul 07 05:39:58 PM PDT 24 |
158613362927 ps |
| T901 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.3162374515 |
|
|
Jul 07 04:53:28 PM PDT 24 |
Jul 07 04:56:33 PM PDT 24 |
19543883927 ps |
| T902 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1160929793 |
|
|
Jul 07 04:54:53 PM PDT 24 |
Jul 07 04:55:04 PM PDT 24 |
434215405 ps |
| T903 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.3235566907 |
|
|
Jul 07 04:55:01 PM PDT 24 |
Jul 07 04:58:06 PM PDT 24 |
19107484105 ps |
| T904 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.3644151994 |
|
|
Jul 07 04:59:15 PM PDT 24 |
Jul 07 05:25:32 PM PDT 24 |
57389865515 ps |
| T905 |
/workspace/coverage/default/6.sram_ctrl_partial_access.202348397 |
|
|
Jul 07 04:53:34 PM PDT 24 |
Jul 07 04:53:39 PM PDT 24 |
394403505 ps |
| T906 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.3700043603 |
|
|
Jul 07 04:53:20 PM PDT 24 |
Jul 07 04:57:07 PM PDT 24 |
10963040189 ps |
| T907 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.2742367294 |
|
|
Jul 07 04:56:33 PM PDT 24 |
Jul 07 05:01:29 PM PDT 24 |
13376185086 ps |
| T908 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.439532517 |
|
|
Jul 07 04:53:43 PM PDT 24 |
Jul 07 05:03:57 PM PDT 24 |
9579180550 ps |
| T909 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.2897855633 |
|
|
Jul 07 04:53:52 PM PDT 24 |
Jul 07 04:53:56 PM PDT 24 |
350345168 ps |
| T910 |
/workspace/coverage/default/13.sram_ctrl_alert_test.4101806212 |
|
|
Jul 07 04:53:56 PM PDT 24 |
Jul 07 04:53:57 PM PDT 24 |
38458926 ps |
| T911 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.61002152 |
|
|
Jul 07 04:53:36 PM PDT 24 |
Jul 07 04:56:03 PM PDT 24 |
2632747001 ps |
| T912 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.1526358946 |
|
|
Jul 07 04:53:15 PM PDT 24 |
Jul 07 04:56:13 PM PDT 24 |
27724816720 ps |
| T913 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.2534899129 |
|
|
Jul 07 04:58:20 PM PDT 24 |
Jul 07 04:58:58 PM PDT 24 |
17202248831 ps |
| T914 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.1323634288 |
|
|
Jul 07 04:59:28 PM PDT 24 |
Jul 07 05:03:41 PM PDT 24 |
8923386017 ps |
| T915 |
/workspace/coverage/default/40.sram_ctrl_regwen.2853807846 |
|
|
Jul 07 04:59:34 PM PDT 24 |
Jul 07 05:18:13 PM PDT 24 |
17295257877 ps |
| T916 |
/workspace/coverage/default/18.sram_ctrl_alert_test.1207448109 |
|
|
Jul 07 04:54:41 PM PDT 24 |
Jul 07 04:54:42 PM PDT 24 |
35958885 ps |
| T917 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.3230225403 |
|
|
Jul 07 04:53:34 PM PDT 24 |
Jul 07 05:00:17 PM PDT 24 |
230880641952 ps |
| T918 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.978145582 |
|
|
Jul 07 05:00:31 PM PDT 24 |
Jul 07 05:01:36 PM PDT 24 |
6058354697 ps |
| T919 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.2614192351 |
|
|
Jul 07 04:54:08 PM PDT 24 |
Jul 07 04:54:11 PM PDT 24 |
360183220 ps |
| T920 |
/workspace/coverage/default/26.sram_ctrl_partial_access.2660695552 |
|
|
Jul 07 04:56:13 PM PDT 24 |
Jul 07 04:58:03 PM PDT 24 |
1009001391 ps |
| T921 |
/workspace/coverage/default/1.sram_ctrl_executable.2016617570 |
|
|
Jul 07 04:53:18 PM PDT 24 |
Jul 07 05:07:33 PM PDT 24 |
6734547847 ps |
| T922 |
/workspace/coverage/default/11.sram_ctrl_partial_access.112617697 |
|
|
Jul 07 04:53:46 PM PDT 24 |
Jul 07 04:54:14 PM PDT 24 |
18950941253 ps |
| T923 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.569968604 |
|
|
Jul 07 04:53:12 PM PDT 24 |
Jul 07 04:53:46 PM PDT 24 |
1480726475 ps |
| T924 |
/workspace/coverage/default/8.sram_ctrl_partial_access.3526807292 |
|
|
Jul 07 04:53:43 PM PDT 24 |
Jul 07 04:54:03 PM PDT 24 |
1878903936 ps |
| T925 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.623800731 |
|
|
Jul 07 04:56:13 PM PDT 24 |
Jul 07 05:29:46 PM PDT 24 |
23083999476 ps |
| T926 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.94322691 |
|
|
Jul 07 04:56:21 PM PDT 24 |
Jul 07 05:00:09 PM PDT 24 |
3687137387 ps |
| T927 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.2927800745 |
|
|
Jul 07 04:57:07 PM PDT 24 |
Jul 07 04:57:10 PM PDT 24 |
356731699 ps |
| T928 |
/workspace/coverage/default/29.sram_ctrl_executable.2921601629 |
|
|
Jul 07 04:56:52 PM PDT 24 |
Jul 07 04:59:40 PM PDT 24 |
6564002985 ps |
| T929 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.508396160 |
|
|
Jul 07 04:56:09 PM PDT 24 |
Jul 07 04:59:12 PM PDT 24 |
97858305492 ps |
| T930 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.3349672538 |
|
|
Jul 07 04:53:23 PM PDT 24 |
Jul 07 05:03:56 PM PDT 24 |
3938173281 ps |
| T931 |
/workspace/coverage/default/19.sram_ctrl_executable.742658483 |
|
|
Jul 07 04:54:45 PM PDT 24 |
Jul 07 05:09:18 PM PDT 24 |
12836869281 ps |
| T932 |
/workspace/coverage/default/11.sram_ctrl_executable.817800553 |
|
|
Jul 07 04:53:49 PM PDT 24 |
Jul 07 05:08:45 PM PDT 24 |
16186305958 ps |
| T933 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.1172170609 |
|
|
Jul 07 05:01:10 PM PDT 24 |
Jul 07 05:06:52 PM PDT 24 |
57523330922 ps |
| T934 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.1842974165 |
|
|
Jul 07 04:54:04 PM PDT 24 |
Jul 07 05:18:32 PM PDT 24 |
73506513838 ps |
| T935 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.2363566043 |
|
|
Jul 07 04:54:20 PM PDT 24 |
Jul 07 04:55:14 PM PDT 24 |
7227343874 ps |
| T936 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.2383269833 |
|
|
Jul 07 04:59:15 PM PDT 24 |
Jul 07 05:04:49 PM PDT 24 |
19751015265 ps |
| T937 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.693341299 |
|
|
Jul 07 04:56:13 PM PDT 24 |
Jul 07 05:00:58 PM PDT 24 |
74890092611 ps |
| T938 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.305827560 |
|
|
Jul 07 04:58:21 PM PDT 24 |
Jul 07 05:01:27 PM PDT 24 |
21147567329 ps |
| T939 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.1200859870 |
|
|
Jul 07 04:54:44 PM PDT 24 |
Jul 07 05:10:06 PM PDT 24 |
80631110262 ps |
| T940 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.23553428 |
|
|
Jul 07 04:55:07 PM PDT 24 |
Jul 07 05:01:12 PM PDT 24 |
57851130142 ps |
| T941 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.2524108007 |
|
|
Jul 07 04:53:23 PM PDT 24 |
Jul 07 04:53:27 PM PDT 24 |
768392208 ps |
| T942 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.2976762494 |
|
|
Jul 07 04:57:25 PM PDT 24 |
Jul 07 04:58:21 PM PDT 24 |
1426315109 ps |
| T71 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3031626785 |
|
|
Jul 07 04:52:03 PM PDT 24 |
Jul 07 04:52:04 PM PDT 24 |
18247139 ps |
| T72 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.58484571 |
|
|
Jul 07 04:52:30 PM PDT 24 |
Jul 07 04:52:32 PM PDT 24 |
79928913 ps |
| T73 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2308835932 |
|
|
Jul 07 04:52:07 PM PDT 24 |
Jul 07 04:52:57 PM PDT 24 |
7080562066 ps |
| T80 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3579606466 |
|
|
Jul 07 04:52:01 PM PDT 24 |
Jul 07 04:52:04 PM PDT 24 |
525393295 ps |
| T943 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2256600424 |
|
|
Jul 07 04:52:13 PM PDT 24 |
Jul 07 04:52:18 PM PDT 24 |
1170619366 ps |
| T68 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1971946076 |
|
|
Jul 07 04:52:17 PM PDT 24 |
Jul 07 04:52:19 PM PDT 24 |
113989346 ps |
| T944 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3417750768 |
|
|
Jul 07 04:52:09 PM PDT 24 |
Jul 07 04:52:14 PM PDT 24 |
3467394158 ps |
| T945 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.432473943 |
|
|
Jul 07 04:52:05 PM PDT 24 |
Jul 07 04:52:10 PM PDT 24 |
81996755 ps |
| T81 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3836593115 |
|
|
Jul 07 04:52:14 PM PDT 24 |
Jul 07 04:52:15 PM PDT 24 |
103863972 ps |
| T82 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3309060478 |
|
|
Jul 07 04:52:06 PM PDT 24 |
Jul 07 04:52:07 PM PDT 24 |
23290391 ps |
| T946 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2977031284 |
|
|
Jul 07 04:52:01 PM PDT 24 |
Jul 07 04:52:07 PM PDT 24 |
157636613 ps |
| T114 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3647407895 |
|
|
Jul 07 04:52:10 PM PDT 24 |
Jul 07 04:52:12 PM PDT 24 |
73485021 ps |
| T947 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2251148369 |
|
|
Jul 07 04:52:27 PM PDT 24 |
Jul 07 04:52:31 PM PDT 24 |
151618295 ps |
| T83 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1038740075 |
|
|
Jul 07 04:52:05 PM PDT 24 |
Jul 07 04:52:06 PM PDT 24 |
33077521 ps |
| T84 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3213506395 |
|
|
Jul 07 04:51:56 PM PDT 24 |
Jul 07 04:51:59 PM PDT 24 |
232504539 ps |
| T85 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.352119604 |
|
|
Jul 07 04:51:59 PM PDT 24 |
Jul 07 04:52:00 PM PDT 24 |
21174508 ps |
| T69 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.723503747 |
|
|
Jul 07 04:52:25 PM PDT 24 |
Jul 07 04:52:27 PM PDT 24 |
589995389 ps |
| T70 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2457619110 |
|
|
Jul 07 04:52:24 PM PDT 24 |
Jul 07 04:52:27 PM PDT 24 |
259487596 ps |
| T86 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2804081391 |
|
|
Jul 07 04:52:22 PM PDT 24 |
Jul 07 04:52:48 PM PDT 24 |
3975486674 ps |
| T948 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1698199565 |
|
|
Jul 07 04:52:24 PM PDT 24 |
Jul 07 04:52:28 PM PDT 24 |
729844573 ps |
| T949 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3472501908 |
|
|
Jul 07 04:52:00 PM PDT 24 |
Jul 07 04:52:01 PM PDT 24 |
21194414 ps |
| T141 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3858394963 |
|
|
Jul 07 04:51:55 PM PDT 24 |
Jul 07 04:51:58 PM PDT 24 |
101803588 ps |
| T87 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3914830163 |
|
|
Jul 07 04:52:30 PM PDT 24 |
Jul 07 04:52:31 PM PDT 24 |
106530630 ps |
| T105 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.975018695 |
|
|
Jul 07 04:51:55 PM PDT 24 |
Jul 07 04:51:56 PM PDT 24 |
40056025 ps |
| T950 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2481258243 |
|
|
Jul 07 04:52:30 PM PDT 24 |
Jul 07 04:52:33 PM PDT 24 |
115888112 ps |
| T134 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3224898934 |
|
|
Jul 07 04:52:01 PM PDT 24 |
Jul 07 04:52:04 PM PDT 24 |
176221109 ps |
| T951 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.375580550 |
|
|
Jul 07 04:52:07 PM PDT 24 |
Jul 07 04:52:12 PM PDT 24 |
367535138 ps |
| T135 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1830624370 |
|
|
Jul 07 04:52:02 PM PDT 24 |
Jul 07 04:52:04 PM PDT 24 |
1327928205 ps |
| T88 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2416214357 |
|
|
Jul 07 04:52:08 PM PDT 24 |
Jul 07 04:52:09 PM PDT 24 |
17685333 ps |
| T952 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.236440924 |
|
|
Jul 07 04:51:57 PM PDT 24 |
Jul 07 04:52:01 PM PDT 24 |
363381265 ps |
| T106 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1911507751 |
|
|
Jul 07 04:52:03 PM PDT 24 |
Jul 07 04:53:00 PM PDT 24 |
14395221349 ps |
| T107 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1867626264 |
|
|
Jul 07 04:52:08 PM PDT 24 |
Jul 07 04:52:09 PM PDT 24 |
86554587 ps |
| T953 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3150897174 |
|
|
Jul 07 04:52:29 PM PDT 24 |
Jul 07 04:52:33 PM PDT 24 |
1419242757 ps |
| T137 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2812098657 |
|
|
Jul 07 04:52:09 PM PDT 24 |
Jul 07 04:52:12 PM PDT 24 |
253027753 ps |
| T954 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2032672577 |
|
|
Jul 07 04:52:15 PM PDT 24 |
Jul 07 04:52:19 PM PDT 24 |
110462020 ps |
| T955 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1406750243 |
|
|
Jul 07 04:52:14 PM PDT 24 |
Jul 07 04:52:15 PM PDT 24 |
16171350 ps |
| T956 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3791919455 |
|
|
Jul 07 04:52:07 PM PDT 24 |
Jul 07 04:52:07 PM PDT 24 |
37479602 ps |
| T957 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.91693770 |
|
|
Jul 07 04:52:02 PM PDT 24 |
Jul 07 04:52:03 PM PDT 24 |
19479303 ps |
| T958 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3435698294 |
|
|
Jul 07 04:52:15 PM PDT 24 |
Jul 07 04:52:16 PM PDT 24 |
92885008 ps |
| T959 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2221638968 |
|
|
Jul 07 04:52:17 PM PDT 24 |
Jul 07 04:52:19 PM PDT 24 |
45523685 ps |
| T960 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2013877488 |
|
|
Jul 07 04:52:12 PM PDT 24 |
Jul 07 04:52:13 PM PDT 24 |
46078985 ps |
| T961 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.722070518 |
|
|
Jul 07 04:52:01 PM PDT 24 |
Jul 07 04:52:07 PM PDT 24 |
498746792 ps |
| T89 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3579661173 |
|
|
Jul 07 04:52:22 PM PDT 24 |
Jul 07 04:53:27 PM PDT 24 |
70534487403 ps |
| T962 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.68950145 |
|
|
Jul 07 04:52:06 PM PDT 24 |
Jul 07 04:52:09 PM PDT 24 |
34955106 ps |
| T963 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3642485449 |
|
|
Jul 07 04:52:26 PM PDT 24 |
Jul 07 04:52:27 PM PDT 24 |
15136746 ps |
| T142 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2848452292 |
|
|
Jul 07 04:52:13 PM PDT 24 |
Jul 07 04:52:15 PM PDT 24 |
304886326 ps |
| T964 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3787821414 |
|
|
Jul 07 04:52:14 PM PDT 24 |
Jul 07 04:52:18 PM PDT 24 |
1442675830 ps |
| T965 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1469005068 |
|
|
Jul 07 04:51:56 PM PDT 24 |
Jul 07 04:52:55 PM PDT 24 |
29346489070 ps |
| T966 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2798691936 |
|
|
Jul 07 04:52:10 PM PDT 24 |
Jul 07 04:52:12 PM PDT 24 |
18527236 ps |
| T139 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3787800342 |
|
|
Jul 07 04:52:22 PM PDT 24 |
Jul 07 04:52:24 PM PDT 24 |
170631463 ps |
| T967 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2730982415 |
|
|
Jul 07 04:52:08 PM PDT 24 |
Jul 07 04:52:09 PM PDT 24 |
41989325 ps |
| T968 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3242308239 |
|
|
Jul 07 04:52:25 PM PDT 24 |
Jul 07 04:52:27 PM PDT 24 |
30535696 ps |
| T90 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2887597504 |
|
|
Jul 07 04:52:12 PM PDT 24 |
Jul 07 04:53:26 PM PDT 24 |
78209777349 ps |
| T969 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1749618873 |
|
|
Jul 07 04:52:01 PM PDT 24 |
Jul 07 04:52:03 PM PDT 24 |
129809011 ps |
| T970 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.501747760 |
|
|
Jul 07 04:52:04 PM PDT 24 |
Jul 07 04:52:05 PM PDT 24 |
16348814 ps |
| T971 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3990924352 |
|
|
Jul 07 04:52:00 PM PDT 24 |
Jul 07 04:52:01 PM PDT 24 |
33120811 ps |
| T972 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.4159944094 |
|
|
Jul 07 04:52:08 PM PDT 24 |
Jul 07 04:52:12 PM PDT 24 |
338842756 ps |
| T973 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1029426253 |
|
|
Jul 07 04:51:57 PM PDT 24 |
Jul 07 04:51:58 PM PDT 24 |
33614370 ps |
| T974 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3174165879 |
|
|
Jul 07 04:52:20 PM PDT 24 |
Jul 07 04:52:21 PM PDT 24 |
36381727 ps |
| T975 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.4141133569 |
|
|
Jul 07 04:52:10 PM PDT 24 |
Jul 07 04:52:13 PM PDT 24 |
77413840 ps |
| T976 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2802951909 |
|
|
Jul 07 04:51:55 PM PDT 24 |
Jul 07 04:51:56 PM PDT 24 |
25879651 ps |
| T977 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.921387580 |
|
|
Jul 07 04:52:01 PM PDT 24 |
Jul 07 04:52:03 PM PDT 24 |
123139028 ps |
| T978 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1158865304 |
|
|
Jul 07 04:52:05 PM PDT 24 |
Jul 07 04:52:07 PM PDT 24 |
194833475 ps |
| T140 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1168024514 |
|
|
Jul 07 04:52:08 PM PDT 24 |
Jul 07 04:52:11 PM PDT 24 |
197509171 ps |
| T91 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.477785738 |
|
|
Jul 07 04:52:26 PM PDT 24 |
Jul 07 04:52:54 PM PDT 24 |
4270587919 ps |
| T979 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.412704558 |
|
|
Jul 07 04:51:56 PM PDT 24 |
Jul 07 04:51:57 PM PDT 24 |
26373938 ps |
| T980 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2512049147 |
|
|
Jul 07 04:52:12 PM PDT 24 |
Jul 07 04:52:16 PM PDT 24 |
1622357433 ps |
| T981 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3208029441 |
|
|
Jul 07 04:52:15 PM PDT 24 |
Jul 07 04:52:16 PM PDT 24 |
41536053 ps |
| T92 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3149776333 |
|
|
Jul 07 04:51:57 PM PDT 24 |
Jul 07 04:51:58 PM PDT 24 |
35346756 ps |
| T982 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2379630623 |
|
|
Jul 07 04:52:15 PM PDT 24 |
Jul 07 04:52:19 PM PDT 24 |
2108141285 ps |
| T93 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1909999350 |
|
|
Jul 07 04:52:01 PM PDT 24 |
Jul 07 04:52:33 PM PDT 24 |
14744797604 ps |
| T983 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1105364293 |
|
|
Jul 07 04:52:01 PM PDT 24 |
Jul 07 04:52:02 PM PDT 24 |
141533285 ps |
| T984 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1287001262 |
|
|
Jul 07 04:52:17 PM PDT 24 |
Jul 07 04:52:47 PM PDT 24 |
61609195177 ps |
| T98 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2983568430 |
|
|
Jul 07 04:51:56 PM PDT 24 |
Jul 07 04:51:57 PM PDT 24 |
41971870 ps |
| T102 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1090579414 |
|
|
Jul 07 04:52:03 PM PDT 24 |
Jul 07 04:52:04 PM PDT 24 |
16568089 ps |
| T136 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2229345844 |
|
|
Jul 07 04:52:01 PM PDT 24 |
Jul 07 04:52:05 PM PDT 24 |
284402628 ps |
| T99 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3616813717 |
|
|
Jul 07 04:52:03 PM PDT 24 |
Jul 07 04:52:52 PM PDT 24 |
7066689056 ps |
| T985 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1251633605 |
|
|
Jul 07 04:52:30 PM PDT 24 |
Jul 07 04:52:35 PM PDT 24 |
821404832 ps |
| T986 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3120906572 |
|
|
Jul 07 04:52:22 PM PDT 24 |
Jul 07 04:52:25 PM PDT 24 |
28311683 ps |
| T103 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2339538166 |
|
|
Jul 07 04:51:56 PM PDT 24 |
Jul 07 04:52:25 PM PDT 24 |
36918679081 ps |
| T100 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1799643081 |
|
|
Jul 07 04:52:03 PM PDT 24 |
Jul 07 04:52:50 PM PDT 24 |
8747803364 ps |
| T987 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1275753944 |
|
|
Jul 07 04:52:01 PM PDT 24 |
Jul 07 04:52:02 PM PDT 24 |
155007365 ps |
| T988 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2507131704 |
|
|
Jul 07 04:52:22 PM PDT 24 |
Jul 07 04:52:23 PM PDT 24 |
18175768 ps |
| T101 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1385813542 |
|
|
Jul 07 04:52:26 PM PDT 24 |
Jul 07 04:52:27 PM PDT 24 |
13045095 ps |
| T989 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3718415951 |
|
|
Jul 07 04:52:27 PM PDT 24 |
Jul 07 04:52:28 PM PDT 24 |
47598236 ps |
| T990 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3961580519 |
|
|
Jul 07 04:52:09 PM PDT 24 |
Jul 07 04:52:13 PM PDT 24 |
703516028 ps |
| T991 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3742533837 |
|
|
Jul 07 04:52:22 PM PDT 24 |
Jul 07 04:52:26 PM PDT 24 |
143920247 ps |
| T992 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1553896021 |
|
|
Jul 07 04:52:18 PM PDT 24 |
Jul 07 04:52:20 PM PDT 24 |
324784515 ps |
| T993 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.4012840822 |
|
|
Jul 07 04:52:10 PM PDT 24 |
Jul 07 04:52:12 PM PDT 24 |
34706446 ps |
| T994 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.4153832668 |
|
|
Jul 07 04:52:02 PM PDT 24 |
Jul 07 04:52:04 PM PDT 24 |
169415768 ps |
| T995 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2231238000 |
|
|
Jul 07 04:52:04 PM PDT 24 |
Jul 07 04:52:08 PM PDT 24 |
349701703 ps |
| T996 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.723603905 |
|
|
Jul 07 04:52:10 PM PDT 24 |
Jul 07 04:52:12 PM PDT 24 |
15800244 ps |
| T997 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1624780503 |
|
|
Jul 07 04:52:04 PM PDT 24 |
Jul 07 04:52:58 PM PDT 24 |
29463032810 ps |
| T998 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1284791652 |
|
|
Jul 07 04:52:22 PM PDT 24 |
Jul 07 04:52:23 PM PDT 24 |
23220745 ps |
| T143 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.337783646 |
|
|
Jul 07 04:52:08 PM PDT 24 |
Jul 07 04:52:10 PM PDT 24 |
1024848692 ps |
| T999 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2213973390 |
|
|
Jul 07 04:52:12 PM PDT 24 |
Jul 07 04:52:16 PM PDT 24 |
718611593 ps |
| T1000 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.360300719 |
|
|
Jul 07 04:52:17 PM PDT 24 |
Jul 07 04:52:21 PM PDT 24 |
561868854 ps |
| T1001 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1565238596 |
|
|
Jul 07 04:52:29 PM PDT 24 |
Jul 07 04:52:30 PM PDT 24 |
19613322 ps |
| T1002 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2098614075 |
|
|
Jul 07 04:52:22 PM PDT 24 |
Jul 07 04:52:26 PM PDT 24 |
689597091 ps |
| T1003 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3958669685 |
|
|
Jul 07 04:51:55 PM PDT 24 |
Jul 07 04:51:59 PM PDT 24 |
35636906 ps |