Group : cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
80.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_errors_cgs_wrap[sram_ctrl_prim_reg_block] 100.00 1 100 1 64 64
tl_errors_cgs_wrap[sram_ctrl_regs_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_errors_cgs_wrap[sram_ctrl_prim_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_errors_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 15 5 10 100.00


Variables for Group Instance tl_errors_cgs_wrap[sram_ctrl_prim_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_csr_size_err 2 1 1 50.00 100 0 0 2
cp_instr_type_err 2 0 2 100.00 100 1 1 2
cp_mem_byte_access_err 2 1 1 50.00 100 0 0 2
cp_mem_ro_err 2 1 1 50.00 100 0 0 2
cp_mem_wo_err 2 1 1 50.00 100 0 0 2
cp_tl_protocol_err 1 0 1 100.00 100 1 1 0
cp_unmapped_err 2 1 1 50.00 100 0 0 2
cp_write_w_instr_type_err 2 0 2 100.00 100 1 1 2



Group Instance : tl_errors_cgs_wrap[sram_ctrl_regs_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_errors_cgs_wrap[sram_ctrl_regs_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 15 3 12 100.00


Variables for Group Instance tl_errors_cgs_wrap[sram_ctrl_regs_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_csr_size_err 2 0 2 100.00 100 1 1 2
cp_instr_type_err 2 0 2 100.00 100 1 1 2
cp_mem_byte_access_err 2 1 1 50.00 100 0 0 2
cp_mem_ro_err 2 1 1 50.00 100 0 0 2
cp_mem_wo_err 2 1 1 50.00 100 0 0 2
cp_tl_protocol_err 1 0 1 100.00 100 1 1 0
cp_unmapped_err 2 0 2 100.00 100 1 1 2
cp_write_w_instr_type_err 2 0 2 100.00 100 1 1 2


Summary for Variable cp_csr_size_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_csr_size_err

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
[auto[1]] 0 0 - - - - - -
auto[0] 10762749 0 T2 47979 T3 6920 T12 138358



Summary for Variable cp_instr_type_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_instr_type_err

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5526651 1 T2 24124 T3 5494 T12 69031
auto[1] 5236098 1 T2 23855 T3 1426 T12 69327



Summary for Variable cp_mem_byte_access_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_mem_byte_access_err

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
[auto[1]] 0 0 - - - - - -
auto[0] 10762749 0 T2 47979 T3 6920 T12 138358



Summary for Variable cp_mem_ro_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_mem_ro_err

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
[auto[1]] 0 0 - - - - - -
auto[0] 10762749 0 T2 47979 T3 6920 T12 138358



Summary for Variable cp_mem_wo_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_mem_wo_err

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
[auto[1]] 0 0 - - - - - -
auto[0] 10762749 0 T2 47979 T3 6920 T12 138358



Summary for Variable cp_tl_protocol_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_tl_protocol_err

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
covered 287422 1 T3 4107 T26 5755 T27 2992



Summary for Variable cp_unmapped_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_unmapped_err

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
[auto[1]] 0 0 - - - - - -
auto[0] 10762749 0 T2 47979 T3 6920 T12 138358



Summary for Variable cp_write_w_instr_type_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write_w_instr_type_err

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5523713 1 T2 23855 T3 5533 T12 69327
auto[1] 5239036 1 T2 24124 T3 1387 T12 69031


Summary for Variable cp_csr_size_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_csr_size_err

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 150075 1 T3 1724 T26 3242 T27 1872
auto[1] 4137 1 T3 40 T26 89 T27 54



Summary for Variable cp_instr_type_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_instr_type_err

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 108809 1 T3 1128 T26 2451 T27 1312
auto[1] 45403 1 T3 636 T26 880 T27 614



Summary for Variable cp_mem_byte_access_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_mem_byte_access_err

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
[auto[1]] 0 0 - - - - - -
auto[0] 154212 0 T3 1764 T26 3331 T27 1926



Summary for Variable cp_mem_ro_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_mem_ro_err

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
[auto[1]] 0 0 - - - - - -
auto[0] 154212 0 T3 1764 T26 3331 T27 1926



Summary for Variable cp_mem_wo_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_mem_wo_err

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
[auto[1]] 0 0 - - - - - -
auto[0] 154212 0 T3 1764 T26 3331 T27 1926



Summary for Variable cp_tl_protocol_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_tl_protocol_err

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
covered 54297 1 T3 386 T26 1342 T27 596



Summary for Variable cp_unmapped_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_unmapped_err

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 149535 1 T3 1725 T26 3244 T27 1844
auto[1] 4677 1 T3 39 T26 87 T27 82



Summary for Variable cp_write_w_instr_type_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write_w_instr_type_err

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 108602 1 T3 1101 T26 2398 T27 1346
auto[1] 45610 1 T3 663 T26 933 T27 580

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%